Aseda Aboagye abd7e7d582 g: Change rdd 0.4V ref to 0.3V. ...

On some boards, it was seen that SuzyQable wasn't detected by the rdd
block.  The voltage around 0.4V is marginal with a Vbus around 4.75V.
This commit simply adjust the 0.4V comparator reference voltage to 0.3V
in order to make the detection work.

BUG=b:64847312
BRANCH=cr50
TEST=Find a soraka where SuzyQable didn't work.  Verify with this patch,
it does work.  Additionally, verify that servo_v4 continues works.

Change-Id: If54630ec469408031cd84ffb93ef5fea42bdee3b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/633403
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>

2017-08-24 17:20:41 -07:00

..

dcrypto

Fix compilation with coreboot-sdk

2017-08-04 18:08:16 -07:00

loader

chip/g to chip/lm4: fix more misspellings in comments

2016-11-15 17:41:55 -08:00

blob.c

cr50: add support for creating multiple serial endpoints

2016-04-07 13:00:39 -07:00

board_id.c

g: add a function to report current board ID mismatch status

2017-06-15 20:13:51 -07:00

board_id.h

g: add a function to report current board ID mismatch status

2017-06-15 20:13:51 -07:00

build.mk

g: Move chip pre-init to chip_pre_init()

2017-08-24 11:29:02 -07:00

clock.c

cr50: add basic rbox support

2016-04-29 16:07:13 -07:00

config_chip.h

g: Move chip pre-init to chip_pre_init()

2017-08-24 11:29:02 -07:00

crypto_api.c

g: rework DCRYPTO_app_cipher (AES-CTR) for speed

2017-01-28 21:37:58 -08:00

flash_config.h

chip/g to chip/lm4: fix more misspellings in comments

2016-11-15 17:41:55 -08:00

flash_info.h

cr50: Add console and TPM vendor commands to get/set board ID

2017-06-02 16:59:33 -07:00

flash.c

g: expose API to unlock secondary RO area

2017-03-21 23:15:07 -07:00

gpio.c

g: don't enable interrupts in gpio_set_flags_by_mask

2017-06-13 15:12:33 -07:00

hw_regdefs.h

cr50: integrate register definitions consistent with real silicon

2016-02-09 01:26:06 -08:00

hwtimer.c

g: hwtimer: Improve accuracy of hwtimer and ensure minimum udelay() wait

2017-07-21 21:24:12 -07:00

i2cm.c

chip/g to chip/lm4: fix more misspellings in comments

2016-11-15 17:41:55 -08:00

i2cs.c

cr50: log I2C slave 'wedged bus recovery' event

2017-08-23 12:19:07 -07:00

i2cs.h

g: add 'recover hosed slave' i2cs capability

2017-08-17 20:41:57 -07:00

idle.c

cr50: Remove BOARD_AP_USB property

2017-08-17 01:56:48 -07:00

init_chip.h

g: add deep sleep counter to idle.c

2017-03-07 00:34:07 -08:00

jitter.c

g: add permission level checks

2016-11-04 18:31:44 -07:00

jtag.c

g: Move chip pre-init to chip_pre_init()

2017-08-24 11:29:02 -07:00

pmu.c

cr50: drop obsolete/addressed TODOs

2017-05-16 13:37:03 -07:00

pmu.h

Cr50: Fixed soft resets on silicon.

2016-02-01 21:17:22 +00:00

polling_uart.c

cr50: add polling uart implementation

2015-08-11 02:58:39 +00:00

post_reset.c

mn50: fix usb_update

2017-06-16 17:24:28 -07:00

pre_init.c

g: Move chip pre-init to chip_pre_init()

2017-08-24 11:29:02 -07:00

rbox.c

g: rbox: Let pins stabilize before releasing EC.

2017-03-31 12:59:16 -07:00

rbox.h

cr50: add press and release options to powerbtn command

2016-10-11 01:48:21 -07:00

rdd.c

g: Change rdd 0.4V ref to 0.3V.

2017-08-24 17:20:41 -07:00

rdd.h

cr50: Refactor Rdd state machine

2017-08-23 17:01:21 -07:00

registers.h

CR50: add a hardware backed GCM implementation

2017-01-27 03:50:47 -08:00

runlevel.c

g: add permission level checks

2016-11-04 18:31:44 -07:00

signed_header.h

cr50: Add console and TPM vendor commands to get/set board ID

2017-06-02 16:59:33 -07:00

spi_master.c

mn50: initial checkin

2017-05-12 03:25:39 -07:00

spi_master.h

Cr50: Export the chip-specific SPI master functions

2016-05-31 22:16:42 +00:00

sps_tpm.c

cr50: provide chip factory mode support

2017-07-30 22:41:06 -07:00

sps.c

g: fix sps interrupt assertion logic

2017-03-10 08:34:22 -08:00

sps.h

chip/g to chip/lm4: fix more misspellings in comments

2016-11-15 17:41:55 -08:00

system_chip.h

g: cr50: update INFO1 mask when corrupting the second image

2017-06-21 18:48:05 -07:00

system.c

g: cr50: update INFO1 mask when corrupting the second image

2017-06-21 18:48:05 -07:00

trng.c

Cr50: Ensure that trng.h is self-contained.

2016-12-08 19:49:53 -08:00

uart_bitbang.c

g: uart_bitbang: Keep debug stuff off by default.

2017-06-07 23:45:30 -07:00

uart_bitbang.h

chip: g: Add support for UART bit banging.

2017-06-05 14:49:09 -07:00

uart.c

g: disable uart 1 and 2 during init

2016-07-13 19:09:19 -07:00

uartn.c

cr50: CCD V1 controls UART access

2017-08-01 13:01:41 -07:00

uartn.h

cr50: CCD V1 controls UART access

2017-08-01 13:01:41 -07:00

upgrade_fw.c

g: upgrade_fw: limit updates after a hard reset

2017-06-19 15:33:13 -07:00

upgrade_fw.h

cr50: drop obsolete/addressed TODOs

2017-05-16 13:37:03 -07:00

upgrade.c

mn50: fix usb_update

2017-06-16 17:24:28 -07:00

usart.c

mn50: initial checkin

2017-05-12 03:25:39 -07:00

usart.h

cr50: use RXILVL to trigger fewer UART RXINTs

2016-09-23 12:22:06 -07:00

usb_console.c

usb: Cleanup headers

2017-03-16 11:25:50 -07:00

usb_endpoints.S

cr50: add USB support

2015-04-02 20:27:46 +00:00

usb_hid_keyboard.c

chip/stm32/usb_hid: Separate HID keyboard support

2016-11-16 19:04:47 -08:00

usb_hw.h

Fixup usb_updater for reef/clang

2016-10-22 00:01:02 +00:00

usb_spi.c

cr50: CCD V1 controls SPI access

2017-07-28 22:07:57 -07:00

usb_spi.h

cr50: CCD V1 controls SPI access

2017-07-28 22:07:57 -07:00

usb_upgrade.c

cr50: usb_upgrade: allow responses lager than requests

2017-06-06 14:36:28 -07:00

usb-stream.c

g: check that the rx fifo is ready before reading from it

2016-10-13 04:32:11 -07:00

usb-stream.h

usb: Cleanup headers

2017-03-16 11:25:50 -07:00

usb.c

cr50: add delay after soft reset

2017-08-17 20:41:56 -07:00

watchdog.c

watchdog: Don't discard irqprio data due to CONFIG_LTO

2017-06-26 11:12:07 -07:00