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If the power button is pressed for a shorter period than the debounce timeout, then the debounced state never changes. This was causing the power button state machine to disable scanning (in the interrupt handler) but never re-enable it (in the deferred handler). Easy fix; just re-enable based on whether the current state is released, not whether the debounced state is transitioning to released. BUG=chrome-os-partner:21772 BRANCH=all (falco, pit, etc.) TEST=type on console. briefly flick power button. type more; should work. Change-Id: I9723a6aa10f122fcee62702b85ce7981b1c8103a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65238 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
In the most general case, the flash layout looks something like this: +---------------------+ | Reserved for EC use | +---------------------+ +---------------------+ | Vblock B | +---------------------+ | RW firmware B | +---------------------+ +---------------------+ | Vblock A | +---------------------+ | RW firmware A | +---------------------+ +---------------------+ | FMAP | +---------------------+ | Public root key | +---------------------+ | Read-only firmware | +---------------------+ BIOS firmware (and kernel) put the vblock info at the start of each image where it's easy to find. The Blizzard EC expects the firmware vector table to come first, so we have to put the vblock at the end. This means we have to know where to look for it, but that's built into the FMAP and the RO firmware anyway, so that's not an issue. The RO firmware doesn't need a vblock of course, but it does need some reserved space for vboot-related things. Using SHA256/RSA4096, the vblock is 2468 bytes (0x9a4), while the public root key is 1064 bytes (0x428) and the current FMAP is 644 bytes (0x284). If we reserve 4K at the top of each FW image, that should give us plenty of room for vboot-related stuff.