Merge pull request #510 from yhwu5/add_inventec_d5264q28b

Add new platform for Inventec d5264q28b and support onlp

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/.gitignore

@@ -0,0 +1,2 @@
+*x86*64*inventec*d5264q28b*.mk
+onlpdump.mk

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/Makefile

@@ -0,0 +1 @@
+include $(ONL)/make/pkg.mk

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/modules/Makefile

@@ -0,0 +1 @@
+include $(ONL)/make/pkg.mk

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/modules/PKG.yml

@@ -0,0 +1 @@
+!include $ONL_TEMPLATES/platform-modules.yml VENDOR=inventec BASENAME=x86-64-inventec-d5264q28b ARCH=amd64 KERNELS="onl-kernel-3.16-lts-x86-64-all:amd64"

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/modules/builds/.gitignore

@@ -0,0 +1 @@
+lib

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/modules/builds/Makefile

@@ -0,0 +1,6 @@
+KERNELS := onl-kernel-3.16-lts-x86-64-all:amd64
+KMODULES := src
+VENDOR := inventec
+BASENAME := x86-64-inventec-d5264q28b
+ARCH := x86_64
+include $(ONL)/make/kmodule.mk

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/modules/builds/src/Makefile

@@ -0,0 +1,10 @@
+#obj-m += gpio-ich.o
+obj-m += inv_cpld.o
+obj-m += inv_mux.o
+obj-m += inv_platform.o
+obj-m += inv_psoc.o
+obj-m += inv_swps.o
+obj-m += inv_vpd.o
+obj-m += io_expander.o
+obj-m += onie_tlvinfo.o
+obj-m += transceiver.o

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/modules/builds/src/gpio-ich.c

@@ -0,0 +1,548 @@
+/*
+ * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
+ *
+ * Copyright (C) 2010 Extreme Engineering Solutions.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/lpc_ich.h>
+
+#define DRV_NAME "gpio_ich"
+
+/*
+ * GPIO register offsets in GPIO I/O space.
+ * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
+ * LVLx registers.  Logic in the read/write functions takes a register and
+ * an absolute bit number and determines the proper register offset and bit
+ * number in that register.  For example, to read the value of GPIO bit 50
+ * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
+ * bit 18 (50%32).
+ */
+enum GPIO_REG {
+	GPIO_USE_SEL = 0,
+	GPIO_IO_SEL,
+	GPIO_LVL,
+	GPO_BLINK
+};
+
+static const u8 ichx_regs[4][3] = {
+	{0x00, 0x30, 0x40},	/* USE_SEL[1-3] offsets */
+	{0x04, 0x34, 0x44},	/* IO_SEL[1-3] offsets */
+	{0x0c, 0x38, 0x48},	/* LVL[1-3] offsets */
+	{0x18, 0x18, 0x18},	/* BLINK offset */
+};
+
+static const u8 ichx_reglen[3] = {
+	0x30, 0x10, 0x10,
+};
+
+static const u8 avoton_regs[4][3] = {
+	{0x00, 0x80, 0x00},
+	{0x04, 0x84, 0x00},
+	{0x08, 0x88, 0x00},
+};
+
+static const u8 avoton_reglen[3] = {
+	0x10, 0x10, 0x00,
+};
+
+#define ICHX_WRITE(val, reg, base_res)	outl(val, (reg) + (base_res)->start)
+#define ICHX_READ(reg, base_res)	inl((reg) + (base_res)->start)
+
+struct ichx_desc {
+	/* Max GPIO pins the chipset can have */
+	uint ngpio;
+
+	/* chipset registers */
+	const u8 (*regs)[3];
+	const u8 *reglen;
+
+	/* GPO_BLINK is available on this chipset */
+	bool have_blink;
+
+	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
+	bool uses_gpe0;
+
+	/* USE_SEL is bogus on some chipsets, eg 3100 */
+	u32 use_sel_ignore[3];
+
+	/* Some chipsets have quirks, let these use their own request/get */
+	int (*request)(struct gpio_chip *chip, unsigned offset);
+	int (*get)(struct gpio_chip *chip, unsigned offset);
+
+	/*
+	 * Some chipsets don't let reading output values on GPIO_LVL register
+	 * this option allows driver caching written output values
+	 */
+	bool use_outlvl_cache;
+};
+
+static struct {
+	spinlock_t lock;
+	struct platform_device *dev;
+	struct gpio_chip chip;
+	struct resource *gpio_base;	/* GPIO IO base */
+	struct resource *pm_base;	/* Power Mangagment IO base */
+	struct ichx_desc *desc;	/* Pointer to chipset-specific description */
+	u32 orig_gpio_ctrl;	/* Orig CTRL value, used to restore on exit */
+	u8 use_gpio;		/* Which GPIO groups are usable */
+	int outlvl_cache[3];	/* cached output values */
+} ichx_priv;
+
+static int modparam_gpiobase = -1;	/* dynamic */
+module_param_named(gpiobase, modparam_gpiobase, int, 0444);
+MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
+			   "which is the default.");
+
+static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
+{
+	unsigned long flags;
+	u32 data, tmp;
+	int reg_nr = nr / 32;
+	int bit = nr & 0x1f;
+	int ret = 0;
+
+	spin_lock_irqsave(&ichx_priv.lock, flags);
+
+	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
+		data = ichx_priv.outlvl_cache[reg_nr];
+	else
+		data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
+				 ichx_priv.gpio_base);
+
+	if (val)
+		data |= 1 << bit;
+	else
+		data &= ~(1 << bit);
+	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
+			 ichx_priv.gpio_base);
+	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
+		ichx_priv.outlvl_cache[reg_nr] = data;
+
+	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
+			ichx_priv.gpio_base);
+	if (verify && data != tmp)
+		ret = -EPERM;
+
+	spin_unlock_irqrestore(&ichx_priv.lock, flags);
+
+	return ret;
+}
+
+static int ichx_read_bit(int reg, unsigned nr)
+{
+	unsigned long flags;
+	u32 data;
+	int reg_nr = nr / 32;
+	int bit = nr & 0x1f;
+
+	spin_lock_irqsave(&ichx_priv.lock, flags);
+
+	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
+			 ichx_priv.gpio_base);
+
+	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
+		data = ichx_priv.outlvl_cache[reg_nr] | data;
+
+	spin_unlock_irqrestore(&ichx_priv.lock, flags);
+
+	return data & (1 << bit) ? 1 : 0;
+}
+
+static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
+{
+	return !!(ichx_priv.use_gpio & (1 << (nr / 32)));
+}
+
+static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
+{
+	/*
+	 * Try setting pin as an input and verify it worked since many pins
+	 * are output-only.
+	 */
+	if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
+					int val)
+{
+	/* Disable blink hardware which is available for GPIOs from 0 to 31. */
+	if (nr < 32 && ichx_priv.desc->have_blink)
+		ichx_write_bit(GPO_BLINK, nr, 0, 0);
+
+	/* Set GPIO output value. */
+	ichx_write_bit(GPIO_LVL, nr, val, 0);
+
+	/*
+	 * Try setting pin as an output and verify it worked since many pins
+	 * are input-only.
+	 */
+	if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
+{
+	return ichx_read_bit(GPIO_LVL, nr);
+}
+
+static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
+{
+	unsigned long flags;
+	u32 data;
+
+	/*
+	 * GPI 0 - 15 need to be read from the power management registers on
+	 * a ICH6/3100 bridge.
+	 */
+	if (nr < 16) {
+		if (!ichx_priv.pm_base)
+			return -ENXIO;
+
+		spin_lock_irqsave(&ichx_priv.lock, flags);
+
+		/* GPI 0 - 15 are latched, write 1 to clear*/
+		ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);
+		data = ICHX_READ(0, ichx_priv.pm_base);
+
+		spin_unlock_irqrestore(&ichx_priv.lock, flags);
+
+		return (data >> 16) & (1 << nr) ? 1 : 0;
+	} else {
+		return ichx_gpio_get(chip, nr);
+	}
+}
+
+static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
+{
+	if (!ichx_gpio_check_available(chip, nr))
+		return -ENXIO;
+
+	/*
+	 * Note we assume the BIOS properly set a bridge's USE value.  Some
+	 * chips (eg Intel 3100) have bogus USE values though, so first see if
+	 * the chipset's USE value can be trusted for this specific bit.
+	 * If it can't be trusted, assume that the pin can be used as a GPIO.
+	 */
+	if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
+		return 0;
+
+	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
+}
+
+static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
+{
+	/*
+	 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
+	 * bridge as they are controlled by USE register bits 0 and 1.  See
+	 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
+	 * additional info.
+	 */
+	if (nr == 16 || nr == 17)
+		nr -= 16;
+
+	return ichx_gpio_request(chip, nr);
+}
+
+static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
+{
+	ichx_write_bit(GPIO_LVL, nr, val, 0);
+}
+
+static void ichx_gpiolib_setup(struct gpio_chip *chip)
+{
+	chip->owner = THIS_MODULE;
+	chip->label = DRV_NAME;
+	chip->dev = &ichx_priv.dev->dev;
+
+	/* Allow chip-specific overrides of request()/get() */
+	chip->request = ichx_priv.desc->request ?
+		ichx_priv.desc->request : ichx_gpio_request;
+	chip->get = ichx_priv.desc->get ?
+		ichx_priv.desc->get : ichx_gpio_get;
+
+	chip->set = ichx_gpio_set;
+	chip->direction_input = ichx_gpio_direction_input;
+	chip->direction_output = ichx_gpio_direction_output;
+	chip->base = modparam_gpiobase;
+	chip->ngpio = ichx_priv.desc->ngpio;
+	chip->can_sleep = false;
+	chip->dbg_show = NULL;
+}
+
+/* ICH6-based, 631xesb-based */
+static struct ichx_desc ich6_desc = {
+	/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
+	.request = ich6_gpio_request,
+	.get = ich6_gpio_get,
+
+	/* GPIO 0-15 are read in the GPE0_STS PM register */
+	.uses_gpe0 = true,
+
+	.ngpio = 50,
+	.have_blink = true,
+	.regs = ichx_regs,
+	.reglen = ichx_reglen,
+};
+
+/* Intel 3100 */
+static struct ichx_desc i3100_desc = {
+	/*
+	 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
+	 * the Intel 3100.  See "Table 712. GPIO Summary Table" of 3100
+	 * Datasheet for more info.
+	 */
+	.use_sel_ignore = {0x00130000, 0x00010000, 0x0},
+
+	/* The 3100 needs fixups for GPIO 0 - 17 */
+	.request = ich6_gpio_request,
+	.get = ich6_gpio_get,
+
+	/* GPIO 0-15 are read in the GPE0_STS PM register */
+	.uses_gpe0 = true,
+
+	.ngpio = 50,
+	.regs = ichx_regs,
+	.reglen = ichx_reglen,
+};
+
+/* ICH7 and ICH8-based */
+static struct ichx_desc ich7_desc = {
+	.ngpio = 50,
+	.have_blink = true,
+	.regs = ichx_regs,
+	.reglen = ichx_reglen,
+};
+
+/* ICH9-based */
+static struct ichx_desc ich9_desc = {
+	.ngpio = 61,
+	.have_blink = true,
+	.regs = ichx_regs,
+	.reglen = ichx_reglen,
+};
+
+/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
+static struct ichx_desc ich10_cons_desc = {
+	.ngpio = 61,
+	.have_blink = true,
+	.regs = ichx_regs,
+	.reglen = ichx_reglen,
+};
+static struct ichx_desc ich10_corp_desc = {
+	.ngpio = 72,
+	.have_blink = true,
+	.regs = ichx_regs,
+	.reglen = ichx_reglen,
+};
+
+/* Intel 5 series, 6 series, 3400 series, and C200 series */
+static struct ichx_desc intel5_desc = {
+	.ngpio = 76,
+	.regs = ichx_regs,
+	.reglen = ichx_reglen,
+};
+
+/* Avoton */
+static struct ichx_desc avoton_desc = {
+	/* Avoton has only 59 GPIOs, but we assume the first set of register
+	 * (Core) has 32 instead of 31 to keep gpio-ich compliance
+	 */
+	.ngpio = 60,
+	.regs = avoton_regs,
+	.reglen = avoton_reglen,
+	.use_outlvl_cache = true,
+};
+
+static int ichx_gpio_request_regions(struct resource *res_base,
+						const char *name, u8 use_gpio)
+{
+	int i;
+
+	if (!res_base || !res_base->start || !res_base->end)
+		return -ENODEV;
+
+	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
+		if (!(use_gpio & (1 << i)))
+			continue;
+		if (!request_region(
+				res_base->start + ichx_priv.desc->regs[0][i],
+				ichx_priv.desc->reglen[i], name))
+			goto request_err;
+	}
+	return 0;
+
+request_err:
+	/* Clean up: release already requested regions, if any */
+	for (i--; i >= 0; i--) {
+		if (!(use_gpio & (1 << i)))
+			continue;
+		release_region(res_base->start + ichx_priv.desc->regs[0][i],
+			       ichx_priv.desc->reglen[i]);
+	}
+	return -EBUSY;
+}
+
+static void ichx_gpio_release_regions(struct resource *res_base, u8 use_gpio)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
+		if (!(use_gpio & (1 << i)))
+			continue;
+		release_region(res_base->start + ichx_priv.desc->regs[0][i],
+			       ichx_priv.desc->reglen[i]);
+	}
+}
+
+static int ichx_gpio_probe(struct platform_device *pdev)
+{
+	struct resource *res_base, *res_pm;
+	int err;
+	struct lpc_ich_info *ich_info = dev_get_platdata(&pdev->dev);
+
+	if (!ich_info)
+		return -ENODEV;
+
+	ichx_priv.dev = pdev;
+
+	switch (ich_info->gpio_version) {
+	case ICH_I3100_GPIO:
+		ichx_priv.desc = &i3100_desc;
+		break;
+	case ICH_V5_GPIO:
+		ichx_priv.desc = &intel5_desc;
+		break;
+	case ICH_V6_GPIO:
+		ichx_priv.desc = &ich6_desc;
+		break;
+	case ICH_V7_GPIO:
+		ichx_priv.desc = &ich7_desc;
+		break;
+	case ICH_V9_GPIO:
+		ichx_priv.desc = &ich9_desc;
+		break;
+	case ICH_V10CORP_GPIO:
+		ichx_priv.desc = &ich10_corp_desc;
+		break;
+	case ICH_V10CONS_GPIO:
+		ichx_priv.desc = &ich10_cons_desc;
+		break;
+	case AVOTON_GPIO:
+		ichx_priv.desc = &avoton_desc;
+		break;
+	default:
+		return -ENODEV;
+	}
+
+	spin_lock_init(&ichx_priv.lock);
+	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
+	ichx_priv.use_gpio = ich_info->use_gpio;
+	err = ichx_gpio_request_regions(res_base, pdev->name,
+					ichx_priv.use_gpio);
+	if (err)
+		return err;
+
+	ichx_priv.gpio_base = res_base;
+
+	/*
+	 * If necessary, determine the I/O address of ACPI/power management
+	 * registers which are needed to read the the GPE0 register for GPI pins
+	 * 0 - 15 on some chipsets.
+	 */
+	if (!ichx_priv.desc->uses_gpe0)
+		goto init;
+
+	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
+	if (!res_pm) {
+		pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
+		goto init;
+	}
+
+	if (!request_region(res_pm->start, resource_size(res_pm),
+			pdev->name)) {
+		pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
+		goto init;
+	}
+
+	ichx_priv.pm_base = res_pm;
+
+init:
+	ichx_gpiolib_setup(&ichx_priv.chip);
+	err = gpiochip_add(&ichx_priv.chip);
+	if (err) {
+		pr_err("Failed to register GPIOs\n");
+		goto add_err;
+	}
+
+	pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
+	       ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);
+
+	return 0;
+
+add_err:
+	ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
+	if (ichx_priv.pm_base)
+		release_region(ichx_priv.pm_base->start,
+				resource_size(ichx_priv.pm_base));
+	return err;
+}
+
+static int ichx_gpio_remove(struct platform_device *pdev)
+{
+	int err;
+
+	err = gpiochip_remove(&ichx_priv.chip);
+	if (err) {
+		dev_err(&pdev->dev, "%s failed, %d\n",
+				"gpiochip_remove()", err);
+		return err;
+	}
+
+	ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
+	if (ichx_priv.pm_base)
+		release_region(ichx_priv.pm_base->start,
+				resource_size(ichx_priv.pm_base));
+
+	return 0;
+}
+
+static struct platform_driver ichx_gpio_driver = {
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= DRV_NAME,
+	},
+	.probe		= ichx_gpio_probe,
+	.remove		= ichx_gpio_remove,
+};
+
+module_platform_driver(ichx_gpio_driver);
+
+MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
+MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:"DRV_NAME);

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/modules/builds/src/inv_cpld.c

@@ -0,0 +1,463 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/jiffies.h>
+#include <linux/i2c.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/err.h>
+#include <linux/mutex.h>
+
+//#include "I2CHostCommunication.h"
+
+#define USE_SMBUS    1
+
+/* definition */
+#define CPLD_INFO_OFFSET   0x00
+#define CPLD_PSU_OFFSET    0x08
+#define CPLD_LED_OFFSET    0x0E
+#define CPLD_LED_STATU_OFFSET    0x0D
+#define CPLD_CTL_OFFSET    0x0C
+#define CPLD_BIOSCS_OFFSET	0x04
+
+
+/* Each client has this additional data */
+struct cpld_data {
+	struct device		*hwmon_dev;
+	struct mutex		update_lock;
+};
+
+/*-----------------------------------------------------------------------*/
+
+static ssize_t cpld_i2c_read(struct i2c_client *client, u8 *buf, u8 offset, size_t count)
+{
+#if USE_SMBUS    
+	int i;
+	
+    for(i=0; i<count; i++) {
+        buf[i] = i2c_smbus_read_byte_data(client, offset+i);
+    }	
+    return count;
+#else
+	struct i2c_msg msg[2];
+	char msgbuf[2];
+	int status;
+
+	memset(msg, 0, sizeof(msg));
+	
+	msgbuf[0] = offset;
+	
+	msg[0].addr = client->addr;
+	msg[0].buf = msgbuf;
+	msg[0].len = 1;
+
+	msg[1].addr = client->addr;
+	msg[1].flags = I2C_M_RD;
+	msg[1].buf = buf;
+	msg[1].len = count;
+	
+	status = i2c_transfer(client->adapter, msg, 2);
+	
+	if(status == 2)
+	    status = count;
+	    
+	return status;    
+#endif	
+}
+
+static ssize_t cpld_i2c_write(struct i2c_client *client, char *buf, unsigned offset, size_t count)
+{
+#if USE_SMBUS    
+	int i;
+	
+    for(i=0; i<count; i++) {
+        i2c_smbus_write_byte_data(client, offset+i, buf[i]);
+    }	
+    return count;
+#else
+	struct i2c_msg msg;
+	int status;
+    u8 writebuf[64];
+	
+	int i = 0;
+
+	msg.addr = client->addr;
+	msg.flags = 0;
+
+	/* msg.buf is u8 and casts will mask the values */
+	msg.buf = writebuf;
+	
+	msg.buf[i++] = offset;
+	memcpy(&msg.buf[i], buf, count);
+	msg.len = i + count;
+	
+	status = i2c_transfer(client->adapter, &msg, 1);
+	if (status == 1)
+		status = count;
+	
+    return status;	
+#endif    
+}
+
+/*-----------------------------------------------------------------------*/
+
+/* sysfs attributes for hwmon */
+
+static ssize_t show_info(struct device *dev, struct device_attribute *da,
+			 char *buf)
+{
+	u32 status;
+	//struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+	struct i2c_client *client = to_i2c_client(dev);
+	struct cpld_data *data = i2c_get_clientdata(client);
+	u8 b[4];
+    
+    memset(b, 0, 4);
+    
+	mutex_lock(&data->update_lock);
+    status = cpld_i2c_read(client, b, CPLD_INFO_OFFSET, 4);
+	mutex_unlock(&data->update_lock);
+	
+	if(status != 4) return sprintf(buf, "read cpld info fail\n");
+	
+	status = sprintf (buf,   "The CPLD release date is %02d/%02d/%d.\n", b[2] & 0xf, (b[3] & 0x1f), 2014+(b[2] >> 4));	/* mm/dd/yyyy*/
+	status = sprintf (buf, "%sThe PCB  version is %X%X\n", buf,  b[0]>>4, b[0]&0xf);
+	status = sprintf (buf, "%sThe CPLD version is %d.%d\n", buf, b[1]>>4, b[1]&0xf);
+	
+	return strlen(buf);
+}
+
+
+static ssize_t show_ctl(struct device *dev, struct device_attribute *da,
+			 char *buf)
+{
+	u32 status;
+	//struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+	struct i2c_client *client = to_i2c_client(dev);
+	struct cpld_data *data = i2c_get_clientdata(client);
+	u8 b[1];
+    
+	mutex_lock(&data->update_lock);
+	
+    status = cpld_i2c_read(client, b, CPLD_CTL_OFFSET, 1);
+	
+	mutex_unlock(&data->update_lock);
+	
+	if(status != 1) return sprintf(buf, "read cpld ctl fail\n");
+	    
+	
+	status = sprintf (buf, "0x%X\n", b[0]);
+	    
+	return strlen(buf);
+}
+
+static ssize_t set_ctl(struct device *dev,
+			   struct device_attribute *devattr,
+			   const char *buf, size_t count)
+{
+	//struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
+	struct i2c_client *client = to_i2c_client(dev);
+	struct cpld_data *data = i2c_get_clientdata(client);
+	u8 byte;
+
+	u8 temp = simple_strtol(buf, NULL, 10);
+    
+	mutex_lock(&data->update_lock);
+        cpld_i2c_read(client, &byte, CPLD_CTL_OFFSET, 1);
+	if(temp) byte |= (1<<0);
+	else     byte &= ~(1<<0);
+	cpld_i2c_write(client, &byte, CPLD_CTL_OFFSET, 1);
+	mutex_unlock(&data->update_lock);
+
+	return count;
+}
+
+static ssize_t show_bios_cs(struct device *dev, struct device_attribute *da,
+                         char *buf)
+{
+        u32 status;
+        //struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+        struct i2c_client *client = to_i2c_client(dev);
+        struct cpld_data *data = i2c_get_clientdata(client);
+        u8 b[1];
+
+        mutex_lock(&data->update_lock);
+
+    status = cpld_i2c_read(client, b, CPLD_BIOSCS_OFFSET, 1);
+
+        mutex_unlock(&data->update_lock);
+
+        if(status != 1) return sprintf(buf, "read cpld BIOS_CS fail\n");
+
+
+        status = sprintf (buf, "0x%X\n", b[0] & 0x01);
+
+        return strlen(buf);
+}
+
+static ssize_t set_bios_cs(struct device *dev,
+                           struct device_attribute *devattr,
+                           const char *buf, size_t count)
+{
+        //struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
+        struct i2c_client *client = to_i2c_client(dev);
+        struct cpld_data *data = i2c_get_clientdata(client);
+        u8 byte;
+
+        u8 temp = simple_strtol(buf, NULL, 10);
+
+        mutex_lock(&data->update_lock);
+        cpld_i2c_read(client, &byte, CPLD_BIOSCS_OFFSET, 1);
+        if(temp) byte |= 0x01;
+        else     byte &= ~(0x01);
+        cpld_i2c_write(client, &byte, CPLD_BIOSCS_OFFSET, 1);
+        mutex_unlock(&data->update_lock);
+
+        return count;
+}
+
+
+static char* led_str[] = {
+    "OFF",     //000
+    "0.5 Hz",  //001
+    "1 Hz",    //010
+    "2 Hz",    //011
+    "NA",      //100
+    "NA",      //101
+    "NA",      //110
+    "ON",      //111
+};
+
+static ssize_t show_led(struct device *dev, struct device_attribute *da,
+			 char *buf)
+{
+	u32 status;
+	struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+	struct i2c_client *client = to_i2c_client(dev);
+	struct cpld_data *data = i2c_get_clientdata(client);
+	u8 byte;
+	int shift = (attr->index == 0)?3:0;
+    
+	mutex_lock(&data->update_lock);
+    status = cpld_i2c_read(client, &byte, CPLD_LED_OFFSET, 1);
+	mutex_unlock(&data->update_lock);
+	
+	if(status != 1) return sprintf(buf, "read cpld offset 0x%x\n", CPLD_LED_OFFSET);
+	
+    byte = (byte >> shift) & 0x7;
+	
+	/*
+	    0: off
+	    1: 0.5hz
+	    2: 1 hz
+	    3: 2 hz
+	    4~6: not define
+	    7: on
+	*/
+	
+	status = sprintf (buf, "%d: %s\n", byte, led_str[byte]);
+	    
+	return strlen(buf);
+}
+
+static ssize_t set_led(struct device *dev,
+			   struct device_attribute *devattr,
+			   const char *buf, size_t count)
+{
+	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
+	struct i2c_client *client = to_i2c_client(dev);
+	struct cpld_data *data = i2c_get_clientdata(client);
+
+	u8 temp = simple_strtol(buf, NULL, 16);
+	u8 byte;
+	int shift = (attr->index == 0)?3:0;
+    
+    temp &= 0x7;    
+    //validate temp value: 0,1,2,3,7, TBD
+    
+	mutex_lock(&data->update_lock);
+    cpld_i2c_read(client, &byte, CPLD_LED_OFFSET, 1);
+    byte &= ~(0x7<<shift);
+    byte |= (temp<<shift);
+	cpld_i2c_write(client, &byte, CPLD_LED_OFFSET, 1);
+	mutex_unlock(&data->update_lock);
+
+	return count;
+}
+
+/*
+CPLD report the PSU0 status
+000 = PSU normal operation
+100 = PSU fault
+010 = PSU unpowered
+111 = PSU not installed
+
+7 6 | 5 4 3 |  2 1 0
+----------------------
+    | psu0  |  psu1
+*/
+static char* psu_str[] = {
+    "normal",           //000
+    "NA",               //001
+    "unpowered",        //010
+    "NA",               //011
+    "fault",            //100
+    "NA",               //101
+    "NA",               //110
+    "not installed",    //111
+};
+
+static ssize_t show_psu(struct device *dev, struct device_attribute *da,
+			 char *buf)
+{
+	u32 status;
+	struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+	struct i2c_client *client = to_i2c_client(dev);
+	struct cpld_data *data = i2c_get_clientdata(client);
+	u8 byte;
+	int shift = (attr->index == 1)?0:3;
+    
+	mutex_lock(&data->update_lock);
+    status = cpld_i2c_read(client, &byte, CPLD_PSU_OFFSET, 1);
+	mutex_unlock(&data->update_lock);
+	
+    byte = (byte >> shift) & 0x7;
+	
+	status = sprintf (buf, "%d : %s\n", byte, psu_str[byte]);
+	    
+	return strlen(buf);
+}
+
+
+static SENSOR_DEVICE_ATTR(info,  S_IRUGO,			        show_info, 0, 0);
+static SENSOR_DEVICE_ATTR(ctl, S_IWUSR|S_IRUGO,			show_ctl, set_ctl, 0);
+
+static SENSOR_DEVICE_ATTR(grn_led, S_IWUSR|S_IRUGO,			show_led, set_led, 0);
+static SENSOR_DEVICE_ATTR(red_led, S_IWUSR|S_IRUGO,			show_led, set_led, 1);
+
+static SENSOR_DEVICE_ATTR(psu0,  S_IRUGO,			        show_psu, 0, 0);
+static SENSOR_DEVICE_ATTR(psu1,  S_IRUGO,			        show_psu, 0, 1);
+
+static SENSOR_DEVICE_ATTR(bios_cs,  S_IWUSR|S_IRUGO,         show_bios_cs, set_bios_cs, 0);
+			
+static struct attribute *cpld_attributes[] = {
+    //info
+	&sensor_dev_attr_info.dev_attr.attr,
+	&sensor_dev_attr_ctl.dev_attr.attr,
+
+	&sensor_dev_attr_grn_led.dev_attr.attr,
+	&sensor_dev_attr_red_led.dev_attr.attr,
+
+	&sensor_dev_attr_psu0.dev_attr.attr,
+	&sensor_dev_attr_psu1.dev_attr.attr,
+	
+	&sensor_dev_attr_bios_cs.dev_attr.attr,
+
+	NULL
+};
+
+static const struct attribute_group cpld_group = {
+	.attrs = cpld_attributes,
+};
+
+/*-----------------------------------------------------------------------*/
+
+/* device probe and removal */
+
+static int
+cpld_probe(struct i2c_client *client, const struct i2c_device_id *id)
+{
+	struct cpld_data *data;
+	int status;
+
+    printk("+%s\n", __func__);
+    
+	if (!i2c_check_functionality(client->adapter,
+			I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA))
+		return -EIO;
+
+	data = kzalloc(sizeof(struct cpld_data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	i2c_set_clientdata(client, data);
+	mutex_init(&data->update_lock);
+	
+	/* Register sysfs hooks */
+	status = sysfs_create_group(&client->dev.kobj, &cpld_group);
+	if (status)
+		goto exit_free;
+
+	data->hwmon_dev = hwmon_device_register(&client->dev);
+	if (IS_ERR(data->hwmon_dev)) {
+		status = PTR_ERR(data->hwmon_dev);
+		goto exit_remove;
+	}
+
+	dev_info(&client->dev, "%s: sensor '%s'\n",
+		 dev_name(data->hwmon_dev), client->name);
+
+	return 0;
+
+exit_remove:
+	sysfs_remove_group(&client->dev.kobj, &cpld_group);
+exit_free:
+	i2c_set_clientdata(client, NULL);
+	kfree(data);
+	return status;
+}
+
+static int cpld_remove(struct i2c_client *client)
+{
+	struct cpld_data *data = i2c_get_clientdata(client);
+
+	hwmon_device_unregister(data->hwmon_dev);
+	sysfs_remove_group(&client->dev.kobj, &cpld_group);
+	i2c_set_clientdata(client, NULL);
+	kfree(data);
+	return 0;
+}
+
+static const struct i2c_device_id cpld_ids[] = {
+	{ "inv_cpld", 0, },
+	{ /* LIST END */ }
+};
+MODULE_DEVICE_TABLE(i2c, cpld_ids);
+
+static struct i2c_driver cpld_driver = {
+	.class		= I2C_CLASS_HWMON,
+	.driver = {
+		.name	= "inv_cpld",
+	},
+	.probe		= cpld_probe,
+	.remove		= cpld_remove,
+	.id_table	= cpld_ids,
+};
+
+/*-----------------------------------------------------------------------*/
+
+/* module glue */
+
+static int __init inv_cpld_init(void)
+{
+	return i2c_add_driver(&cpld_driver);
+}
+
+static void __exit inv_cpld_exit(void)
+{
+	i2c_del_driver(&cpld_driver);
+}
+
+MODULE_AUTHOR("eddie.lan <eddie.lan@inventec>");
+MODULE_DESCRIPTION("inv cpld driver");
+MODULE_LICENSE("GPL");
+
+module_init(inv_cpld_init);
+module_exit(inv_cpld_exit);

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/modules/builds/src/inv_mux.c

@@ -0,0 +1,281 @@
+#include <linux/module.h>
+#include <asm/io.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/jiffies.h>
+#include "io_expander.h"
+#include "inv_mux.h"
+
+static struct mux_obj_s *mux_head_p = NULL;
+
+
+/* ========== MUX object functions ==========
+ */
+int
+_common_force_pull_gpio(int mem_addr,
+                        int input,
+                        int bit_offset){
+
+    unsigned int val  = 0;
+    unsigned int targ = 0;
+
+    /* Get current value */
+    val = inl(mem_addr);
+    if (val == 0) {
+        SWPS_ERR("%s: inl:%d fail!\n", __func__, val);
+        return -1;
+    }
+    /* Count target value */
+    switch (input) {
+        case 0: /* Pull Low */
+            targ = (val & (~(1 << bit_offset)));
+            break;
+        case 1: /* Pull high */
+            targ = (val | (1 << bit_offset));
+            break;
+        default:
+            SWPS_ERR("%s: input state:%d incorrect!\n",
+                    __func__, input);
+            return -1;
+    }
+    /* Setup gpio */
+    outl(targ, mem_addr);
+    if (targ != inl(mem_addr)){
+        SWPS_ERR("%s: outl:%d fail!\n", __func__, targ);
+        return -1;
+    }
+    SWPS_DEBUG("%s: done.\n", __func__);
+    return 0;
+}
+
+
+int
+rangeley_force_pull_high(struct mux_obj_s *self){
+    SWPS_ERR("%s: not ready!\n", __func__);
+    return -1;
+}
+
+
+int
+rangeley_force_pull_low(struct mux_obj_s *self){
+    SWPS_ERR("%s: not ready!\n", __func__);
+    return -1;
+}
+
+
+int
+hedera_force_pull_high(struct mux_obj_s *self){
+    return _common_force_pull_gpio(MUX_RST_MEM_ADDR_HEDERA, 1, 5);
+}
+
+
+int
+hedera_force_pull_low(struct mux_obj_s *self){
+    return _common_force_pull_gpio(MUX_RST_MEM_ADDR_HEDERA, 0, 5);
+}
+
+
+int
+normal_gpio_pull_high(struct mux_obj_s *self){
+    return gpio_direction_output(self->gpio_num, 1);
+}
+
+
+int
+normal_gpio_pull_low(struct mux_obj_s *self){
+    return gpio_direction_output(self->gpio_num, 0);
+}
+
+
+int
+pca9548_reset_mux_all(struct mux_obj_s *self){
+    /* [Note] Power-on reset (PCA9548A-NXP)
+     *     When power is applied to VDD, an internal Power-On Reset (POR)
+     *     holds the PCA9548A in a reset condition until VDD has reached
+     *     VPOR. At this point, the reset condition is released and the
+     *     PCA9548A register and I2C-bus state machine are initialized to
+     *     their default states (all zeroes) causing all the channels to
+     *     be deselected. Thereafter, VDD must be lowered below 0.2 V for
+     *     at least 5 us in order to reset the device.
+     */
+    if (self->_pull_low(self) < 0) {
+        SWPS_ERR("%s: _pull_low fail!\n", __func__);
+        return -1;
+    }
+    mdelay(MUX_RST_WAIT_MS);
+    if (self->_pull_high(self) < 0) {
+        SWPS_ERR("%s: _pull_high fail!\n", __func__);
+        return -1;
+    }
+    mdelay(MUX_RST_WAIT_MS);
+    return 0;
+}
+
+
+int
+common_reset_mux_all(struct mux_obj_s *self){
+    SWPS_ERR("%s: not ready!\n", __func__);
+    return -1;
+}
+
+
+int
+init_gpio_4_force(struct mux_obj_s *self){
+    return 0;
+}
+
+
+int
+init_gpio_4_normal(struct mux_obj_s *self){
+
+    int err = 0;
+
+    if (!gpio_is_valid(self->gpio_num)) {
+        SWPS_ERR("%s: GIPO:%d isn't valid\n", __func__, self->gpio_num);
+        return -1;
+    }
+    err = gpio_request(self->gpio_num, MUX_GPIO_LABEL);
+    if (err < 0) {
+        SWPS_ERR("%s: gpio_request fail <err>:%d <gpio>:%d\n",
+                 __func__, err, self->gpio_num);
+        return -1;
+    }
+    SWPS_DEBUG("%s: gpio_request:%d ok.\n", __func__, self->gpio_num);
+    return 0;
+}
+
+
+static int
+_setup_muxctl_cb(struct mux_obj_s *self,
+                 unsigned gpio){
+
+    char *mod_dsc = "ERR";
+
+    switch (gpio) {
+        case MUX_RST_GPIO_FORCE_RANGELEY:
+            self->gpio_num   = gpio;
+            self->_pull_low  = rangeley_force_pull_low;
+            self->_pull_high = rangeley_force_pull_high;
+            self->_init      = init_gpio_4_force;
+            self->reset      = pca9548_reset_mux_all;
+            mod_dsc = "Rangeley force mode";
+            goto ok_setup_muxctl_cb;
+
+        case MUX_RST_GPIO_FORCE_HEDERA:
+            self->gpio_num   = gpio;
+            self->_pull_low  = hedera_force_pull_low;
+            self->_pull_high = hedera_force_pull_high;
+            self->_init      = init_gpio_4_force;
+            self->reset      = pca9548_reset_mux_all;
+            mod_dsc = "Hedera force mode";
+            goto ok_setup_muxctl_cb;
+
+        case MUX_RST_GPIO_48_PAC9548:
+            self->gpio_num   = gpio;
+            self->_pull_low  = normal_gpio_pull_low;
+            self->_pull_high = normal_gpio_pull_high;
+            self->_init      = init_gpio_4_normal;
+            self->reset      = pca9548_reset_mux_all;
+            mod_dsc = "Normal mode <gpio>:48";
+            goto ok_setup_muxctl_cb;
+
+        case MUX_RST_GPIO_69_PAC9548:
+            self->gpio_num   = gpio;
+            self->_pull_low  = normal_gpio_pull_low;
+            self->_pull_high = normal_gpio_pull_high;
+            self->_init      = init_gpio_4_normal;
+            self->reset      = pca9548_reset_mux_all;
+            mod_dsc = "Normal mode <gpio>:69";
+            goto ok_setup_muxctl_cb;
+
+        default:
+            break;
+    }
+    SWPS_ERR("%s: Unexpected GPIO:%d\n", __func__, gpio);
+    return -1;
+
+ok_setup_muxctl_cb:
+    SWPS_INFO("muxctl: %s.\n", mod_dsc);
+    return 0;
+}
+
+
+/* ========== MUX public functions ==========
+ */
+void
+clean_mux_gpio(void){
+
+    if (!mux_head_p) {
+        SWPS_DEBUG("%s: mux_head_p is NULL\n", __func__);
+        return;
+    }
+    if (gpio_is_valid(mux_head_p->gpio_num)) {
+        gpio_free(mux_head_p->gpio_num);
+    }
+    kfree(mux_head_p);
+    mux_head_p = NULL;
+    SWPS_DEBUG("%s: done.\n", __func__);
+}
+EXPORT_SYMBOL(clean_mux_gpio);
+
+
+int
+reset_mux_gpio(void){
+
+    if (!mux_head_p) {
+        SWPS_ERR("%s: MUX ctl object doesn't exist!\n", __func__);
+        return -1;
+    }
+    if (mux_head_p->reset(mux_head_p) < 0){
+        SWPS_ERR("%s: reset fail!\n", __func__);
+        return -1;
+    }
+    return 0;
+}
+EXPORT_SYMBOL(reset_mux_gpio);
+
+
+int
+init_mux_gpio(unsigned gpio){
+
+    /* Create MUX control object */
+    if (mux_head_p) {
+        SWPS_DEBUG("%s: mux_head_p is not NULL!\n", __func__);
+        clean_mux_gpio();
+    }
+    /* Currently, it is using single muxctl architecture.
+     * In the future, it may use the multi-muxctl if HW add new features.
+     * (Ex: Port power-status control)
+     */
+    mux_head_p = kzalloc(sizeof(struct mux_obj_s), GFP_KERNEL);
+    if (!mux_head_p) {
+        SWPS_ERR("%s: kzalloc fail!\n", __func__);
+        return -1;
+    }
+    /* Initial MUX controller */
+    if (_setup_muxctl_cb(mux_head_p, gpio) < 0){
+        SWPS_ERR("%s: _setup_muxctl_cb fail!\n", __func__);
+        return -1;
+    }
+    if (mux_head_p->_init(mux_head_p) < 0) {
+        SWPS_ERR("%s: init() fail\n", __func__);
+        goto err_init_mux_gpio;
+    }
+    /* Setup default value */
+    if (mux_head_p->_pull_high(mux_head_p) < 0) {
+        SWPS_ERR("%s: setup default fail!\n", __func__);
+        goto err_init_mux_gpio;
+    }
+    return 0;
+
+err_init_mux_gpio:
+    clean_mux_gpio();
+    return -1;
+}
+EXPORT_SYMBOL(init_mux_gpio);
+
+
+
+MODULE_LICENSE("GPL");
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/modules/builds/src/inv_mux.h

@@ -0,0 +1,36 @@
+#ifndef INV_MUX_H
+#define INV_MUX_H
+
+
+/* MUX basic information */
+#define MUX_GPIO_LABEL                 "SWPS_RST_MUX"
+
+/* MUX reset GPIO define */
+#define MUX_RST_GPIO_FORCE            (30100)
+#define MUX_RST_GPIO_FORCE_RANGELEY   (30101)
+#define MUX_RST_GPIO_FORCE_HEDERA     (30102)
+#define MUX_RST_GPIO_48_PAC9548          (48)
+#define MUX_RST_GPIO_69_PAC9548          (69)
+
+/* MUX relate value define */
+#define MUX_RST_WAIT_MS                   (1)
+#define MUX_RST_MEM_ADDR_RANGELEY         (0)    // TBD
+#define MUX_RST_MEM_ADDR_HEDERA       (0x548)
+
+struct mux_obj_s {
+    unsigned gpio_num;
+    int (*_pull_high)(struct mux_obj_s *self);
+    int (*_pull_low)(struct mux_obj_s *self);
+    int (*_init)(struct mux_obj_s *self);
+    int (*reset)(struct mux_obj_s *self);
+};
+
+
+void clean_mux_gpio(void);
+int  reset_mux_gpio(void);
+int  init_mux_gpio(unsigned gpio);
+
+
+#endif /* INV_MUX_H */
+
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/modules/builds/src/inv_platform.c

@@ -0,0 +1,280 @@
+#include <linux/i2c.h>
+//#include <linux/i2c-algo-bit.h>
+#include <linux/i2c-gpio.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+
+#include <linux/i2c/pca954x.h>
+#include <linux/platform_data/pca953x.h>
+#include <linux/platform_data/at24.h>
+
+//#include <asm/gpio.h>
+#define IO_EXPAND_BASE    64
+#define IO_EXPAND_NGPIO   16
+
+struct inv_i2c_board_info {
+    int ch;
+    int size;
+    struct i2c_board_info *board_info;
+};
+
+#define bus_id(id)  (id)
+static struct pca954x_platform_mode mux_modes_0[] = {
+    {.adap_id = bus_id(1),},    {.adap_id = bus_id(2),},
+    {.adap_id = bus_id(3),},    {.adap_id = bus_id(4),},
+    {.adap_id = bus_id(5),},    {.adap_id = bus_id(8),},
+};
+static struct pca954x_platform_mode mux_modes_0_0[] = {
+    {.adap_id = bus_id(17),},    {.adap_id = bus_id(18),},
+    {.adap_id = bus_id(19),},    {.adap_id = bus_id(20),},
+    {.adap_id = bus_id(21),},    {.adap_id = bus_id(22),},
+    {.adap_id = bus_id(23),},    {.adap_id = bus_id(24),},
+};
+
+static struct pca954x_platform_mode mux_modes_0_1[] = {
+    {.adap_id = bus_id(25),},    {.adap_id = bus_id(26),},
+    {.adap_id = bus_id(27),},    {.adap_id = bus_id(28),},
+    {.adap_id = bus_id(29),},    {.adap_id = bus_id(30),},
+    {.adap_id = bus_id(31),},    {.adap_id = bus_id(32),},
+};
+
+static struct pca954x_platform_mode mux_modes_0_2[] = {
+    {.adap_id = bus_id(33),},    {.adap_id = bus_id(34),},
+    {.adap_id = bus_id(35),},    {.adap_id = bus_id(36),},
+    {.adap_id = bus_id(37),},    {.adap_id = bus_id(38),},
+    {.adap_id = bus_id(39),},    {.adap_id = bus_id(40),},
+};
+
+static struct pca954x_platform_mode mux_modes_0_3[] = {
+    {.adap_id = bus_id(41),},    {.adap_id = bus_id(42),},
+    {.adap_id = bus_id(43),},    {.adap_id = bus_id(44),},
+    {.adap_id = bus_id(45),},    {.adap_id = bus_id(46),},
+    {.adap_id = bus_id(47),},    {.adap_id = bus_id(48),},
+};
+
+
+static struct pca954x_platform_mode mux_modes_0_7[] = {
+    {.adap_id = bus_id(9),},    {.adap_id = bus_id(10),},
+    {.adap_id = bus_id(11),},    {.adap_id = bus_id(12),},
+};
+static struct pca954x_platform_mode mux_modes_0_7_0[] = {
+    {.adap_id = bus_id(49),},    {.adap_id = bus_id(50),},
+    {.adap_id = bus_id(51),},    {.adap_id = bus_id(52),},
+    {.adap_id = bus_id(53),},    {.adap_id = bus_id(54),},
+    {.adap_id = bus_id(55),},    {.adap_id = bus_id(56),},
+};
+
+static struct pca954x_platform_mode mux_modes_0_7_1[] = {
+    {.adap_id = bus_id(57),},    {.adap_id = bus_id(58),},
+    {.adap_id = bus_id(59),},    {.adap_id = bus_id(60),},
+    {.adap_id = bus_id(61),},    {.adap_id = bus_id(62),},
+    {.adap_id = bus_id(63),},    {.adap_id = bus_id(64),},
+};
+
+static struct pca954x_platform_mode mux_modes_0_7_2[] = {
+    {.adap_id = bus_id(65),},    {.adap_id = bus_id(66),},
+    {.adap_id = bus_id(67),},    {.adap_id = bus_id(68),},
+    {.adap_id = bus_id(69),},    {.adap_id = bus_id(70),},
+    {.adap_id = bus_id(71),},    {.adap_id = bus_id(72),},
+};
+
+static struct pca954x_platform_mode mux_modes_0_7_3[] = {
+    {.adap_id = bus_id(73),},    {.adap_id = bus_id(74),},
+    {.adap_id = bus_id(75),},    {.adap_id = bus_id(76),},
+    {.adap_id = bus_id(77),},    {.adap_id = bus_id(78),},
+    {.adap_id = bus_id(79),},    {.adap_id = bus_id(80),},
+};
+
+
+static struct pca954x_platform_data mux_data_0 = {
+        .modes          = mux_modes_0,
+        .num_modes      = 6,
+};
+static struct pca954x_platform_data mux_data_0_0 = {
+        .modes          = mux_modes_0_0,
+        .num_modes      = 8,
+};
+static struct pca954x_platform_data mux_data_0_1 = {
+        .modes          = mux_modes_0_1,
+        .num_modes      = 8,
+};
+static struct pca954x_platform_data mux_data_0_2 = {
+        .modes          = mux_modes_0_2,
+        .num_modes      = 8,
+};
+static struct pca954x_platform_data mux_data_0_3 = {
+        .modes          = mux_modes_0_3,
+        .num_modes      = 8,
+};
+
+
+static struct pca954x_platform_data mux_data_0_7 = {
+        .modes          = mux_modes_0_7,
+        .num_modes      = 4,
+};
+static struct pca954x_platform_data mux_data_0_7_0 = {
+        .modes          = mux_modes_0_7_0,
+        .num_modes      = 8,
+};
+static struct pca954x_platform_data mux_data_0_7_1 = {
+        .modes          = mux_modes_0_7_1,
+        .num_modes      = 8,
+};
+static struct pca954x_platform_data mux_data_0_7_2 = {
+        .modes          = mux_modes_0_7_2,
+        .num_modes      = 8,
+};
+static struct pca954x_platform_data mux_data_0_7_3 = {
+        .modes          = mux_modes_0_7_3,
+        .num_modes      = 8,
+};
+
+
+static struct i2c_board_info i2c_device_info0[] __initdata = {
+        {"inv_cpld",         0, 0x55, 0, 0, 0},
+        {"pca9548",          0, 0x70, &mux_data_0, 0, 0},	
+};
+
+static struct i2c_board_info i2c_device_info1[] __initdata = {
+        {"pca9548",         0, 0x72, &mux_data_0_0, 0, 0},	
+};
+
+static struct i2c_board_info i2c_device_info2[] __initdata = {
+        {"pca9548",         0, 0x72, &mux_data_0_1, 0, 0},	
+};
+
+static struct i2c_board_info i2c_device_info3[] __initdata = {
+        {"pca9548",         0, 0x72, &mux_data_0_2, 0, 0},	
+};
+
+static struct i2c_board_info i2c_device_info4[] __initdata = {
+        {"pca9548",         0, 0x72, &mux_data_0_3, 0, 0},	
+};
+
+static struct i2c_board_info i2c_device_info5[] __initdata = {
+        {"pca9548",         0, 0x72, &mux_data_0_3, 0, 0},
+};
+
+static struct i2c_board_info i2c_device_info8[] __initdata = {
+        {"inv_cpld",        0, 0x77, 0, 0, 0},
+        {"pca9548",         0, 0x71, &mux_data_0_7, 0, 0},
+};
+
+static struct i2c_board_info i2c_device_info9[] __initdata = {
+        {"pca9548",         0, 0x72, &mux_data_0_7_0, 0, 0},
+};
+
+static struct i2c_board_info i2c_device_info10[] __initdata = {
+        {"pca9548",         0, 0x72, &mux_data_0_7_1, 0, 0},
+};
+
+static struct i2c_board_info i2c_device_info11[] __initdata = {
+        {"pca9548",         0, 0x72, &mux_data_0_7_2, 0, 0},
+};
+
+static struct i2c_board_info i2c_device_info12[] __initdata = {
+        {"pca9548",         0, 0x72, &mux_data_0_7_3, 0, 0},
+};
+
+static struct inv_i2c_board_info i2cdev_list[] = {
+    {0, ARRAY_SIZE(i2c_device_info0),  i2c_device_info0 },  //smbus 0, mux0
+    {8, ARRAY_SIZE(i2c_device_info8),  i2c_device_info8 },  //mux9
+
+    {bus_id(1), ARRAY_SIZE(i2c_device_info1),  i2c_device_info1 },  //mux1
+    {bus_id(2), ARRAY_SIZE(i2c_device_info2),  i2c_device_info2 },  //mux2
+    {bus_id(3), ARRAY_SIZE(i2c_device_info3),  i2c_device_info3 },  //mux3
+    {bus_id(4), ARRAY_SIZE(i2c_device_info4),  i2c_device_info4 },  //mux4
+    {bus_id(5), ARRAY_SIZE(i2c_device_info5),  i2c_device_info5 },  
+
+    {bus_id(9), ARRAY_SIZE(i2c_device_info9),  i2c_device_info9 },    //mux5
+    {bus_id(10), ARRAY_SIZE(i2c_device_info10),  i2c_device_info10 }, //mux6 
+    {bus_id(11), ARRAY_SIZE(i2c_device_info11),  i2c_device_info11 }, //mux7 
+    {bus_id(12), ARRAY_SIZE(i2c_device_info12),  i2c_device_info12 }, //mux8
+};
+
+/////////////////////////////////////////////////////////////////////////////////////////
+static struct 	i2c_gpio_platform_data 	i2c_gpio_platdata0 = {
+	.scl_pin = 8,
+	.sda_pin = 9,
+    
+	.udelay  = 5, //5:100kHz
+	.sda_is_open_drain = 0,
+	.scl_is_open_drain = 0,
+	.scl_is_output_only = 0
+};
+
+static struct 	i2c_gpio_platform_data 	i2c_gpio_platdata1 = {
+	.scl_pin = 12,
+	.sda_pin = 11,
+    
+	.udelay  = 5, //5:100kHz
+	.sda_is_open_drain = 0,
+	.scl_is_open_drain = 0,
+	.scl_is_output_only = 0
+};
+
+static struct 	platform_device 	device_i2c_gpio0 = {
+	.name 	= "i2c-gpio",
+	.id  	= 0, // adapter number
+	.dev.platform_data = &i2c_gpio_platdata0,
+};
+
+static struct 	platform_device 	device_i2c_gpio1 = {
+	.name 	= "i2c-gpio",
+	.id  	= 1, // adapter number
+	.dev.platform_data = &i2c_gpio_platdata1,
+};
+
+static int __init plat_lavender_x86_init(void)
+{
+    struct i2c_adapter *adap = NULL;
+    struct i2c_client *e = NULL;
+    int ret = 0;
+    int i,j;
+
+    printk("el6661 plat_lavender_x86_init  \n");
+
+#if 0  //disable for ICOS
+    //use i2c-gpio    
+    //register i2c gpio
+    //config gpio8,9 to gpio function
+    outl( inl(0x500) | (1<<8 | 1<<9), 0x500);
+    
+	ret = platform_device_register(&device_i2c_gpio0);
+	if (ret) {
+		printk(KERN_ERR "i2c-gpio: device_i2c_gpio0 register fail %d\n", ret);
+	}
+	
+    outl( inl(0x500) | (1<<11 | 1<<12), 0x500);
+	ret = platform_device_register(&device_i2c_gpio1);
+	if (ret) {
+		printk(KERN_ERR "i2c-gpio: device_i2c_gpio1 register fail %d\n", ret);
+	}
+#endif
+    
+    for(i=0; i<ARRAY_SIZE(i2cdev_list); i++) {
+        
+        adap = i2c_get_adapter( i2cdev_list[i].ch );
+        if (adap == NULL) {
+            printk("lavender_x86 get channel %d adapter fail\n", i);
+            continue;
+            return -ENODEV;
+        }
+    
+        i2c_put_adapter(adap);
+        for(j=0; j<i2cdev_list[i].size; j++) {
+            e = i2c_new_device(adap, &i2cdev_list[i].board_info[j] );
+        }
+    }
+
+    return ret;    
+}
+
+module_init(plat_lavender_x86_init);
+//arch_initcall(plat_lavender_x86_init);
+
+MODULE_AUTHOR("Inventec");
+MODULE_DESCRIPTION("Lavender_x86 Platform devices");
+MODULE_LICENSE("GPL");

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/modules/builds/src/inv_psoc.c

@@ -0,0 +1,760 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/jiffies.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/err.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/kthread.h>
+
+//=================================
+#include <linux/mutex.h>
+#include <linux/completion.h>
+#include <linux/ipmi.h>
+#include <linux/ipmi_smi.h>
+
+#define IPMI_MAX_INTF            (4)
+#define NETFN_OEM 0x30
+#define CMD_GETDATA 0x31
+#define CMD_SETDATA 0x32
+#define FAN_NUM  4 
+#define PSU_NUM  2 
+
+#define PSU1		0x5800
+#define PSU2		0x5900
+#define BMC_PMBusNumber	3
+#define PMBus_Vender	0x99
+#define PMBus_Serial	0x9E
+#define PMBus_Temp2 	0x8E
+#define PMBus_Version	0x9B
+#define MaxLeng_Result	0x20
+
+#define MAX_IPMI_RECV_LENGTH 0xff
+
+static long pmbus_reg2data_linear(int data, int linear16);
+struct ipmi_result{
+	char result[MAX_IPMI_RECV_LENGTH];
+	int result_length;
+};
+
+DEFINE_MUTEX(ipmi_mutex);
+DEFINE_MUTEX(ipmi2_mutex);
+static struct ipmi_result ipmiresult;
+static struct device *hwmon_dev;
+static struct kobject *device_kobj;
+static ipmi_user_t ipmi_mh_user = NULL;
+static void msg_handler(struct ipmi_recv_msg *msg,void* handler_data);
+static struct ipmi_user_hndl ipmi_hndlrs = {   .ipmi_recv_hndl = msg_handler,};
+
+static atomic_t dummy_count = ATOMIC_INIT(0);
+static void dummy_smi_free(struct ipmi_smi_msg *msg)
+{
+        atomic_dec(&dummy_count);
+}
+static void dummy_recv_free(struct ipmi_recv_msg *msg)
+{
+        atomic_dec(&dummy_count);
+}
+static struct ipmi_smi_msg halt_smi_msg = {
+        .done = dummy_smi_free
+};
+static struct ipmi_recv_msg halt_recv_msg = {
+        .done = dummy_recv_free
+};
+
+struct __attribute__ ((__packed__))  psoc_psu_layout {
+    u16 psu1_iin;
+    u16 psu2_iin;
+    u16 psu1_iout;
+    u16 psu2_iout;
+    
+    u16 psu1_pin;
+    u16 psu2_pin;
+    u16 psu1_pout;
+    u16 psu2_pout;
+    
+    u16 psu1_vin;
+    u16 psu2_vin;
+    u16 psu1_vout;
+    u16 psu2_vout;
+};
+
+struct __attribute__ ((__packed__))  psoc_layout {
+    u8 ctl;                 //offset: 0
+    u16 switch_temp;        //offset: 1
+    u8 reserve0;            //offset: 3
+
+    u8 fw_upgrade;          //offset: 4
+
+    //i2c bridge
+    u8 i2c_st;              //offset: 5
+    u8 i2c_ctl;             //offset: 6
+    u8 i2c_addr;            //offset: 7
+    u8 i2c_data[0x20];      //offset: 8 
+
+    //gpo
+    u8 led_ctl;             //offset: 28
+
+    u8 gpio;                //offset: 29
+
+    //pwm duty
+    u8 pwm[FAN_NUM];        //offset: 2a
+    u8 pwm_psu[PSU_NUM];    //offset: 2e
+
+    //fan rpm
+    u16 fan[FAN_NUM*2];     //offset: 30
+    
+    u8  reserve1[4];        //offset: 40
+
+    //gpi 
+    u8 gpi_fan;             //offset: 44 
+
+    //psu state
+    u8 psu_state;           //offset: 45
+
+    //temperature
+    u16 temp[5];            //offset: 46
+    u16 temp_psu[PSU_NUM];  //offset: 50
+
+    //version
+    u8 version[2];          //offset: 54
+    
+    u8  reserve2[4];        //offset: 56
+    struct psoc_psu_layout psu_info;      //offset: 5a
+};        
+
+/* definition */
+/* definition */
+#define PSOC_OFF(m)    offsetof(struct psoc_layout, m)
+#define PSOC_PSU_OFF(m)    offsetof(struct psoc_psu_layout, m)
+
+#define SWITCH_TMP_OFFSET       PSOC_OFF(switch_temp)
+#define PWM_OFFSET              PSOC_OFF(pwm)
+#define THERMAL_OFFSET          PSOC_OFF(temp)
+#define RPM_OFFSET              PSOC_OFF(fan)
+#define DIAG_FLAG_OFFSET        PSOC_OFF(ctl)
+#define FAN_LED_OFFSET          PSOC_OFF(led_ctl)
+#define FAN_GPI_OFFSET          PSOC_OFF(gpi_fan)
+#define PSOC_PSU_OFFSET         PSOC_OFF(psu_state)
+#define VERSION_OFFSET          PSOC_OFF(version)
+#define PSU_INFO_OFFSET         PSOC_OFF(psu_info)
+
+
+static void msg_handler(struct ipmi_recv_msg *recv_msg,void* handler_data)
+{
+    struct ipmi_result *msg_result = recv_msg->user_msg_data;
+    
+    if(recv_msg->msg.data[0]==0 && recv_msg->msg.data_len>0) {
+        msg_result->result_length=recv_msg->msg.data_len-1;
+        memcpy(msg_result->result, &recv_msg->msg.data[1], recv_msg->msg.data_len-1);
+    }
+    ipmi_free_recv_msg(recv_msg);
+    mutex_unlock(&ipmi_mutex);
+
+    return;
+}
+
+int start_ipmi_command(char NetFn, char cmd,char *data,int data_length, char* result, int* result_length)
+{
+    int rv=0,i;
+    int timeout;
+	
+    //wait previous command finish at least 50msec
+    timeout=50;
+    while((mutex_is_locked(&ipmi_mutex) == 1 || (mutex_is_locked(&ipmi2_mutex) == 1)) && (--timeout)>0) { usleep_range(1000,1010); }
+    if(timeout==0) { return -1; }
+    mutex_lock(&ipmi_mutex);
+    mutex_lock(&ipmi2_mutex);
+
+    if(ipmi_mh_user == NULL) {
+        for (i=0,rv=1; i<IPMI_MAX_INTF && rv; i++) {
+            rv = ipmi_create_user(i, &ipmi_hndlrs, NULL, &ipmi_mh_user);
+	    }
+    }
+	
+    if (rv < 0) { 
+        mutex_unlock(&ipmi_mutex); 
+        mutex_unlock(&ipmi2_mutex);
+        return rv; 
+    }
+    else {
+	struct	ipmi_system_interface_addr addr;
+	struct	kernel_ipmi_msg msg;
+	uint8_t msg_data[data_length];
+		
+	memcpy(msg_data,data,data_length);
+	addr.addr_type = IPMI_SYSTEM_INTERFACE_ADDR_TYPE; 
+	addr.channel = IPMI_BMC_CHANNEL;  
+	addr.lun = 0;
+
+	msg.netfn = NetFn;
+	msg.cmd = cmd;
+	msg.data = msg_data;
+	msg.data_len = data_length;
+
+	rv = ipmi_request_supply_msgs(ipmi_mh_user, (struct ipmi_addr*)&addr, 0,&msg, &ipmiresult, &halt_smi_msg, &halt_recv_msg, 0);
+	if (rv) {
+		mutex_unlock(&ipmi_mutex);
+                mutex_unlock(&ipmi2_mutex);
+		return -6;
+	}
+
+        //skip command if 1sec no response from remote
+        timeout=1000;
+        while(mutex_is_locked(&ipmi_mutex) == 1 && (--timeout)>0) { usleep_range(1000,1100);}
+	if(timeout==0) {
+        	mutex_unlock(&ipmi2_mutex);
+		return -1; 
+	}
+	else {
+		*result_length=ipmiresult.result_length;
+		memcpy(result,ipmiresult.result,*result_length);
+                mutex_unlock(&ipmi2_mutex);
+		return 0;
+	}
+    }
+    return 0;
+}
+EXPORT_SYMBOL(start_ipmi_command);
+
+static ssize_t psoc_ipmi_read(u8 *buf, u8 offset, size_t count)
+{
+    uint8_t data[2];
+    int result_len=0;
+    int rv;
+
+    data[0] = offset;
+    data[1] = count;
+
+    rv=start_ipmi_command(NETFN_OEM, CMD_GETDATA,data,2, buf, &result_len);
+
+    return result_len;
+}
+
+static ssize_t psoc_ipmi_write(char *buf, unsigned offset, size_t count)
+{
+    uint8_t data[count+1],result[1];
+    int result_len;
+
+    data[0] = offset;
+    memcpy(&data[1],buf,count);
+
+    start_ipmi_command(NETFN_OEM, CMD_SETDATA,data,count+1, result, &result_len);	
+    return count;
+}
+
+
+static u16 psoc_read16(u8 offset)
+{
+	u16 value = 0;
+	u8 buf[]={0,0};
+    
+    if(psoc_ipmi_read(buf, offset, 2) == 2)
+        value = (buf[0]<<8 | buf[1]<<0);
+    
+	return value;
+}
+
+static u8 psoc_read8(u8 offset)
+{
+	u8 value = 0;
+	u8 buf = 0;
+    
+    if(psoc_ipmi_read(&buf, offset, 1) == 1)
+        value = buf;
+    
+	return value;
+}
+
+/*
+CPLD report the PSU0 status
+000 = PSU normal operation
+100 = PSU fault
+010 = PSU unpowered
+111 = PSU not installed
+
+7 6 | 5 4 3 |  2 1 0
+----------------------
+    | psu1  |  psu0
+*/
+static char* psu_str[] = {
+    "normal",           //000
+    "NA",               //001
+    "unpowered",        //010
+    "NA",               //011
+    "fault",            //100
+    "NA",               //101
+    "NA",               //110
+    "not installed",    //111
+};
+
+static ssize_t show_psu_st(struct device *dev, struct device_attribute *da,
+			 char *buf)
+{
+	u32 status=0;
+	struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+	u8 byte=0;
+	int shift = (attr->index == 0)?3:0;
+    
+    status = psoc_ipmi_read(&byte, PSOC_PSU_OFFSET, 1);
+	
+    byte = (byte >> shift) & 0x7;
+	
+	status = sprintf (buf, "%d : %s\n", byte, psu_str[byte]);
+	    
+	return strlen(buf);
+}
+
+static ssize_t show_ipmi_pmbus(struct device *dev, struct device_attribute *da,
+                         char *buf)
+{
+    struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+	uint8_t data[4],result[MaxLeng_Result];
+	int result_len=0;
+
+	data[0] = BMC_PMBusNumber;
+	data[1] = (attr->index & 0xFF00 ) >>7;
+	data[3] = attr->index & 0xff;
+	if(data[3]==PMBus_Temp2) 
+		{data[2]=2;}
+	else
+		{data[2]=MaxLeng_Result;}
+
+	if(start_ipmi_command(0x06, 0x52,data,4, result, &result_len)==0)
+	{
+		if(data[3]==PMBus_Temp2)
+		{
+  			return sprintf(buf, "%ld \n", pmbus_reg2data_linear(result[0] | (result[1]<<8), 0 ));
+		}
+		result[result[0]+1]='\0';
+	    return sprintf(buf, "%s\n",&result[1] );
+	}
+	else
+	{
+		return 0;
+	}
+}
+
+static ssize_t show_thermal(struct device *dev, struct device_attribute *da,
+			 char *buf)
+{
+	int status=0;
+	struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+	u8 offset = attr->index * 2 + THERMAL_OFFSET;
+
+	status = psoc_read16(offset);
+
+	return sprintf(buf, "%d\n",
+		       (s8)(status>>8) * 1000  );
+}
+
+static ssize_t show_pwm(struct device *dev, struct device_attribute *da,
+			 char *buf)
+{
+	int status=0;
+	struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+	u8 offset = attr->index  + PWM_OFFSET;
+
+	status = psoc_read8(offset);
+
+	return sprintf(buf, "%d\n",
+		       status);
+}
+
+static ssize_t set_pwm(struct device *dev,
+			   struct device_attribute *da,
+			   const char *buf, size_t count)
+{
+	struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+	u8 offset = attr->index  + PWM_OFFSET;
+
+	u8 pwm = simple_strtol(buf, NULL, 10);
+	if(pwm > 255) pwm = 255;
+	  
+    psoc_ipmi_write(&pwm, offset, 1);
+	
+	return count;
+}
+
+
+static ssize_t show_rpm(struct device *dev, struct device_attribute *da,
+			 char *buf)
+{
+	int status=0;
+	struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+	u8 offset = attr->index*2  + RPM_OFFSET;
+	
+	status = psoc_read16(offset);
+
+	return sprintf(buf, "%d\n",
+		       status);
+}
+
+static ssize_t show_switch_tmp(struct device *dev, struct device_attribute *da,
+			 char *buf)
+{
+	u16 status=0;
+	u16 temp = 0;
+
+    status = psoc_ipmi_read((u8*)&temp, SWITCH_TMP_OFFSET, 2);
+	
+	status = sprintf (buf, "%d\n",  (s8)(temp>>8) * 1000  );
+	    
+	return strlen(buf);
+}
+
+static ssize_t set_switch_tmp(struct device *dev,
+			   struct device_attribute *devattr,
+			   const char *buf, size_t count)
+{
+	long temp = simple_strtol(buf, NULL, 10);
+    u16 temp2 =  ( (temp/1000) <<8 ) & 0xFF00 ;
+    
+    //printk("set_switch_tmp temp=%d, temp2=0x%x (%x,%x)\n", temp, temp2, ( ( (temp/1000) <<8 ) & 0xFF00 ),  (( (temp%1000) / 10 ) & 0xFF));
+	psoc_ipmi_write((u8*)&temp2, SWITCH_TMP_OFFSET, 2);
+
+	
+	return count;
+}
+
+static ssize_t show_diag(struct device *dev, struct device_attribute *da,
+			 char *buf)
+{
+	u16 status=0;
+	u8 diag_flag = 0;
+
+    status = psoc_ipmi_read((u8*)&diag_flag, DIAG_FLAG_OFFSET, 1);
+
+	status = sprintf (buf, "%d\n", ((diag_flag & 0x80)?1:0));
+	    
+	return strlen(buf);
+}
+
+static ssize_t set_diag(struct device *dev,
+			   struct device_attribute *devattr,
+			   const char *buf, size_t count)
+{
+	u8 value = 0;
+	u8 diag = simple_strtol(buf, NULL, 10);
+	
+    diag = diag?1:0;
+
+	psoc_ipmi_read((u8*)&value, DIAG_FLAG_OFFSET, 1);
+	if(diag) value |= (1<<7);
+	else     value &= ~(1<<7);
+	psoc_ipmi_write((u8*)&value, DIAG_FLAG_OFFSET, 1);
+	
+	return count;
+}
+
+static ssize_t show_version(struct device *dev, struct device_attribute *da,
+			 char *buf)
+{
+	u16 status=0;
+
+	status = psoc_read16(VERSION_OFFSET);
+	
+	return sprintf(buf, "ver: %x.%x\n", (status & 0xFF00)>>8,  (status & 0xFF) );
+}
+
+
+static ssize_t show_fan_led(struct device *dev, struct device_attribute *da,
+			 char *buf)
+{
+	int status=0;
+	struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+	u8 bit = attr->index;
+	
+	status = psoc_read8(FAN_LED_OFFSET);
+
+	return sprintf(buf, "%d\n",
+		       (status & (1<<bit))?1:0 );
+}
+
+static ssize_t set_fan_led(struct device *dev,
+			   struct device_attribute *devattr,
+			   const char *buf, size_t count)
+{
+	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
+	u8 bit = attr->index;
+	u8 led_state = 0;
+
+	u8 v = simple_strtol(buf, NULL, 10);
+	  
+    led_state = psoc_read8(FAN_LED_OFFSET);
+    if(v) led_state |=  (1<<bit);
+    else  led_state &= ~(1<<bit);    
+    psoc_ipmi_write(&led_state, FAN_LED_OFFSET, 1);
+    
+	return count;
+}
+
+static ssize_t show_value8(struct device *dev, struct device_attribute *da,
+			 char *buf)
+{
+	int status=0;
+	struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+	u8 offset = attr->index;
+
+	status = psoc_read8(offset);
+	
+	return sprintf(buf, "0x%02X\n", status );
+}
+
+static long pmbus_reg2data_linear(int data, int linear16)
+{
+    s16 exponent;
+    s32 mantissa;
+    long val;
+
+    if (linear16) { /* LINEAR16 */
+        exponent = -9;
+        mantissa = (u16) data;
+    } else {  /* LINEAR11 */
+        exponent = ((s16)data) >> 11;
+        exponent = ((s16)( data & 0xF800) ) >> 11;
+        mantissa = ((s32)((data & 0x7ff) << 5)) >> 5;
+    }
+    
+    //printk("data=%d,  m=%d, e=%d\n", data, exponent, mantissa);
+    val = mantissa;
+
+    /* scale result to micro-units for power sensors */
+    val = val * 1000L;
+
+    if (exponent >= 0)
+        val <<= exponent;
+    else
+        val >>= -exponent;
+
+    return val;
+}
+
+static ssize_t show_psu_psoc(struct device *dev, struct device_attribute *da,
+			 char *buf)
+{
+	u16 status=0;
+	struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+	u8 offset = attr->index + PSU_INFO_OFFSET;
+
+	status = psoc_read16(offset);
+	
+	return sprintf(buf, "%ld \n", pmbus_reg2data_linear(status, strstr(attr->dev_attr.attr.name, "vout")? 1:0 ));
+}
+
+
+static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO,			show_thermal, 0, 0);
+static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO,			show_thermal, 0, 1);
+static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO,			show_thermal, 0, 2);
+static SENSOR_DEVICE_ATTR(temp4_input, S_IRUGO,			show_thermal, 0, 3);
+static SENSOR_DEVICE_ATTR(temp5_input, S_IRUGO,			show_thermal, 0, 4);
+static SENSOR_DEVICE_ATTR(thermal_psu1, S_IRUGO,		show_thermal, 0, 5);
+static SENSOR_DEVICE_ATTR(thermal_psu2, S_IRUGO,		show_thermal, 0, 6);
+
+static SENSOR_DEVICE_ATTR(pwm1, S_IWUSR|S_IRUGO,			show_pwm, set_pwm, 0);
+static SENSOR_DEVICE_ATTR(pwm2, S_IWUSR|S_IRUGO,			show_pwm, set_pwm, 1);
+static SENSOR_DEVICE_ATTR(pwm3, S_IWUSR|S_IRUGO,			show_pwm, set_pwm, 2);
+static SENSOR_DEVICE_ATTR(pwm4, S_IWUSR|S_IRUGO,			show_pwm, set_pwm, 3);
+static SENSOR_DEVICE_ATTR(pwm_psu1, S_IWUSR|S_IRUGO,		show_pwm, set_pwm, 4);
+static SENSOR_DEVICE_ATTR(pwm_psu2, S_IWUSR|S_IRUGO,		show_pwm, set_pwm, 5);
+
+static SENSOR_DEVICE_ATTR(psu0,  S_IRUGO,			        show_psu_st, 0, 0);
+static SENSOR_DEVICE_ATTR(psu1,  S_IRUGO,			        show_psu_st, 0, 1);
+
+static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO,			show_rpm, 0, 0);
+static SENSOR_DEVICE_ATTR(fan2_input, S_IRUGO,			show_rpm, 0, 1);
+static SENSOR_DEVICE_ATTR(fan3_input, S_IRUGO,			show_rpm, 0, 2);
+static SENSOR_DEVICE_ATTR(fan4_input, S_IRUGO,			show_rpm, 0, 3);
+static SENSOR_DEVICE_ATTR(fan5_input, S_IRUGO,			show_rpm, 0, 4);
+static SENSOR_DEVICE_ATTR(fan6_input, S_IRUGO,			show_rpm, 0, 5);
+static SENSOR_DEVICE_ATTR(fan7_input, S_IRUGO,			show_rpm, 0, 6);
+static SENSOR_DEVICE_ATTR(fan8_input, S_IRUGO,			show_rpm, 0, 7);
+static SENSOR_DEVICE_ATTR(rpm_psu1, S_IRUGO,		show_rpm, 0, 8);
+static SENSOR_DEVICE_ATTR(rpm_psu2, S_IRUGO,		show_rpm, 0, 9);
+
+static SENSOR_DEVICE_ATTR(switch_tmp, S_IWUSR|S_IRUGO,			show_switch_tmp, set_switch_tmp, 0);
+
+static SENSOR_DEVICE_ATTR(diag, S_IWUSR|S_IRUGO,			show_diag, set_diag, 0);
+static SENSOR_DEVICE_ATTR(version, S_IRUGO,			show_version, 0, 0);
+
+static SENSOR_DEVICE_ATTR(fan_led_grn1, S_IWUSR|S_IRUGO,			show_fan_led, set_fan_led, 0);
+static SENSOR_DEVICE_ATTR(fan_led_grn2, S_IWUSR|S_IRUGO,			show_fan_led, set_fan_led, 1);
+static SENSOR_DEVICE_ATTR(fan_led_grn3, S_IWUSR|S_IRUGO,			show_fan_led, set_fan_led, 2);
+static SENSOR_DEVICE_ATTR(fan_led_grn4, S_IWUSR|S_IRUGO,			show_fan_led, set_fan_led, 3);
+static SENSOR_DEVICE_ATTR(fan_led_red1, S_IWUSR|S_IRUGO,			show_fan_led, set_fan_led, 4);
+static SENSOR_DEVICE_ATTR(fan_led_red2, S_IWUSR|S_IRUGO,			show_fan_led, set_fan_led, 5);
+static SENSOR_DEVICE_ATTR(fan_led_red3, S_IWUSR|S_IRUGO,			show_fan_led, set_fan_led, 6);
+static SENSOR_DEVICE_ATTR(fan_led_red4, S_IWUSR|S_IRUGO,			show_fan_led, set_fan_led, 7);
+
+static SENSOR_DEVICE_ATTR(fan_gpi,      S_IRUGO,			        show_value8,  0,           FAN_GPI_OFFSET);
+static SENSOR_DEVICE_ATTR(psoc_psu1_vin,      S_IRUGO,                          show_psu_psoc,  0,           PSOC_PSU_OFF(psu1_vin));
+static SENSOR_DEVICE_ATTR(psoc_psu1_vout,     S_IRUGO,			        show_psu_psoc,  0,           PSOC_PSU_OFF(psu1_vout));
+static SENSOR_DEVICE_ATTR(psoc_psu1_iin,      S_IRUGO,			        show_psu_psoc,  0,           PSOC_PSU_OFF(psu1_iin));
+static SENSOR_DEVICE_ATTR(psoc_psu1_iout,     S_IRUGO,			        show_psu_psoc,  0,           PSOC_PSU_OFF(psu1_iout));
+static SENSOR_DEVICE_ATTR(psoc_psu1_pin,      S_IRUGO,			        show_psu_psoc,  0,           PSOC_PSU_OFF(psu1_pin));
+static SENSOR_DEVICE_ATTR(psoc_psu1_pout,     S_IRUGO,			        show_psu_psoc,  0,           PSOC_PSU_OFF(psu1_pout));
+
+
+static SENSOR_DEVICE_ATTR(psoc_psu2_vin,      S_IRUGO,			        show_psu_psoc,  0,           PSOC_PSU_OFF(psu2_vin)); 
+static SENSOR_DEVICE_ATTR(psoc_psu2_vout,     S_IRUGO,			        show_psu_psoc,  0,           PSOC_PSU_OFF(psu2_vout));
+static SENSOR_DEVICE_ATTR(psoc_psu2_iin,      S_IRUGO,			        show_psu_psoc,  0,           PSOC_PSU_OFF(psu2_iin)); 
+static SENSOR_DEVICE_ATTR(psoc_psu2_iout,     S_IRUGO,			        show_psu_psoc,  0,           PSOC_PSU_OFF(psu2_iout));
+static SENSOR_DEVICE_ATTR(psoc_psu2_pin,      S_IRUGO,			        show_psu_psoc,  0,           PSOC_PSU_OFF(psu2_pin)); 
+static SENSOR_DEVICE_ATTR(psoc_psu2_pout,     S_IRUGO,			        show_psu_psoc,  0,           PSOC_PSU_OFF(psu2_pout));
+
+//IPMI
+static SENSOR_DEVICE_ATTR(thermal2_psu1,	S_IRUGO,                show_ipmi_pmbus, 0, PSU1 | PMBus_Temp2);
+static SENSOR_DEVICE_ATTR(psoc_psu1_vender,	S_IRUGO,                show_ipmi_pmbus, 0, PSU1 | PMBus_Vender);
+static SENSOR_DEVICE_ATTR(psoc_psu1_serial,	S_IRUGO,                show_ipmi_pmbus, 0, PSU1 | PMBus_Serial);
+static SENSOR_DEVICE_ATTR(psoc_psu1_version,	S_IRUGO,                show_ipmi_pmbus, 0, PSU1 | PMBus_Version);
+
+static SENSOR_DEVICE_ATTR(thermal2_psu2,        S_IRUGO,                show_ipmi_pmbus, 0, PSU2 | PMBus_Temp2);
+static SENSOR_DEVICE_ATTR(psoc_psu2_vender,     S_IRUGO,                show_ipmi_pmbus, 0, PSU2 | PMBus_Vender);
+static SENSOR_DEVICE_ATTR(psoc_psu2_serial,     S_IRUGO,                show_ipmi_pmbus, 0, PSU2 | PMBus_Serial);
+static SENSOR_DEVICE_ATTR(psoc_psu2_version,    S_IRUGO,                show_ipmi_pmbus, 0, PSU2 | PMBus_Version);
+
+ 
+static struct attribute *psoc_attributes[] = {
+    //thermal
+	&sensor_dev_attr_temp1_input.dev_attr.attr,
+	&sensor_dev_attr_temp2_input.dev_attr.attr,
+	&sensor_dev_attr_temp3_input.dev_attr.attr,
+	&sensor_dev_attr_temp4_input.dev_attr.attr,
+	&sensor_dev_attr_temp5_input.dev_attr.attr,
+	
+	&sensor_dev_attr_thermal_psu1.dev_attr.attr,
+	&sensor_dev_attr_thermal_psu2.dev_attr.attr,
+
+
+    //pwm
+	&sensor_dev_attr_pwm1.dev_attr.attr,
+	&sensor_dev_attr_pwm2.dev_attr.attr,
+	&sensor_dev_attr_pwm3.dev_attr.attr,
+	&sensor_dev_attr_pwm4.dev_attr.attr,
+	&sensor_dev_attr_pwm_psu1.dev_attr.attr,
+	&sensor_dev_attr_pwm_psu2.dev_attr.attr,
+	
+	//rpm
+	&sensor_dev_attr_fan1_input.dev_attr.attr,
+	&sensor_dev_attr_fan2_input.dev_attr.attr,
+	&sensor_dev_attr_fan3_input.dev_attr.attr,
+	&sensor_dev_attr_fan4_input.dev_attr.attr,
+	&sensor_dev_attr_fan5_input.dev_attr.attr,
+	&sensor_dev_attr_fan6_input.dev_attr.attr,
+	&sensor_dev_attr_fan7_input.dev_attr.attr,
+	&sensor_dev_attr_fan8_input.dev_attr.attr,
+	
+	&sensor_dev_attr_rpm_psu1.dev_attr.attr,
+	&sensor_dev_attr_rpm_psu2.dev_attr.attr,
+    
+    //switch temperature
+	&sensor_dev_attr_switch_tmp.dev_attr.attr,
+
+    //diag flag
+	&sensor_dev_attr_diag.dev_attr.attr,
+	
+	//version
+	&sensor_dev_attr_version.dev_attr.attr,
+	
+	//fan led 
+	&sensor_dev_attr_fan_led_grn1.dev_attr.attr,
+	&sensor_dev_attr_fan_led_grn2.dev_attr.attr,
+	&sensor_dev_attr_fan_led_grn3.dev_attr.attr,
+	&sensor_dev_attr_fan_led_grn4.dev_attr.attr,
+	&sensor_dev_attr_fan_led_red1.dev_attr.attr,
+	&sensor_dev_attr_fan_led_red2.dev_attr.attr,
+	&sensor_dev_attr_fan_led_red3.dev_attr.attr,
+	&sensor_dev_attr_fan_led_red4.dev_attr.attr,
+
+	//fan GPI 
+	&sensor_dev_attr_fan_gpi.dev_attr.attr,
+	&sensor_dev_attr_psu0.dev_attr.attr,
+	&sensor_dev_attr_psu1.dev_attr.attr,
+
+
+	//psu_psoc
+	&sensor_dev_attr_psoc_psu1_vin.dev_attr.attr,
+	&sensor_dev_attr_psoc_psu1_vout.dev_attr.attr,
+	&sensor_dev_attr_psoc_psu1_iin.dev_attr.attr,
+	&sensor_dev_attr_psoc_psu1_iout.dev_attr.attr,
+	&sensor_dev_attr_psoc_psu1_pin.dev_attr.attr,
+	&sensor_dev_attr_psoc_psu1_pout.dev_attr.attr,
+	&sensor_dev_attr_psoc_psu2_vin.dev_attr.attr,
+	&sensor_dev_attr_psoc_psu2_vout.dev_attr.attr,
+	&sensor_dev_attr_psoc_psu2_iin.dev_attr.attr,
+	&sensor_dev_attr_psoc_psu2_iout.dev_attr.attr,
+	&sensor_dev_attr_psoc_psu2_pin.dev_attr.attr,
+	&sensor_dev_attr_psoc_psu2_pout.dev_attr.attr,
+
+	//ipmi_i2c_command
+	&sensor_dev_attr_thermal2_psu1.dev_attr.attr,
+	&sensor_dev_attr_psoc_psu1_vender.dev_attr.attr,
+	&sensor_dev_attr_psoc_psu1_serial.dev_attr.attr,
+	&sensor_dev_attr_psoc_psu1_version.dev_attr.attr,
+
+	&sensor_dev_attr_thermal2_psu2.dev_attr.attr,
+	&sensor_dev_attr_psoc_psu2_vender.dev_attr.attr,
+	&sensor_dev_attr_psoc_psu2_serial.dev_attr.attr,
+	&sensor_dev_attr_psoc_psu2_version.dev_attr.attr,
+
+
+	NULL
+};
+
+static const struct attribute_group psoc_group = {
+	.attrs = psoc_attributes,
+};
+
+static int __init inv_psoc_init(void)
+{
+	int ret;
+	
+    printk("+%s\n", __func__);
+
+	hwmon_dev = hwmon_device_register(NULL);
+	if (IS_ERR(hwmon_dev)) {
+		goto fail_hwmon_device_register;
+	}	
+	
+	device_kobj = kobject_create_and_add("device", &hwmon_dev->kobj);
+	if(!device_kobj) {
+		goto fail_hwmon_device_register;	
+	}
+	
+	ret = sysfs_create_group(device_kobj, &psoc_group);
+	if (ret) {
+		goto fail_create_group_hwmon;
+	}
+
+	printk(" Enable IPMI PSoC protocol.\n");
+	return ret;
+
+fail_create_group_hwmon:
+	hwmon_device_unregister(hwmon_dev);
+fail_hwmon_device_register:
+	return  -ENOMEM;
+}
+
+static void __exit inv_psoc_exit(void)
+{
+	if(ipmi_mh_user!=NULL) {ipmi_destroy_user(ipmi_mh_user);}
+	if(hwmon_dev != NULL) hwmon_device_unregister(hwmon_dev);
+	sysfs_remove_group(device_kobj, &psoc_group);
+}
+
+MODULE_AUTHOR("Ting.Jack <ting.jack@inventec>");
+MODULE_DESCRIPTION("inv psoc driver");
+MODULE_LICENSE("GPL");
+
+module_init(inv_psoc_init);
+module_exit(inv_psoc_exit);
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/modules/builds/src/inv_swps.h

@@ -0,0 +1,762 @@
+#ifndef INV_SWPS_H
+#define INV_SWPS_H
+
+#include "transceiver.h"
+#include "io_expander.h"
+#include "inv_mux.h"
+
+/* Module settings */
+#define SWP_CLS_NAME          "swps"
+#define SWP_DEV_PORT          "port"
+#define SWP_DEV_MODCTL        "module"
+#define SWP_RESET_PWD         "inventec"
+#define SWP_POLLING_PERIOD    (300)  /* msec */
+#define SWP_POLLING_ENABLE    (1)
+#define SWP_AUTOCONFIG_ENABLE (1)
+
+/* Module information */
+#define SWP_AUTHOR            "Neil <liao.neil@inventec.com>"
+#define SWP_DESC              "Inventec port and transceiver driver"
+#define SWP_VERSION           "4.2.3"
+#define SWP_LICENSE           "GPL"
+
+/* Module status define */
+#define SWP_STATE_NORMAL      (0)
+#define SWP_STATE_I2C_DIE     (-91)
+
+/* [Note]:
+ *  Functions and mechanism for auto-detect platform type is ready,
+ *  But HW and BIOS not ready! We need to wait them.
+ *  So, please do not use PLATFORM_TYPE_AUTO until they are ready.
+ *  (2016.06.13)
+ */
+#define PLATFORM_TYPE_AUTO          (100)
+#define PLATFORM_TYPE_MAGNOLIA      (111)
+#define PLATFORM_TYPE_MAGNOLIA_FNC  (112)
+#define PLATFORM_TYPE_REDWOOD       (121)
+#define PLATFORM_TYPE_REDWOOD_FSL   (122)
+#define PLATFORM_TYPE_HUDSON32I_GA  (131)
+#define PLATFORM_TYPE_SPRUCE        (141)
+#define PLATFORM_TYPE_CYPRESS_GA1   (151) /* Up -> Down */
+#define PLATFORM_TYPE_CYPRESS_GA2   (152) /* Down -> Up */
+#define PLATFORM_TYPE_LAVENDER      (161)
+/* Current running platfrom */
+#define PLATFORM_SETTINGS           PLATFORM_TYPE_LAVENDER
+
+/* Define platform flag and kernel version */
+#if (PLATFORM_SETTINGS == PLATFORM_TYPE_MAGNOLIA)
+  #define SWPS_MAGNOLIA          (1)
+  #define SWPS_KERN_VER_BF_3_8   (1)
+#elif (PLATFORM_SETTINGS == PLATFORM_TYPE_MAGNOLIA_FNC)
+  #define SWPS_MAGNOLIA          (1)
+  #define SWPS_KERN_VER_AF_3_10  (1)
+#elif (PLATFORM_SETTINGS == PLATFORM_TYPE_REDWOOD)
+  #define SWPS_REDWOOD           (1)
+  #define SWPS_KERN_VER_BF_3_8   (1)
+#elif (PLATFORM_SETTINGS == PLATFORM_TYPE_REDWOOD_FSL)
+  #define SWPS_REDWOOD_FSL       (1)
+  #define SWPS_KERN_VER_BF_3_8   (1)
+#elif (PLATFORM_SETTINGS == PLATFORM_TYPE_HUDSON32I_GA)
+  #define SWPS_HUDSON32I_GA      (1)
+  #define SWPS_KERN_VER_BF_3_8   (1)
+#elif (PLATFORM_SETTINGS == PLATFORM_TYPE_SPRUCE)
+  #define SWPS_SPRUCE            (1)
+  #define SWPS_KERN_VER_BF_3_8   (1)
+#elif (PLATFORM_SETTINGS == PLATFORM_TYPE_CYPRESS_GA1)
+  #define SWPS_CYPRESS_GA1       (1)
+  #define SWPS_KERN_VER_BF_3_8   (1)
+#elif (PLATFORM_SETTINGS == PLATFORM_TYPE_CYPRESS_GA2)
+  #define SWPS_CYPRESS_GA2       (1)
+  #define SWPS_KERN_VER_BF_3_8   (1)
+#elif (PLATFORM_SETTINGS == PLATFORM_TYPE_LAVENDER)
+  #define SWPS_LAVENDER          (1)
+  #define SWPS_KERN_VER_BF_3_8   (1)
+#endif
+
+
+struct inv_platform_s {
+    int  id;
+    char name[64];
+};
+
+struct inv_ioexp_layout_s {
+    int ioexp_id;
+    int ioexp_type;
+    struct ioexp_addr_s addr[4];
+};
+
+struct inv_port_layout_s {
+    int port_id;
+    int chan_id;
+    int ioexp_id;
+    int ioexp_offset;
+    int transvr_type;
+    int chipset_type;
+    int lane_id[8];
+};
+
+
+/* ==========================================
+ *   Inventec Platform Settings
+ * ==========================================
+ */
+struct inv_platform_s platform_map[] = {
+    {PLATFORM_TYPE_AUTO,         "Auto-Detect"  },
+    {PLATFORM_TYPE_MAGNOLIA,     "Magnolia"     },
+    {PLATFORM_TYPE_MAGNOLIA_FNC, "Magnolia_FNC" },
+    {PLATFORM_TYPE_REDWOOD,      "Redwood"      },
+    {PLATFORM_TYPE_REDWOOD_FSL,  "Redwood_FSL"  },
+    {PLATFORM_TYPE_HUDSON32I_GA, "Hudson32i"    },
+    {PLATFORM_TYPE_SPRUCE,       "Spruce"       },
+    {PLATFORM_TYPE_CYPRESS_GA1,  "Cypress_GA1"  },
+    {PLATFORM_TYPE_CYPRESS_GA2,  "Cypress_GA2"  },
+    {PLATFORM_TYPE_LAVENDER,     "Lavender"  },
+};
+
+
+/* ==========================================
+ *   Magnolia Layout configuration
+ * ==========================================
+ */
+#ifdef SWPS_MAGNOLIA
+unsigned magnolia_gpio_rest_mux = MUX_RST_GPIO_48_PAC9548;
+
+struct inv_ioexp_layout_s magnolia_ioexp_layout[] = {
+    /* IOEXP_ID / IOEXP_TYPE / { Chan_ID, Chip_addr, Read_offset, Write_offset, config_offset, data_default, conf_default } */
+    {0,  IOEXP_TYPE_MAGINOLIA_NAB, { {2, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[0] = I/O Expander N A */
+                                     {2, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, }, }, /* addr[1] = I/O Expander N B */
+    },
+    {1,  IOEXP_TYPE_MAGINOLIA_NAB, { {3, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[0] = I/O Expander N A */
+                                     {3, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, }, }, /* addr[1] = I/O Expander N B */
+    },
+    {2,  IOEXP_TYPE_MAGINOLIA_NAB, { {4, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[0] = I/O Expander N A */
+                                     {4, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, }, }, /* addr[1] = I/O Expander N B */
+    },
+    {3,  IOEXP_TYPE_MAGINOLIA_NAB, { {5, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[0] = I/O Expander N A */
+                                     {5, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, }, }, /* addr[1] = I/O Expander N B */
+    },
+    {4,  IOEXP_TYPE_MAGINOLIA_NAB, { {6, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[0] = I/O Expander N A */
+                                     {6, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, }, }, /* addr[1] = I/O Expander N B */
+    },
+    {5,  IOEXP_TYPE_MAGINOLIA_NAB, { {7, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[0] = I/O Expander N A */
+                                     {7, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, }, }, /* addr[1] = I/O Expander N B */
+    },
+    {6,  IOEXP_TYPE_MAGINOLIA_7AB, { {8, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[0] = I/O Expander 7 A */
+                                     {8, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xf0, 0x33}, }, }, /* addr[1] = I/O Expander 7 B */
+    },
+};
+
+struct inv_port_layout_s magnolia_port_layout[] = {
+    /* Port_ID / Chan_ID / IOEXP_ID / IOEXP_VIRT_OFFSET / TRANSCEIVER_TYPE / BCM_CHIP_TYPE / LANE_ID */
+    { 0,  10,  0,  0, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 16} },
+    { 1,  11,  0,  1, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 15} },
+    { 2,  12,  0,  2, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 14} },
+    { 3,  13,  0,  3, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 13} },
+    { 4,  14,  0,  4, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 24} },
+    { 5,  15,  0,  5, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 23} },
+    { 6,  16,  0,  6, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 22} },
+    { 7,  17,  0,  7, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 21} },
+    { 8,  18,  1,  0, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 28} },
+    { 9,  19,  1,  1, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 27} },
+    {10,  20,  1,  2, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 26} },
+    {11,  21,  1,  3, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 25} },
+    {12,  22,  1,  4, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 32} },
+    {13,  23,  1,  5, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 31} },
+    {14,  24,  1,  6, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 30} },
+    {15,  25,  1,  7, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 29} },
+    {16,  26,  2,  0, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 48} },
+    {17,  27,  2,  1, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 47} },
+    {18,  28,  2,  2, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 46} },
+    {19,  29,  2,  3, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 45} },
+    {20,  30,  2,  4, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 52} },
+    {21,  31,  2,  5, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 51} },
+    {22,  32,  2,  6, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 50} },
+    {23,  33,  2,  7, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 49} },
+    {24,  34,  3,  0, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 56} },
+    {25,  35,  3,  1, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 55} },
+    {26,  36,  3,  2, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 54} },
+    {27,  37,  3,  3, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 53} },
+    {28,  38,  3,  4, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 60} },
+    {29,  39,  3,  5, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 59} },
+    {30,  40,  3,  6, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 58} },
+    {31,  41,  3,  7, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 57} },
+    {32,  42,  4,  0, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 64} },
+    {33,  43,  4,  1, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 63} },
+    {34,  44,  4,  2, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 62} },
+    {35,  45,  4,  3, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 61} },
+    {36,  46,  4,  4, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 68} },
+    {37,  47,  4,  5, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 67} },
+    {38,  48,  4,  6, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 66} },
+    {39,  49,  4,  7, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 65} },
+    {40,  50,  5,  0, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 72} },
+    {41,  51,  5,  1, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 71} },
+    {42,  52,  5,  2, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 70} },
+    {43,  53,  5,  3, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 69} },
+    {44,  54,  5,  4, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 76} },
+    {45,  55,  5,  5, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 75} },
+    {46,  56,  5,  6, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 74} },
+    {47,  57,  5,  7, TRANSVR_TYPE_SFP,  BCM_CHIP_TYPE_TRIDENT_2, { 73} },
+    {48,  58,  6,  0, TRANSVR_TYPE_QSFP, BCM_CHIP_TYPE_TRIDENT_2, { 81, 82, 83, 84} },
+    {49,  59,  6,  1, TRANSVR_TYPE_QSFP, BCM_CHIP_TYPE_TRIDENT_2, { 77, 78, 79, 80} },
+    {50,  60,  6,  2, TRANSVR_TYPE_QSFP, BCM_CHIP_TYPE_TRIDENT_2, { 97, 98, 99,100} },
+    {51,  61,  6,  3, TRANSVR_TYPE_QSFP, BCM_CHIP_TYPE_TRIDENT_2, {101,102,103,104} },
+    {52,  62,  6,  4, TRANSVR_TYPE_QSFP, BCM_CHIP_TYPE_TRIDENT_2, {105,106,107,108} },
+    {53,  63,  6,  5, TRANSVR_TYPE_QSFP, BCM_CHIP_TYPE_TRIDENT_2, {109,110,111,112} },
+};
+#endif
+
+
+/* ==========================================
+ *   Redwood Layout configuration
+ * ==========================================
+ */
+#ifdef SWPS_REDWOOD
+unsigned redwood_gpio_rest_mux = MUX_RST_GPIO_48_PAC9548;
+
+struct inv_ioexp_layout_s redwood_ioexp_layout[] = {
+    /* IOEXP_ID / IOEXP_TYPE / { Chan_ID, Chip_addr, Read_offset, Write_offset, config_offset, data_default, conf_default } */
+    {0,  IOEXP_TYPE_REDWOOD_P01P08, { {4, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[0] = I/O Expander 1-4 A */
+                                      {4, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[1] = I/O Expander 1-4 B */
+                                      {0, 0x25, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0xff, 0xff}, }, }, /* addr[2] = I/O Expander 5 B   */
+    },
+    {1,  IOEXP_TYPE_REDWOOD_P09P16, { {5, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[0] = I/O Expander 1-4 A */
+                                      {5, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[1] = I/O Expander 1-4 B */
+                                      {0, 0x25, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0xff, 0xff}, }, }, /* addr[2] = I/O Expander 5 B   */
+    },
+    {2,  IOEXP_TYPE_REDWOOD_P01P08, { {2, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[0] = I/O Expander 1-4 A */
+                                      {2, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[1] = I/O Expander 1-4 B */
+                                      {0, 0x24, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0xff, 0xff}, }, }, /* addr[2] = I/O Expander 5 B   */
+    },
+    {3,  IOEXP_TYPE_REDWOOD_P09P16, { {3, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[0] = I/O Expander 1-4 A */
+                                      {3, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[1] = I/O Expander 1-4 B */
+                                      {0, 0x24, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0xff, 0xff}, }, }, /* addr[2] = I/O Expander 5 B   */
+    },
+};
+
+struct inv_port_layout_s redwood_port_layout[] = {
+    /* Port_ID / Chan_ID / IOEXP_ID / IOEXP_VIRT_OFFSET / TRANSCEIVER_TYPE / BCM_CHIP_TYPE / LANE_ID */
+    { 0,  22,  0,  0, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {  1,  2,  3,  4} },
+    { 1,  23,  0,  1, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {  5,  6,  7,  8} },
+    { 2,  24,  0,  2, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {  9, 10, 11, 12} },
+    { 3,  25,  0,  3, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 13, 14, 15, 16} },
+    { 4,  26,  0,  4, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 17, 18, 19, 20} },
+    { 5,  27,  0,  5, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 21, 22, 23, 24} },
+    { 6,  28,  0,  6, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 25, 26, 27, 28} },
+    { 7,  29,  0,  7, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 29, 30, 31, 32} },
+    { 8,  30,  1,  0, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 33, 34, 35, 36} },
+    { 9,  31,  1,  1, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 37, 38, 39, 40} },
+    {10,  32,  1,  2, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 41, 42, 43, 44} },
+    {11,  33,  1,  3, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 45, 46, 47, 48} },
+    {12,  34,  1,  4, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 49, 50, 51, 52} },
+    {13,  35,  1,  5, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 53, 54, 55, 56} },
+    {14,  36,  1,  6, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 57, 58, 59, 60} },
+    {15,  37,  1,  7, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 61, 62, 63, 64} },
+    {16,   6,  2,  0, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 65, 66, 67, 68} },
+    {17,   7,  2,  1, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 69, 70, 71, 72} },
+    {18,   8,  2,  2, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 73, 74, 75, 76} },
+    {19,   9,  2,  3, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 77, 78, 79, 80} },
+    {20,  10,  2,  4, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 81, 82, 83, 84} },
+    {21,  11,  2,  5, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 85, 86, 87, 88} },
+    {22,  12,  2,  6, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 89, 90, 91, 92} },
+    {23,  13,  2,  7, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 93, 94, 95, 96} },
+    {24,  14,  3,  0, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 97, 98, 99,100} },
+    {25,  15,  3,  1, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {101,102,103,104} },
+    {26,  16,  3,  2, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {105,106,107,108} },
+    {27,  17,  3,  3, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {109,110,111,112} },
+    {28,  18,  3,  4, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {113,114,115,116} },
+    {29,  19,  3,  5, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {117,118,119,120} },
+    {30,  20,  3,  6, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {121,122,123,124} },
+    {31,  21,  3,  7, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {125,126,127,128} },
+};
+#endif
+
+
+/* ==========================================
+ *   Hudson32i Layout configuration
+ * ==========================================
+ */
+#ifdef SWPS_HUDSON32I_GA
+unsigned hudsin32iga_gpio_rest_mux = MUX_RST_GPIO_48_PAC9548;
+
+struct inv_ioexp_layout_s hudson32iga_ioexp_layout[] = {
+    /* IOEXP_ID / IOEXP_TYPE / { Chan_ID, Chip_addr, Read_offset, Write_offset, config_offset, data_default, conf_default } */
+    {0,  IOEXP_TYPE_HUDSON32IGA_P01P08, { {2, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[0] = I/O Expander A    */
+                                          {2, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[1] = I/O Expander B    */
+                                          {0, 0x24, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0xff, 0xff}, }, }, /* addr[2] = I/O Expander 0x24 */
+    },
+    {1,  IOEXP_TYPE_HUDSON32IGA_P09P16, { {3, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[0] = I/O Expander A    */
+                                          {3, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[1] = I/O Expander B    */
+                                          {0, 0x24, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0xff, 0xff}, }, }, /* addr[2] = I/O Expander 0x24 */
+    },
+    {2,  IOEXP_TYPE_HUDSON32IGA_P01P08, { {4, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[0] = I/O Expander A    */
+                                          {4, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[1] = I/O Expander B    */
+                                          {0, 0x25, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0xff, 0xff}, }, }, /* addr[2] = I/O Expander 0x25 */
+    },
+    {3,  IOEXP_TYPE_HUDSON32IGA_P09P16, { {5, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[0] = I/O Expander A    */
+                                          {5, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[1] = I/O Expander B    */
+                                          {0, 0x25, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0xff, 0xff}, }, }, /* addr[2] = I/O Expander 0x25 */
+    },
+};
+
+struct inv_port_layout_s hudson32iga_port_layout[] = {
+    /* Port_ID / Chan_ID / IOEXP_ID / IOEXP_VIRT_OFFSET / TRANSCEIVER_TYPE / BCM_CHIP_TYPE / LANE_ID */
+    { 0,   6,  0,  0, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, {  1,  2,  3,  4} },
+    { 1,   7,  0,  1, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, {  5,  6,  7,  8} },
+    { 2,   8,  0,  2, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, {  9, 10, 11, 12} },
+    { 3,   9,  0,  3, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 13, 14, 15, 16} },
+    { 4,  10,  0,  4, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 17, 18, 19, 20} },
+    { 5,  11,  0,  5, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 21, 22, 23, 24} },
+    { 6,  12,  0,  6, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 25, 26, 27, 28} },
+    { 7,  13,  0,  7, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 29, 30, 31, 32} },
+    { 8,  14,  1,  0, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 33, 34, 35, 36} },
+    { 9,  15,  1,  1, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 37, 38, 39, 40} },
+    {10,  16,  1,  2, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 41, 42, 43, 44} },
+    {11,  17,  1,  3, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 45, 46, 47, 48} },
+    {12,  18,  1,  4, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 49, 50, 51, 52} },
+    {13,  19,  1,  5, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 53, 54, 55, 56} },
+    {14,  20,  1,  6, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 57, 58, 59, 60} },
+    {15,  21,  1,  7, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 61, 62, 63, 64} },
+    {16,  22,  2,  0, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 65, 66, 67, 68} },
+    {17,  23,  2,  1, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 69, 70, 71, 72} },
+    {18,  24,  2,  2, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 73, 74, 75, 76} },
+    {19,  25,  2,  3, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 77, 78, 79, 80} },
+    {20,  26,  2,  4, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 81, 82, 83, 84} },
+    {21,  27,  2,  5, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 85, 86, 87, 88} },
+    {22,  28,  2,  6, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 89, 90, 91, 92} },
+    {23,  29,  2,  7, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 93, 94, 95, 96} },
+    {24,  30,  3,  0, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 97, 98, 99,100} },
+    {25,  31,  3,  1, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, {101,102,103,104} },
+    {26,  32,  3,  2, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, {105,106,107,108} },
+    {27,  33,  3,  3, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, {109,110,111,112} },
+    {28,  34,  3,  4, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, {113,114,115,116} },
+    {29,  35,  3,  5, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, {117,118,119,120} },
+    {30,  36,  3,  6, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, {121,122,123,124} },
+    {31,  37,  3,  7, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, {125,126,127,128} },
+};
+#endif
+
+
+/* ==========================================
+ *   Spruce Layout configuration
+ * ==========================================
+ */
+#ifdef SWPS_SPRUCE
+unsigned spruce_gpio_rest_mux = MUX_RST_GPIO_48_PAC9548;
+
+struct inv_ioexp_layout_s spruce_ioexp_layout[] = {
+    /* IOEXP_ID / IOEXP_TYPE / { Chan_ID, Chip_addr, Read_offset, Write_offset, config_offset, data_default, conf_default } */
+    {0,  IOEXP_TYPE_SPRUCE_7AB,  { {2, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[0] = I/O Expander 7A  */
+                                   {2, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xf0, 0x33}, }, }, /* addr[2] = I/O Expander 7B  */
+    },
+};
+
+struct inv_port_layout_s spruce_port_layout[] = {
+    /* Port_ID / Chan_ID / IOEXP_ID / IOEXP_VIRT_OFFSET / TRANSCEIVER_TYPE / BCM_CHIP_TYPE / LANE_ID */
+    { 0,   6,  0,  0, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 81, 82, 83, 84} },
+    { 1,   7,  0,  1, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 77, 78, 79, 80} },
+    { 2,   8,  0,  2, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, { 97, 98, 99,100} },
+    { 3,   9,  0,  3, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, {101,102,103,104} },
+    { 4,  10,  0,  4, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, {105,106,107,108} },
+    { 5,  11,  0,  5, TRANSVR_TYPE_QSFP_PLUS, BCM_CHIP_TYPE_TRIDENT_2, {109,110,111,112} },
+};
+#endif
+
+
+/* ==========================================
+ *   Cypress Layout configuration (Inventec version [Up->Down])
+ * ==========================================
+ */
+#ifdef SWPS_CYPRESS_GA1
+unsigned cypress_ga1_gpio_rest_mux = MUX_RST_GPIO_69_PAC9548;
+
+struct inv_ioexp_layout_s cypress_ga1_ioexp_layout[] = {
+    /* IOEXP_ID / IOEXP_TYPE / { Chan_ID, Chip_addr, Read_offset, Write_offset, config_offset, data_default, conf_default } */
+    {0,  IOEXP_TYPE_CYPRESS_NABC,  { {2, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[0] = I/O Expander N A */
+                                     {2, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[1] = I/O Expander N B */
+                                     {2, 0x22, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0x00, 0x00}, }, }, /* addr[2] = I/O Expander N C */
+    },
+    {1,  IOEXP_TYPE_CYPRESS_NABC,  { {3, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[0] = I/O Expander N A */
+                                     {3, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[1] = I/O Expander N B */
+                                     {3, 0x22, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0x00, 0x00}, }, }, /* addr[2] = I/O Expander N C */
+    },
+    {2,  IOEXP_TYPE_CYPRESS_NABC,  { {4, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[0] = I/O Expander N A */
+                                     {4, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[1] = I/O Expander N B */
+                                     {4, 0x22, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0x00, 0x00}, }, }, /* addr[2] = I/O Expander N C */
+    },
+    {3,  IOEXP_TYPE_CYPRESS_NABC,  { {5, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[0] = I/O Expander N A */
+                                     {5, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[1] = I/O Expander N B */
+                                     {5, 0x22, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0x00, 0x00}, }, }, /* addr[2] = I/O Expander N C */
+    },
+    {4,  IOEXP_TYPE_CYPRESS_NABC,  { {6, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[0] = I/O Expander N A */
+                                     {6, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[1] = I/O Expander N B */
+                                     {6, 0x22, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0x00, 0x00}, }, }, /* addr[2] = I/O Expander N C */
+    },
+    {5,  IOEXP_TYPE_CYPRESS_NABC,  { {7, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[0] = I/O Expander N A */
+                                     {7, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[1] = I/O Expander N B */
+                                     {7, 0x22, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0x00, 0x00}, }, }, /* addr[2] = I/O Expander N C */
+    },
+    {6,  IOEXP_TYPE_CYPRESS_7ABC,  { {8, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0xc0, 0xc0}, },    /* addr[0] = I/O Expander 7 A */
+                                     {8, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xc0, 0xc0}, {0xff, 0xc0}, },    /* addr[1] = I/O Expander 7 B */
+                                     {8, 0x22, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0xff, 0xff}, }, }, /* addr[2] = I/O Expander 7 C */
+    },
+};
+
+struct inv_port_layout_s cypress_ga1_port_layout[] = {
+    /* Port_ID / Chan_ID / IOEXP_ID / IOEXP_VIRT_OFFSET / TRANSCEIVER_TYPE / BCM_CHIP_TYPE / LANE_ID */
+    { 0,  10,  0,  0, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, {  1} },
+    { 1,  11,  0,  1, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, {  2} },
+    { 2,  12,  0,  2, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, {  3} },
+    { 3,  13,  0,  3, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, {  4} },
+    { 4,  14,  0,  4, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, {  5} },
+    { 5,  15,  0,  5, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, {  6} },
+    { 6,  16,  0,  6, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, {  7} },
+    { 7,  17,  0,  7, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, {  8} },
+    { 8,  18,  1,  0, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, {  9} },
+    { 9,  19,  1,  1, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 10} },
+    {10,  20,  1,  2, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 11} },
+    {11,  21,  1,  3, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 12} },
+    {12,  22,  1,  4, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 21} },
+    {13,  23,  1,  5, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 22} },
+    {14,  24,  1,  6, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 23} },
+    {15,  25,  1,  7, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 24} },
+    {16,  26,  2,  0, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 33} },
+    {17,  27,  2,  1, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 34} },
+    {18,  28,  2,  2, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 35} },
+    {19,  29,  2,  3, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 36} },
+    {20,  30,  2,  4, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 37} },
+    {21,  31,  2,  5, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 38} },
+    {22,  32,  2,  6, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 39} },
+    {23,  33,  2,  7, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 40} },
+    {24,  34,  3,  0, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 41} },
+    {25,  35,  3,  1, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 42} },
+    {26,  36,  3,  2, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 43} },
+    {27,  37,  3,  3, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 44} },
+    {28,  38,  3,  4, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 49} },
+    {29,  39,  3,  5, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 50} },
+    {30,  40,  3,  6, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 51} },
+    {31,  41,  3,  7, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 52} },
+    {32,  42,  4,  0, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 53} },
+    {33,  43,  4,  1, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 54} },
+    {34,  44,  4,  2, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 55} },
+    {35,  45,  4,  3, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 56} },
+    {36,  46,  4,  4, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 65} },
+    {37,  47,  4,  5, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 66} },
+    {38,  48,  4,  6, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 67} },
+    {39,  49,  4,  7, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 68} },
+    {40,  50,  5,  0, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 69} },
+    {41,  51,  5,  1, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 70} },
+    {42,  52,  5,  2, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 71} },
+    {43,  53,  5,  3, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 72} },
+    {44,  54,  5,  4, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 81} },
+    {45,  55,  5,  5, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 82} },
+    {46,  56,  5,  6, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 83} },
+    {47,  57,  5,  7, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 84} },
+    {48,  58,  6,  0, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 97, 98, 99,100} },
+    {49,  59,  6,  1, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 85, 86, 87, 88} },
+    {50,  60,  6,  2, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {101,102,103,104} },
+    {51,  61,  6,  3, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {105,106,107,108} },
+    {52,  62,  6,  4, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {109,110,111,112} },
+    {53,  63,  6,  5, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {117,118,119,120} },
+};
+#endif
+
+
+/* ==========================================
+ *   Cypress Layout configuration (Inventec version [Down->Up])
+ * ==========================================
+ */
+#ifdef SWPS_CYPRESS_GA2
+unsigned cypress_ga2_gpio_rest_mux = MUX_RST_GPIO_FORCE_HEDERA;
+
+struct inv_ioexp_layout_s cypress_ga2_ioexp_layout[] = {
+    /* IOEXP_ID / IOEXP_TYPE / { Chan_ID, Chip_addr, Read_offset, Write_offset, config_offset, data_default, conf_default } */
+    {0,  IOEXP_TYPE_CYPRESS_NABC,  { {2, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[0] = I/O Expander N A */
+                                     {2, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[1] = I/O Expander N B */
+                                     {2, 0x22, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0x00, 0x00}, }, }, /* addr[2] = I/O Expander N C */
+    },
+    {1,  IOEXP_TYPE_CYPRESS_NABC,  { {3, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[0] = I/O Expander N A */
+                                     {3, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[1] = I/O Expander N B */
+                                     {3, 0x22, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0x00, 0x00}, }, }, /* addr[2] = I/O Expander N C */
+    },
+    {2,  IOEXP_TYPE_CYPRESS_NABC,  { {4, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[0] = I/O Expander N A */
+                                     {4, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[1] = I/O Expander N B */
+                                     {4, 0x22, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0x00, 0x00}, }, }, /* addr[2] = I/O Expander N C */
+    },
+    {3,  IOEXP_TYPE_CYPRESS_NABC,  { {5, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[0] = I/O Expander N A */
+                                     {5, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[1] = I/O Expander N B */
+                                     {5, 0x22, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0x00, 0x00}, }, }, /* addr[2] = I/O Expander N C */
+    },
+    {4,  IOEXP_TYPE_CYPRESS_NABC,  { {6, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[0] = I/O Expander N A */
+                                     {6, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[1] = I/O Expander N B */
+                                     {6, 0x22, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0x00, 0x00}, }, }, /* addr[2] = I/O Expander N C */
+    },
+    {5,  IOEXP_TYPE_CYPRESS_NABC,  { {7, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[0] = I/O Expander N A */
+                                     {7, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xf0}, {0xff, 0xf0}, },    /* addr[1] = I/O Expander N B */
+                                     {7, 0x22, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0x00, 0x00}, }, }, /* addr[2] = I/O Expander N C */
+    },
+    {6,  IOEXP_TYPE_CYPRESS_7ABC,  { {8, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0xc0, 0xc0}, },    /* addr[0] = I/O Expander 7 A */
+                                     {8, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xc0, 0xc0}, {0xff, 0xc0}, },    /* addr[1] = I/O Expander 7 B */
+                                     {8, 0x22, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0xff, 0xff}, }, }, /* addr[2] = I/O Expander 7 C */
+    },
+};
+
+struct inv_port_layout_s cypress_ga2_port_layout[] = {
+    /* Port_ID / Chan_ID / IOEXP_ID / IOEXP_VIRT_OFFSET / TRANSCEIVER_TYPE / BCM_CHIP_TYPE / LANE_ID */
+    { 0,  11,  0,  1, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, {  2} },
+    { 1,  10,  0,  0, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, {  1} },
+    { 2,  13,  0,  3, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, {  4} },
+    { 3,  12,  0,  2, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, {  3} },
+    { 4,  15,  0,  5, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, {  6} },
+    { 5,  14,  0,  4, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, {  5} },
+    { 6,  17,  0,  7, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, {  8} },
+    { 7,  16,  0,  6, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, {  7} },
+    { 8,  19,  1,  1, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 10} },
+    { 9,  18,  1,  0, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, {  9} },
+    {10,  21,  1,  3, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 12} },
+    {11,  20,  1,  2, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 11} },
+    {12,  23,  1,  5, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 22} },
+    {13,  22,  1,  4, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 21} },
+    {14,  25,  1,  7, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 24} },
+    {15,  24,  1,  6, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 23} },
+    {16,  27,  2,  1, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 34} },
+    {17,  26,  2,  0, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 33} },
+    {18,  29,  2,  3, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 36} },
+    {19,  28,  2,  2, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 35} },
+    {20,  31,  2,  5, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 38} },
+    {21,  30,  2,  4, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 37} },
+    {22,  33,  2,  7, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 40} },
+    {23,  32,  2,  6, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 39} },
+    {24,  35,  3,  1, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 42} },
+    {25,  34,  3,  0, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 41} },
+    {26,  37,  3,  3, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 44} },
+    {27,  36,  3,  2, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 43} },
+    {28,  39,  3,  5, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 50} },
+    {29,  38,  3,  4, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 49} },
+    {30,  41,  3,  7, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 52} },
+    {31,  40,  3,  6, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 51} },
+    {32,  43,  4,  1, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 54} },
+    {33,  42,  4,  0, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 53} },
+    {34,  45,  4,  3, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 56} },
+    {35,  44,  4,  2, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 55} },
+    {36,  47,  4,  5, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 66} },
+    {37,  46,  4,  4, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 65} },
+    {38,  49,  4,  7, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 68} },
+    {39,  48,  4,  6, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 67} },
+    {40,  51,  5,  1, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 70} },
+    {41,  50,  5,  0, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 69} },
+    {42,  53,  5,  3, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 72} },
+    {43,  52,  5,  2, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 71} },
+    {44,  55,  5,  5, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 82} },
+    {45,  54,  5,  4, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 81} },
+    {46,  57,  5,  7, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 84} },
+    {47,  56,  5,  6, TRANSVR_TYPE_SFP,     BCM_CHIP_TYPE_TOMAHAWK, { 83} },
+    {48,  59,  6,  1, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 85, 86, 87, 88} },
+    {49,  58,  6,  0, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 97, 98, 99,100} },
+    {50,  61,  6,  3, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {105,106,107,108} },
+    {51,  60,  6,  2, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {101,102,103,104} },
+    {52,  63,  6,  5, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {117,118,119,120} },
+    {53,  62,  6,  4, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {109,110,111,112} },
+};
+#endif
+
+
+
+/* ==========================================
+ *   Redwood_fsl Layout configuration
+ * ==========================================
+ */
+#ifdef SWPS_REDWOOD_FSL
+unsigned redwood_fsl_gpio_rest_mux = MUX_RST_GPIO_48_PAC9548;
+
+struct inv_ioexp_layout_s redwood_fsl_ioexp_layout[] = {
+    /* IOEXP_ID / IOEXP_TYPE / { Chan_ID, Chip_addr, Read_offset, Write_offset, config_offset, data_default, conf_default } */
+    {0,  IOEXP_TYPE_REDWOOD_P01P08, { {4, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[0] = I/O Expander 1-4 A */
+                                      {4, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[1] = I/O Expander 1-4 B */
+                                      {0, 0x25, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0xff, 0xff}, }, }, /* addr[2] = I/O Expander 5 B   */
+    },
+    {1,  IOEXP_TYPE_REDWOOD_P09P16, { {5, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[0] = I/O Expander 1-4 A */
+                                      {5, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[1] = I/O Expander 1-4 B */
+                                      {0, 0x25, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0xff, 0xff}, }, }, /* addr[2] = I/O Expander 5 B   */
+    },
+    {2,  IOEXP_TYPE_REDWOOD_P01P08, { {2, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[0] = I/O Expander 1-4 A */
+                                      {2, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[1] = I/O Expander 1-4 B */
+                                      {0, 0x24, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0xff, 0xff}, }, }, /* addr[2] = I/O Expander 5 B   */
+    },
+    {3,  IOEXP_TYPE_REDWOOD_P09P16, { {3, 0x20, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[0] = I/O Expander 1-4 A */
+                                      {3, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0x0f}, },    /* addr[1] = I/O Expander 1-4 B */
+                                      {0, 0x24, {0, 1}, {2, 3}, {6, 7}, {0xff, 0xff}, {0xff, 0xff}, }, }, /* addr[2] = I/O Expander 5 B   */
+    },
+};
+
+
+struct inv_port_layout_s redwood_fsl_port_layout[] = {
+    /* Port_ID / Chan_ID / IOEXP_ID / IOEXP_VIRT_OFFSET / TRANSCEIVER_TYPE / BCM_CHIP_TYPE / LANE_ID */
+    { 0,  22,  0,  0, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {  1,  2,  3,  4} },
+    { 1,  23,  0,  1, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {  5,  6,  7,  8} },
+    { 2,  24,  0,  2, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {  9, 10, 11, 12} },
+    { 3,  25,  0,  3, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 13, 14, 15, 16} },
+    { 4,  26,  0,  4, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 17, 18, 19, 20} },
+    { 5,  27,  0,  5, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 21, 22, 23, 24} },
+    { 6,  28,  0,  6, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 25, 26, 27, 28} },
+    { 7,  29,  0,  7, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 29, 30, 31, 32} },
+    { 8,  30,  1,  0, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 33, 34, 35, 36} },
+    { 9,  31,  1,  1, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 37, 38, 39, 40} },
+    {10,  32,  1,  2, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 41, 42, 43, 44} },
+    {11,  33,  1,  3, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 45, 46, 47, 48} },
+    {12,  34,  1,  4, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 49, 50, 51, 52} },
+    {13,  35,  1,  5, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 53, 54, 55, 56} },
+    {14,  36,  1,  6, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 57, 58, 59, 60} },
+    {15,  37,  1,  7, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 61, 62, 63, 64} },
+    {16,   6,  2,  0, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 65, 66, 67, 68} },
+    {17,   7,  2,  1, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 69, 70, 71, 72} },
+    {18,   8,  2,  2, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 73, 74, 75, 76} },
+    {19,   9,  2,  3, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 77, 78, 79, 80} },
+    {20,  10,  2,  4, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 81, 82, 83, 84} },
+    {21,  11,  2,  5, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 85, 86, 87, 88} },
+    {22,  12,  2,  6, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 89, 90, 91, 92} },
+    {23,  13,  2,  7, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 93, 94, 95, 96} },
+    {24,  14,  3,  0, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, { 97, 98, 99,100} },
+    {25,  15,  3,  1, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {101,102,103,104} },
+    {26,  16,  3,  2, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {105,106,107,108} },
+    {27,  17,  3,  3, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {109,110,111,112} },
+    {28,  18,  3,  4, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {113,114,115,116} },
+    {29,  19,  3,  5, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {117,118,119,120} },
+    {30,  20,  3,  6, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {121,122,123,124} },
+    {31,  21,  3,  7, TRANSVR_TYPE_QSFP_28, BCM_CHIP_TYPE_TOMAHAWK, {125,126,127,128} },
+};
+#endif
+
+
+/* ==========================================
+ *   Lavender Layout configuration
+ * ==========================================
+ */
+#ifdef SWPS_LAVENDER
+unsigned lavender_gpio_rest_mux = MUX_RST_GPIO_69_PAC9548;
+
+struct inv_ioexp_layout_s lavender_ioexp_layout[] = {
+    /* IOEXP_ID / IOEXP_TYPE / { Chan_ID, Chip_addr, Read_offset, Write_offset, config_offset, data_default, conf_default } */
+    {0,  IOEXP_TYPE_LAVENDER_P01P08, { {1, 0x20, {0, 1}, {2, 3}, {6, 7}, {0x00, 0xff}, {0x00, 0x00}, },    /* addr[0] = I/O Expander 1-4 A */
+                                       {1, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0xff}, },    /* addr[1] = I/O Expander 1-4 B */
+                                       {1, 0x22, {0, 1}, {2, 3}, {6, 7}, {0x00, 0xff}, {0xff, 0xff}, },    /* addr[2] = I/O Expander 1-4 C */
+                                     },
+    },
+    {1,  IOEXP_TYPE_LAVENDER_P09P16, { {2, 0x20, {0, 1}, {2, 3}, {6, 7}, {0x00, 0xff}, {0x00, 0x00}, },    /* addr[0] = I/O Expander 1-4 A */
+                                       {2, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0xff}, },    /* addr[1] = I/O Expander 1-4 B */
+                                       {2, 0x22, {0, 1}, {2, 3}, {6, 7}, {0x00, 0xff}, {0xff, 0xff}, },    /* addr[2] = I/O Expander 1-4 C */
+                                     },
+    },
+    {2,  IOEXP_TYPE_LAVENDER_P01P08, { {3, 0x20, {0, 1}, {2, 3}, {6, 7}, {0x00, 0xff}, {0x00, 0x00}, },    /* addr[0] = I/O Expander 1-4 A */
+                                       {3, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0xff}, },    /* addr[1] = I/O Expander 1-4 B */
+                                       {3, 0x22, {0, 1}, {2, 3}, {6, 7}, {0x00, 0xff}, {0xff, 0xff}, },    /* addr[2] = I/O Expander 1-4 C */
+                                     },
+    },
+    {3,  IOEXP_TYPE_LAVENDER_P09P16, { {4, 0x20, {0, 1}, {2, 3}, {6, 7}, {0x00, 0xff}, {0x00, 0x00}, },    /* addr[0] = I/O Expander 1-4 A */
+                                       {4, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0xff}, },    /* addr[1] = I/O Expander 1-4 B */
+                                       {4, 0x22, {0, 1}, {2, 3}, {6, 7}, {0x00, 0xff}, {0xff, 0xff}, },    /* addr[2] = I/O Expander 1-4 C */
+                                     },
+    },
+    {4,  IOEXP_TYPE_LAVENDER_P01P08, { {9, 0x20, {0, 1}, {2, 3}, {6, 7}, {0x00, 0xff}, {0x00, 0x00}, },    /* addr[0] = I/O Expander 1-4 A */
+                                       {9, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0xff}, },    /* addr[1] = I/O Expander 1-4 B */
+                                       {9, 0x22, {0, 1}, {2, 3}, {6, 7}, {0x00, 0xff}, {0xff, 0xff}, },    /* addr[2] = I/O Expander 1-4 C */
+                                     },
+    },
+    {5,  IOEXP_TYPE_LAVENDER_P09P16, { {10, 0x20, {0, 1}, {2, 3}, {6, 7}, {0x00, 0xff}, {0x00, 0x00}, },    /* addr[0] = I/O Expander 1-4 A */
+                                       {10, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0xff}, },    /* addr[1] = I/O Expander 1-4 B */
+                                       {10, 0x22, {0, 1}, {2, 3}, {6, 7}, {0x00, 0xff}, {0xff, 0xff}, },    /* addr[2] = I/O Expander 1-4 C */
+                                     },
+    },
+    {6,  IOEXP_TYPE_LAVENDER_P01P08, { {11, 0x20, {0, 1}, {2, 3}, {6, 7}, {0x00, 0xff}, {0x00, 0x00}, },    /* addr[0] = I/O Expander 1-4 A */
+                                       {11, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0xff}, },    /* addr[1] = I/O Expander 1-4 B */
+                                       {11, 0x22, {0, 1}, {2, 3}, {6, 7}, {0x00, 0xff}, {0xff, 0xff}, },    /* addr[2] = I/O Expander 1-4 C */
+                                     },
+    },
+    {7,  IOEXP_TYPE_LAVENDER_P09P16, { {12, 0x20, {0, 1}, {2, 3}, {6, 7}, {0x00, 0xff}, {0x00, 0x00}, },    /* addr[0] = I/O Expander 1-4 A */
+                                       {12, 0x21, {0, 1}, {2, 3}, {6, 7}, {0xff, 0x00}, {0x00, 0xff}, },    /* addr[1] = I/O Expander 1-4 B */
+                                       {12, 0x22, {0, 1}, {2, 3}, {6, 7}, {0x00, 0xff}, {0xff, 0xff}, },    /* addr[2] = I/O Expander 1-4 C */
+                                     },
+    },
+    {8,  IOEXP_TYPE_LAVENDER_P65,    { {5, 0x22, {0, 1}, {2, 3}, {6, 7}, {0xf6, 0xff}, {0xf8, 0xff}, },    /* addr[0] = I/O Expander */
+                                     },
+    },
+};
+
+struct inv_port_layout_s lavender_port_layout[] = {
+    /* Port_ID / Chan_ID / IOEXP_ID / IOEXP_VIRT_OFFSET / TRANSCEIVER_TYPE / BCM_CHIP_TYPE / LANE_ID */
+    { 0,  17,  0,  0, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {  1,  2,  3,  4} },
+    { 1,  18,  0,  1, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {  5,  6,  7,  8} },
+    { 2,  19,  0,  2, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {  9, 10, 11, 12} },
+    { 3,  20,  0,  3, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 13, 14, 15, 16} },
+    { 4,  21,  0,  4, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 17, 18, 19, 20} },
+    { 5,  22,  0,  5, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 21, 22, 23, 24} },
+    { 6,  23,  0,  6, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 25, 26, 27, 28} },
+    { 7,  24,  0,  7, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 29, 30, 31, 32} },
+    { 8,  25,  1,  0, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 33, 34, 35, 36} },
+    { 9,  26,  1,  1, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 37, 38, 39, 40} },
+    {10,  27,  1,  2, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 41, 42, 43, 44} },
+    {11,  28,  1,  3, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 45, 46, 47, 48} },
+    {12,  29,  1,  4, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 49, 50, 51, 52} },
+    {13,  30,  1,  5, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 53, 54, 55, 56} },
+    {14,  31,  1,  6, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 57, 58, 59, 60} },
+    {15,  32,  1,  7, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 61, 62, 63, 64} },
+    {16,  33,  2,  0, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 65, 66, 67, 68} },
+    {17,  34,  2,  1, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 69, 70, 71, 72} },
+    {18,  35,  2,  2, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 73, 74, 75, 76} },
+    {19,  36,  2,  3, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 77, 78, 79, 80} },
+    {20,  37,  2,  4, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 81, 82, 83, 84} },
+    {21,  38,  2,  5, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 85, 86, 87, 88} },
+    {22,  39,  2,  6, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 89, 90, 91, 92} },
+    {23,  40,  2,  7, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 93, 94, 95, 96} },
+    {24,  41,  3,  0, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, { 97, 98, 99,100} },
+    {25,  42,  3,  1, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {101,102,103,104} },
+    {26,  43,  3,  2, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {105,106,107,108} },
+    {27,  44,  3,  3, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {109,110,111,112} },
+    {28,  45,  3,  4, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {113,114,115,116} },
+    {29,  46,  3,  5, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {117,118,119,120} },
+    {30,  47,  3,  6, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {121,122,123,124} },
+    {31,  48,  3,  7, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {125,126,127,128} },
+
+    {32,  49,  4,  0, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {129,130,131,132} },
+    {33,  50,  4,  1, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {133,134,135,136} },
+    {34,  51,  4,  2, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {137,138,139,140} },
+    {35,  52,  4,  3, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {141,142,143,144} },
+    {36,  53,  4,  4, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {145,146,147,148} },
+    {37,  54,  4,  5, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {149,150,151,152} },
+    {38,  55,  4,  6, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {153,154,155,156} },
+    {39,  56,  4,  7, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {157,158,159,160} },
+
+    {40,  57,  5,  0, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {161,162,163,164} },
+    {41,  58,  5,  1, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {165,166,167,168} },
+    {42,  59,  5,  2, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {169,170,171,172} },
+    {43,  60,  5,  3, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {173,174,175,176} },
+    {44,  61,  5,  4, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {177,178,179,180} },
+    {45,  62,  5,  5, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {181,182,183,184} },
+    {46,  63,  5,  6, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {185,186,187,188} },
+    {47,  64,  5,  7, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {189,190,191,192} },
+
+    {48,  65,  6,  0, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {193,194,195,196} },
+    {49,  66,  6,  1, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {197,198,199,200} },
+    {50,  67,  6,  2, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {201,202,203,204} },
+    {51,  68,  6,  3, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {205,206,207,208} },
+    {52,  69,  6,  4, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {209,210,211,212} },
+    {53,  70,  6,  5, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {213,214,215,216} },
+    {54,  71,  6,  6, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {217,218,219,220} },
+    {55,  72,  6,  7, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {221,222,223,224} },
+
+    {56,  73,  7,  0, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {225,226,227,228} },
+    {57,  74,  7,  1, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {229,230,231,232} },
+    {58,  75,  7,  2, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {233,234,235,236} },
+    {59,  76,  7,  3, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {237,238,239,240} },
+    {60,  77,  7,  4, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {241,242,243,244} },
+    {61,  78,  7,  5, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {245,246,247,248} },
+    {62,  79,  7,  6, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {249,250,251,252} },
+    {63,  80,  7,  7, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {253,254,255,256} },
+    {64,   5,  8,  0, TRANSVR_TYPE_QSFP_28, CHIP_TYPE_D5264Q28B, {257,258,259,260} },
+};
+#endif
+
+
+#endif /* INV_SWPS_H */
+
+
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/modules/builds/src/inv_vpd.c

@@ -0,0 +1,338 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/device.h>
+#include <linux/types.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+#include <linux/jiffies.h>
+#include <linux/dmi.h>
+#include <linux/i2c.h>
+#include "inv_vpd.h"
+#include "onie_tlvinfo.h"
+
+static int vpd_major;
+static struct class *vpd_class_p = NULL;
+static char cEeprom[SYS_EEPROM_MAX_SIZE];
+static DEFINE_MUTEX(vpd_mutex); 
+
+static int
+__swp_match(struct device *dev,
+#ifdef VPD_KERN_VER_AF_3_10
+
+            const void *data){
+#else
+            void *data){
+#endif
+
+    char *name = (char *)data;
+    if (strcmp(dev_name(dev), name) == 0)
+        return 1;
+    return 0;
+}
+
+static
+int get_vpd_data(struct i2c_client *pi2c_client, int i_offset, char *c_buf)
+{
+    int iRet;
+	
+	read_eeprom( pi2c_client, cEeprom);
+ 	iRet = tlvinfo_decode_tlv(cEeprom, i_offset,c_buf);
+    return iRet;
+}
+
+static
+int write_vpd_data(struct i2c_client *pi2c_client, int i_offset, char *c_buf)
+{
+    int iErr = 0;
+
+    if (read_eeprom(pi2c_client, cEeprom)) {
+         printk(KERN_ERR "write vpd data eror at %d-%s\n", __LINE__, __FUNCTION__);
+         return -1;
+    }
+
+    if (tlvinfo_delete_tlv(cEeprom, i_offset) == TRUE) {
+		    }
+    if (c_buf) {
+        if(!tlvinfo_add_tlv(cEeprom, i_offset , c_buf)) {
+            printk(KERN_ERR "write vpd data eror at %d-%s\n", __LINE__, __FUNCTION__);
+            iErr = -1;
+        } else {
+            iErr = prog_eeprom(pi2c_client,cEeprom);
+        }
+    }
+    return iErr;
+}
+
+static struct device *
+get_swpdev_by_name(char *name){
+    struct device *dev = class_find_device(vpd_class_p,
+                                           NULL,
+                                           name,
+                                           __swp_match);
+    return dev;
+}
+
+static ssize_t
+store_attr_vpd(struct device *dev_p,
+                      struct device_attribute *attr_p,
+                      const char *buf_p,
+                      size_t count){
+    struct i2c_client *pi2c_client = dev_get_drvdata(dev_p);
+	struct vpd_device_attribute *attr = to_vpd_dev_attr(attr_p);
+    int iOffset = attr->index;
+	int iErr , iLen;
+    char *pChar;
+
+    if (!pi2c_client){
+        return -ENODEV;
+    }
+	mutex_lock(&vpd_mutex);
+
+    //-strip 0x0a in the last byte.
+    for (iLen = 0, pChar = buf_p; 
+         iLen < 255 && *pChar != 0; 
+         iLen++, pChar++) ;
+    if (iLen !=0 && *pChar == 0 && *(pChar-1) == 0x0a)
+      *(pChar - 1) = 0;
+    //-    
+   
+	iErr = write_vpd_data( pi2c_client, iOffset, buf_p);
+
+	mutex_unlock(&vpd_mutex);
+	return count;
+}
+
+static ssize_t
+show_attr_vpd(struct device *dev_p,
+                 struct device_attribute *attr_p,
+                 char *buf_p){
+
+    struct i2c_client *pi2c_client = dev_get_drvdata(dev_p);
+	struct vpd_device_attribute *attr = to_vpd_dev_attr(attr_p);
+    int iOffset = attr->index;
+	int iErr , iLen;
+
+    if (!pi2c_client){
+        return -ENODEV;
+    }
+	mutex_lock(&vpd_mutex);
+	iErr = get_vpd_data( pi2c_client, iOffset, buf_p);
+	mutex_unlock(&vpd_mutex);
+
+	if( iErr <= 0 )
+		iLen = 0;
+    else
+	    iLen = snprintf(buf_p, TLV_DECODE_VALUE_MAX_LEN, "%s\n", buf_p);
+
+	return iLen;
+}
+
+/* ================= Vpd attribute ========================
+ */
+static VPD_DEVICE_ATTR(product_name ,S_IWUSR|S_IRUGO, show_attr_vpd, store_attr_vpd, TLV_CODE_PRODUCT_NAME  );
+static VPD_DEVICE_ATTR(pn           ,S_IWUSR|S_IRUGO, show_attr_vpd, store_attr_vpd, TLV_CODE_PART_NUMBER );
+static VPD_DEVICE_ATTR(sn           ,S_IWUSR|S_IRUGO, show_attr_vpd, store_attr_vpd, TLV_CODE_SERIAL_NUMBER );
+static VPD_DEVICE_ATTR(base_mac_addr,S_IWUSR|S_IRUGO, show_attr_vpd, store_attr_vpd, TLV_CODE_MAC_BASE );
+static VPD_DEVICE_ATTR(man_date     ,S_IWUSR|S_IRUGO, show_attr_vpd, store_attr_vpd, TLV_CODE_MANUF_DATE  );
+static VPD_DEVICE_ATTR(dev_ver      ,S_IWUSR|S_IRUGO, show_attr_vpd, store_attr_vpd, TLV_CODE_DEVICE_VERSION );
+static VPD_DEVICE_ATTR(label_rev    ,S_IWUSR|S_IRUGO, show_attr_vpd, store_attr_vpd, TLV_CODE_LABEL_REVISION );
+static VPD_DEVICE_ATTR(plat_name    ,S_IWUSR|S_IRUGO, show_attr_vpd, store_attr_vpd, TLV_CODE_PLATFORM_NAME );
+static VPD_DEVICE_ATTR(ldr_ver      ,S_IWUSR|S_IRUGO, show_attr_vpd, store_attr_vpd, TLV_CODE_ONIE_VERSION  );
+static VPD_DEVICE_ATTR(mac_addr     ,S_IWUSR|S_IRUGO, show_attr_vpd, store_attr_vpd, TLV_CODE_MAC_SIZE  );
+static VPD_DEVICE_ATTR(manufacturer ,S_IWUSR|S_IRUGO, show_attr_vpd, store_attr_vpd, TLV_CODE_MANUF_NAME  );
+static VPD_DEVICE_ATTR(country_code ,S_IWUSR|S_IRUGO, show_attr_vpd, store_attr_vpd, TLV_CODE_MANUF_COUNTRY  );
+static VPD_DEVICE_ATTR(vendor_name  ,S_IWUSR|S_IRUGO, show_attr_vpd, store_attr_vpd, TLV_CODE_VENDOR_NAME  );
+static VPD_DEVICE_ATTR(diag_ver     ,S_IWUSR|S_IRUGO, show_attr_vpd, store_attr_vpd, TLV_CODE_DIAG_VERSION  );
+static VPD_DEVICE_ATTR(service_tag  ,S_IWUSR|S_IRUGO, show_attr_vpd, store_attr_vpd, TLV_CODE_SERVICE_TAG  );
+static VPD_DEVICE_ATTR(vendor_ext   ,S_IWUSR|S_IRUGO, show_attr_vpd, store_attr_vpd, TLV_CODE_VENDOR_EXT  );
+static VPD_DEVICE_ATTR(crc32        ,S_IRUGO, show_attr_vpd, NULL, TLV_CODE_CRC_32  );
+
+static void
+clean_vpd_common(void)
+{
+    dev_t dev_num;
+    struct device *device_p;
+
+    device_p = get_swpdev_by_name(VPD_DEVICE);
+    if (device_p){
+        dev_num = MKDEV(vpd_major, 1);
+        device_unregister(device_p);
+        device_destroy(vpd_class_p, dev_num);
+    }
+    VPD_DEBUG("%s: done.\n", __func__);
+}
+
+
+static struct register_attr VpdRegAttr[VPD_ENTRY_SIZE ] ={
+    { &vpd_dev_attr_product_name.dev_attr, "vpd_dev_attr_product_name"},
+    { &vpd_dev_attr_pn.dev_attr, "vpd_dev_attr_pn"},
+    { &vpd_dev_attr_sn.dev_attr, "vpd_dev_attr_sn"},
+    { &vpd_dev_attr_base_mac_addr.dev_attr, "vpd_dev_attr_base_mac_addr"},
+    { &vpd_dev_attr_man_date.dev_attr, "vpd_dev_attr_man_date"},
+    { &vpd_dev_attr_dev_ver.dev_attr, "vpd_dev_attr_dev_ver"},
+    { &vpd_dev_attr_label_rev.dev_attr, "vpd_dev_attr_label_rev"},
+    { &vpd_dev_attr_plat_name.dev_attr, "vpd_dev_attr_plat_name"},
+    { &vpd_dev_attr_ldr_ver.dev_attr, "vpd_dev_attr_ldr_ver"},
+    { &vpd_dev_attr_mac_addr.dev_attr, "vpd_dev_attr_mac_addr"},
+    { &vpd_dev_attr_manufacturer.dev_attr, "vpd_dev_attr_manufacturer"},
+    { &vpd_dev_attr_country_code.dev_attr, "vpd_dev_attr_country_code"},
+    { &vpd_dev_attr_vendor_name.dev_attr, "vpd_dev_attr_vendor_name"},
+    { &vpd_dev_attr_diag_ver.dev_attr, "vpd_dev_attr_diag_ver"},
+    { &vpd_dev_attr_service_tag.dev_attr, "vpd_dev_attr_service_tag"},
+    { &vpd_dev_attr_vendor_ext.dev_attr, "vpd_dev_attr_vendor_ext"},
+    { &vpd_dev_attr_crc32.dev_attr, "vpd_dev_attr_crc32"},
+};
+
+static int
+register_vpd_attr(struct device *device_p){
+
+    char *err_attr = NULL;
+    int i;
+
+    for( i = 0 ; i <VPD_ENTRY_SIZE ;i++ ){
+        if(device_create_file(device_p, VpdRegAttr[ i ].attr) < 0) {
+            err_attr = VpdRegAttr[ i ].errmsg;
+            goto err_register_vpd_attr;
+        }
+    }
+    return 0;
+
+err_register_vpd_attr:
+    VPD_ERR("%s: %s\n", __func__, err_attr);
+    return -1;
+}
+
+
+static int
+register_vpd_device(void)
+{
+    struct device *device_p = NULL;
+    int minor_comm = 0; /* Default minor number for common device */
+    dev_t dev_num  = MKDEV(vpd_major, minor_comm);
+    char *err_msg  = "ERROR";
+    struct i2c_adapter *adap;
+    struct i2c_client *vpd_i2c_client = NULL;
+
+    vpd_i2c_client = kzalloc(sizeof(*vpd_i2c_client), GFP_KERNEL);
+    if (!vpd_i2c_client){
+        printk(KERN_ERR "can not kzalloc client:%d", VPD_I2C_BUS);
+        goto err_register_vpd_device;
+    }
+
+    adap = i2c_get_adapter(VPD_I2C_BUS);
+    vpd_i2c_client->adapter = adap;
+    vpd_i2c_client->addr = VPD_I2C_ADDR;
+
+    device_p = device_create(vpd_class_p,     /* struct class *cls     */
+                             NULL,            /* struct device *parent */
+                             dev_num,         /* dev_t devt            */
+                             vpd_i2c_client,  /* void *private_data    */
+                             VPD_DEVICE);    /* const char *fmt       */
+    if (IS_ERR(device_p)){
+        err_msg = "device_create fail";
+        goto err_register_vpd_device_1;
+    }
+    if (register_vpd_attr(device_p) < 0) {
+        err_msg = "register_vpd_attr fail";
+        goto err_register_vpd_device_2;
+    }
+    return 0;
+
+err_register_vpd_device_2:
+    device_unregister(device_p);
+    device_destroy(vpd_class_p, dev_num);
+err_register_vpd_device_1:
+    kfree(vpd_i2c_client);
+    vpd_i2c_client = NULL;
+err_register_vpd_device:
+    VPD_ERR("%s: %s\n", __func__, err_msg);
+    return -1;
+}
+
+static int
+register_vpd_module(void)
+{
+    dev_t vpd_devt  = 0;
+
+    if (alloc_chrdev_region(&vpd_devt, 0, 1, VPD_DEVICE) < 0){
+        VPD_WARN("Allocate VPD MAJOR failure! \n");
+        goto err_register_vpd_module;
+    }
+    vpd_major  = MAJOR(vpd_devt);
+
+    /* Create class object */
+    vpd_class_p = class_create(THIS_MODULE, EEPROM_CLASS);
+    if (IS_ERR(vpd_class_p)) {
+        VPD_ERR("Create class failure! \n");
+        goto err_register_vpd_module_1;
+    }
+    return 0;
+
+err_register_vpd_module_1:
+    unregister_chrdev_region(MKDEV(vpd_major, 0), 1);
+err_register_vpd_module:
+    return -1;
+}
+
+
+static int
+init_vpd_common(void)
+{
+    char *err_msg = "ERR";
+    
+    if (register_vpd_device() < 0) {
+        err_msg = "register_vpd_device fail";
+        goto err_init_vpd_common;
+    }
+    return 0;
+
+err_init_vpd_common:
+    VPD_ERR("%s: %s\n", __func__, err_msg);
+    return -1;
+}
+
+
+static int __init
+vpd_module_init(void)
+{
+    if (register_vpd_module() < 0){
+        goto err_vpd_module_init;
+    }
+    if (init_vpd_common() < 0){
+        goto err_vpd_module_init_1;
+    }
+    VPD_INFO("Inventec vpd module V.%s initial success.\n", VPD_VERSION);
+    return 0;
+
+err_vpd_module_init_1:
+    class_unregister(vpd_class_p);
+    class_destroy(vpd_class_p);
+    unregister_chrdev_region(MKDEV(vpd_major, 0), 1);
+err_vpd_module_init:
+    VPD_ERR("Inventec vpd module V.%s initial failure.\n", VPD_VERSION);
+    return -1;
+}
+
+
+static void __exit
+vpd_module_exit(void)
+{
+    clean_vpd_common();
+    class_unregister(vpd_class_p);
+    class_destroy(vpd_class_p);
+    unregister_chrdev_region(MKDEV(vpd_major, 0), 1);
+    VPD_INFO("Remove Inventec vpd module success.\n");
+}
+
+
+/*  Module information  */
+MODULE_AUTHOR(VPD_AUTHOR);
+MODULE_DESCRIPTION(VPD_DESC);
+MODULE_VERSION(VPD_VERSION);
+MODULE_LICENSE(VPD_LICENSE);
+
+module_init(vpd_module_init);
+module_exit(vpd_module_exit);

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/modules/builds/src/inv_vpd.h

@@ -0,0 +1,46 @@
+#ifndef INV_VPD_H
+#define INV_VPD_H
+
+#define EEPROM_CLASS   "eeprom"
+#define VPD_DEVICE     "vpd"
+#define VPD_AUTHOR     "Neil <liao.neil@inventec.com>"
+#define VPD_DESC       "Inventec eeprom vpd driver"
+#define VPD_VERSION    "1.0.0"
+#define VPD_LICENSE    "GPL"
+
+#define VPD_ENTRY_SIZE        (17)
+#define VPD_I2C_BUS           (0)
+#define VPD_I2C_ADDR          (0x53)
+
+struct register_attr {
+struct device_attribute *attr;
+char * errmsg;
+};
+
+struct vpd_device_attribute{
+    struct device_attribute dev_attr;
+    int index;
+};
+
+#define to_vpd_dev_attr(_dev_attr) \
+    container_of(_dev_attr, struct vpd_device_attribute, dev_attr)
+
+#define VPD_ATTR(_name, _mode, _show, _store, _index)   \
+    { .dev_attr = __ATTR(_name, _mode, _show, _store),  \
+    .index = _index }
+
+#define VPD_DEVICE_ATTR(_name, _mode, _show, _store, _index)    \
+    struct vpd_device_attribute vpd_dev_attr_##_name            \
+    = VPD_ATTR(_name, _mode, _show, _store, _index)
+
+#define VPD_INFO(fmt, args...) printk( KERN_INFO "[VPD] " fmt, ##args)
+#define VPD_WARN(fmt, args...) printk( KERN_WARNING "[VPD] " fmt, ##args)
+#define VPD_ERR(fmt, args...)  printk( KERN_ERR  "[VPD] " fmt, ##args)
+
+#ifdef DEBUG_VPD
+#    define VPD_DEBUG(fmt, args...)  printk( KERN_DEBUG  "[VPD] " fmt, ##args)
+#else
+#    define VPD_DEBUG(fmt, args...)
+#endif
+
+#endif /* INV_VPD_H */

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/modules/builds/src/io_expander.h

@@ -0,0 +1,172 @@
+#ifndef IO_EXPANDER_H
+#define IO_EXPANDER_H
+
+#include <linux/types.h>
+
+
+/* IOEXP type define (SFP series) */
+#define IOEXP_TYPE_MAGINOLIA_NAB      (10101)
+#define IOEXP_TYPE_CYPRESS_NABC       (10102)
+
+/* IOEXP type define (QSFP series) */
+#define IOEXP_TYPE_MAGINOLIA_7AB      (10201)
+#define IOEXP_TYPE_REDWOOD_P01P08     (10202)
+#define IOEXP_TYPE_REDWOOD_P09P16     (10203)
+#define IOEXP_TYPE_HUDSON32IGA_P01P08 (10204)
+#define IOEXP_TYPE_HUDSON32IGA_P09P16 (10205)
+#define IOEXP_TYPE_SPRUCE_7AB         (10206)
+#define IOEXP_TYPE_CYPRESS_7ABC       (10207)
+#define IOEXP_TYPE_LAVENDER_P01P08    (10208)
+#define IOEXP_TYPE_LAVENDER_P09P16    (10209)
+#define IOEXP_TYPE_LAVENDER_P65       (10210)
+
+/* IOEXP mode define */
+#define IOEXP_MODE_POLLING            (19000)
+#define IOEXP_MODE_DIRECT             (19001)
+
+/* IOEXP state define */
+#define STATE_IOEXP_NORMAL                (0)
+#define STATE_IOEXP_INIT                 (-1)
+#define STATE_IOEXP_ABNORMAL             (-2)
+
+/* IOEXP error code define */
+#define ERR_IOEXP_NOTSUPPORT           (-100)
+#define ERR_IOEXP_UNINIT               (-101)
+#define ERR_IOEXP_BADCONF              (-102)
+#define ERR_IOEXP_ABNORMAL             (-103)
+#define ERR_IOEXP_NOSTATE              (-104)
+#define ERR_IOEXP_BADINPUT             (-105)
+#define ERR_IOEXP_UNEXCPT              (-199)
+
+
+#define SWPS_INFO(fmt, args...) printk( KERN_INFO "[SWPS] " fmt, ##args)
+#define SWPS_WARN(fmt, args...) printk( KERN_WARNING "[SWPS] " fmt, ##args)
+#define SWPS_ERR(fmt, args...)  printk( KERN_ERR  "[SWPS] " fmt, ##args)
+
+#ifdef DEBUG_SWPS
+#    define SWPS_DEBUG(fmt, args...)  printk( KERN_DEBUG  "[SWPS] " fmt, ##args)
+#else
+#    define SWPS_DEBUG(fmt, args...)
+#endif
+
+
+struct ioexp_addr_s {
+    int chan_id;
+    int chip_addr;
+    int read_offset[8];
+    int write_offset[8];
+    int conf_offset[8];
+    uint8_t data_default[8]; 
+    uint8_t conf_default[8]; 
+};
+
+struct ioexp_i2c_s {
+    int chip_id;
+    struct i2c_client  *i2c_client_p;
+    struct ioexp_i2c_s *next;
+};
+
+
+struct ioexp_bitmap_s {
+    int chip_id;        /* IOEXP chip id        */
+    int ioexp_voffset;  /* IOEXP virtual offset */
+    int bit_shift;
+};
+
+struct ioexp_map_s {
+    int chip_amount;    /* Number of chips that IOEXP object content    */
+    int data_width;     /* Number of (Read/Write/Config) bytes          */
+    struct ioexp_addr_s   *map_addr;          /* Chip address info      */
+    struct ioexp_bitmap_s  map_present[8];    /* IOEXP for SFP / QSFP   */
+    struct ioexp_bitmap_s  map_tx_disable[8]; /* IOEXP for SFP          */
+    struct ioexp_bitmap_s  map_tx_fault[8];   /* IOEXP for SFP          */
+    struct ioexp_bitmap_s  map_rxlos[8];      /* IOEXP for SFP          */
+    struct ioexp_bitmap_s  map_reset[8];      /* IOEXP for QSFP         */
+    struct ioexp_bitmap_s  map_lpmod[8];      /* IOEXP for QSFP         */
+    struct ioexp_bitmap_s  map_modsel[8];     /* IOEXP for QSFP         */
+    struct ioexp_bitmap_s  map_hard_rs0[8];   /* IOEXP for QSFP         */
+    struct ioexp_bitmap_s  map_hard_rs1[8];   /* IOEXP for QSFP         */
+};
+
+struct ioexp_data_s {
+    uint8_t data[8];
+};
+
+struct ioexp_obj_s {
+
+    /* ============================
+     *  Object public property
+     * ============================
+     */
+    int ioexp_id;
+    int ioexp_type;
+
+    /* ============================
+     *  Object private property
+     * ============================
+     */
+    struct ioexp_data_s chip_data[16];   /* Max: 8-ioexp in one virt-ioexp(ioexp_obj) */
+    struct ioexp_map_s *ioexp_map_p;
+    struct ioexp_obj_s *next;
+    struct ioexp_i2c_s *i2c_head_p;
+    struct mutex lock;
+    int mode;
+    int state;
+
+    /* ===========================================
+     *  Object public functions
+     * ===========================================
+     */
+    int (*get_present)(struct ioexp_obj_s *self, int virt_offset);
+    int (*get_tx_fault)(struct ioexp_obj_s *self, int virt_offset);
+    int (*get_rxlos)(struct ioexp_obj_s *self, int virt_offset);
+    int (*get_tx_disable)(struct ioexp_obj_s *self, int virt_offset);
+    int (*get_reset)(struct ioexp_obj_s *self, int virt_offset);
+    int (*get_lpmod)(struct ioexp_obj_s *self, int virt_offset);
+    int (*get_modsel)(struct ioexp_obj_s *self, int virt_offset);
+    int (*get_hard_rs0)(struct ioexp_obj_s *self, int virt_offset);
+    int (*get_hard_rs1)(struct ioexp_obj_s *self, int virt_offset);
+    int (*set_tx_disable)(struct ioexp_obj_s *self, int virt_offset, int input_val);
+    int (*set_reset)(struct ioexp_obj_s *self, int virt_offset, int input_val);
+    int (*set_lpmod)(struct ioexp_obj_s *self, int virt_offset, int input_val);
+    int (*set_modsel)(struct ioexp_obj_s *self, int virt_offset, int input_val);
+    int (*set_hard_rs0)(struct ioexp_obj_s *self, int virt_offset, int input_val);
+    int (*set_hard_rs1)(struct ioexp_obj_s *self, int virt_offset, int input_val);
+
+    /* ===========================================
+     *  Object private functions
+     * ===========================================
+     */
+    int (*init)(struct ioexp_obj_s *self);
+    int (*check)(struct ioexp_obj_s *self);
+    int (*update_all)(struct ioexp_obj_s *self, int show_err, char *caller_name);
+    int (*fsm_4_direct)(struct ioexp_obj_s* self);
+    int (*fsm_4_polling)(struct ioexp_obj_s* self);
+};
+
+
+struct ioexp_obj_s* get_ioexp_obj(int ioexp_id);
+int  create_ioexp_obj(int ioexp_id,
+                      int ioexp_type,
+                      struct ioexp_addr_s *addr_map_p,
+                      int run_mode);
+int  init_ioexp_objs(void);
+int  check_ioexp_objs(void);
+void clean_ioexp_objs(void);
+
+void unlock_ioexp_all(void);
+int  lock_ioexp_all(void);
+
+int  check_channel_tier_1(void);
+int  resync_channel_tier_1(void);
+
+/* Macro for bit control */
+#define SWP_BIT_SET(byte_val,bit_shift)   ((byte_val) |= (1<<(bit_shift)))
+#define SWP_BIT_CLEAR(byte_val,bit_shift) ((byte_val) &= ~(1<<(bit_shift)))
+
+
+#endif /* IO_EXPANDER_H */
+
+
+
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/modules/builds/src/onie_tlvinfo.c

@@ -0,0 +1,820 @@
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/ctype.h>
+//#include <linux/crc32.h>
+#include <linux/delay.h>
+
+//#include <linux/slab.h>
+//#include <linux/platform_device.h>
+#include "onie_tlvinfo.h"
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read = 0;
+
+int read_sys_eeprom(struct i2c_client *pi2c_client,void *eeprom_data, int offset, int len);
+int write_sys_eeprom(struct i2c_client *pi2c_client, void *eeprom_data, int len);
+
+static inline int is_multicast_ether_addr(const u_int8_t *addr)
+{
+    return 0x01 & addr[0];
+}
+
+static inline int is_zero_ether_addr(const u_int8_t *addr)
+{
+    return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]);
+}
+
+static inline int is_valid_ether_addr(const u_int8_t *addr)
+{
+    return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr);
+}
+
+#if 0
+static unsigned int crc32(unsigned char const *p, unsigned int len)
+{
+	int i;
+	unsigned int crc = 0;
+	while (len--) {
+		crc ^= *p++;
+		for (i = 0; i < 8; i++)
+			crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0);
+	}
+	return crc;
+}
+#else
+static unsigned long crc32_tab[] = {
+	0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
+	0xe963a535, 0x9e6495a3,	0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
+	0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
+	0xf3b97148, 0x84be41de,	0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
+	0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,	0x14015c4f, 0x63066cd9,
+	0xfa0f3d63, 0x8d080df5,	0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
+	0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,	0x35b5a8fa, 0x42b2986c,
+	0xdbbbc9d6, 0xacbcf940,	0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
+	0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
+	0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
+	0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,	0x76dc4190, 0x01db7106,
+	0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
+	0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
+	0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
+	0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
+	0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
+	0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
+	0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
+	0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
+	0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
+	0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
+	0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
+	0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
+	0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
+	0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
+	0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
+	0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
+	0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
+	0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
+	0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
+	0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
+	0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
+	0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
+	0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
+	0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
+	0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
+	0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
+	0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
+	0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
+	0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
+	0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
+	0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
+	0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
+};
+
+static unsigned long crc32(unsigned char const *buf, unsigned int size)
+{
+	unsigned char *p = buf;
+	unsigned long crc = 0;
+
+    crc = crc ^ ~0U;
+
+	while (size--)
+		crc = crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8);
+
+	return crc ^ ~0U;
+}
+#endif
+
+static int set_bytes(char *buf, const char *string, int * converted_accum)
+{
+    char *p = (char *) string;
+    int   i;
+    uint  byte;
+
+    if (!p) {
+	printk("ERROR: NULL string passed in.\n");
+	return -1;
+    }
+    /* Convert string to bytes */
+    for (i = 0, p = (char *)string; (i < TLV_VALUE_MAX_LEN) && (*p != 0);
+	 i++) {
+	while ((*p == ' ') || (*p == '\t') || (*p == ',') ||
+	       (*p == ';')) {
+	    p++;
+	}
+	if (*p != 0) {
+	    if (!isdigit(*p)) {
+		printk("ERROR: Non-digit found in byte string: (%s)\n", string);
+		return -1;
+	    }
+	    byte = strtoul(p, &p, 0);
+	    if (byte >= 256) {
+		printk("ERROR: The value specified is greater than 255: (%u) " \
+		       "in string: %s\n", byte, string);
+		return -1;
+	    }
+	    buf[i] = byte & 0xFF;
+	}
+    }
+    if ((i == TLV_VALUE_MAX_LEN) && (*p != 0)) {
+	printk("ERROR: Trying to assign too many bytes "
+	       "(max: %d) in string: %s\n", TLV_VALUE_MAX_LEN, string);
+	return -1;
+    }
+    *converted_accum = i;
+    return 0;
+}
+
+/*
+ *  set_date
+ *
+ *  Validates the format of the data string
+ *
+ *  This function takes a pointer to a date string (i.e. MM/DD/YYYY hh:mm:ss)
+ *  and validates that the format is correct. If so the string is copied
+ *  to the supplied buffer.
+ */
+static int set_date(char *buf, const char *string)
+{
+    int i;
+
+    if (!string) {
+	printk("ERROR: NULL date string passed in.\n");
+	return -1;
+    }
+    if (strlen(string) != 19) {
+	printk("ERROR: Date strlen() != 19 -- %d\n", strlen(string));
+	printk("ERROR: Bad date format (MM/DD/YYYY hh:mm:ss): %s\n", string);
+	return -1;
+    }
+    for (i = 0; string[i] != 0; i++) {
+	switch (i) {
+	case 2:
+	case 5:
+	    if (string[i] != '/') {
+		printk("ERROR: Bad date format (MM/DD/YYYY hh:mm:ss): %s\n",
+		       string);
+		return -1;
+	    }
+	    break;
+	case 10:
+	    if (string[i] != ' ') {
+		printk("ERROR: Bad date format (MM/DD/YYYY hh:mm:ss): %s\n",
+		       string);
+		return -1;
+	    }
+	    break;
+	case 13:
+	case 16:
+	    if (string[i] != ':') {
+		printk("ERROR: Bad date format (MM/DD/YYYY hh:mm:ss): %s\n",
+		       string);
+		return -1;
+	    }
+	    break;
+	default:
+	    if (!isdigit(string[i])) {
+		printk("ERROR: Bad date format (MM/DD/YYYY hh:mm:ss): %s\n",
+		       string);
+		return -1;
+	    }
+	    break;
+	}
+    }
+    strcpy(buf, string);
+    return 0;
+}
+
+/*
+ *  is_valid_tlv
+ *
+ *  Perform basic sanity checks on a TLV field. The TLV is pointed to
+ *  by the parameter provided.
+ *      1. The type code is not reserved (0x00 or 0xFF)
+ */
+static inline bool is_valid_tlv(tlvinfo_tlv_t *tlv)
+{
+    return((tlv->type != 0x00) && (tlv->type != 0xFF));
+}
+
+/*
+ *  set_mac
+ *
+ *  Converts a string MAC address into a binary buffer.
+ *
+ *  This function takes a pointer to a MAC address string
+ *  (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number).
+ *  The string format is verified and then converted to binary and
+ *  stored in a buffer.
+ */
+static int set_mac(char *buf, const char *string)
+{
+    char *p = (char *) string;
+    int   i;
+    int   err = 0;
+    char *end;
+
+    if (!p) {
+	printk("ERROR: NULL mac addr string passed in.\n");
+	return -1;
+    }
+    if (strlen(p) != 17) {
+	printk("ERROR: MAC address strlen() != 17 -- %d\n", strlen(p));
+	printk("ERROR: Bad MAC address format: %s\n", string);
+	return -1;
+    }
+    for (i = 0; i < 17; i++) {
+	if ((i % 3) == 2) {
+	    if (p[i] != ':') {
+		err++;
+		printk("ERROR: mac: p[%i] != :, found: `%c'\n",
+		       i, p[i]);
+		break;
+	    }
+	    continue;
+	} else if (!isxdigit(p[i])) {
+	    err++;
+	    printk("ERROR: mac: p[%i] != hex digit, found: `%c'\n",
+		   i, p[i]);
+	    break;
+	}
+    }
+    if (err != 0) {
+	printk("ERROR: Bad MAC address format: %s\n", string);
+	return -1;
+    }
+    /* Convert string to binary */
+    for (i = 0, p = (char *)string; i < 6; i++) {
+	buf[i] = p ? strtoul(p, &end, 16) : 0;
+	if (p) {
+	    p = (*end) ? end + 1 : end;
+	}
+    }
+    if (!is_valid_ether_addr((char *)buf)) {
+	printk("ERROR: MAC address must not be 00:00:00:00:00:00, "
+	       "a multicast address or FF:FF:FF:FF:FF:FF.\n");
+	printk("ERROR: Bad MAC address format: %s\n", string);
+	return -1;
+    }
+    return 0;
+}
+
+/*
+ *  is_valid_tlvinfo_header
+ *
+ *  Perform sanity checks on the first 11 bytes of the TlvInfo EEPROM
+ *  data pointed to by the parameter:
+ *      1. First 8 bytes contain null-terminated ASCII string "TlvInfo"
+ *      2. Version byte is 1
+ *      3. Total length bytes contain value which is less than or equal
+ *         to the allowed maximum (2048-11)
+ *
+ */
+static inline bool is_valid_tlvinfo_header(tlvinfo_header_t *hdr)
+{
+    int max_size = TLV_TOTAL_LEN_MAX;
+    return((strcmp(hdr->signature, TLV_INFO_ID_STRING) == 0) &&
+	   (hdr->version == TLV_INFO_VERSION) &&
+	   (be16_to_cpu(hdr->totallen) <= max_size) );
+}
+
+/*
+ *  decode_tlv_value
+ *
+ *  Decode a single TLV value into a string.
+
+ *  The validity of EEPROM contents and the TLV field have been verified
+ *  prior to calling this function.
+ */
+#define DECODE_NAME_MAX     20
+
+static void decode_tlv_value(tlvinfo_tlv_t * tlv, char* value)
+{
+    int i;
+
+    switch (tlv->type) {
+    case TLV_CODE_PRODUCT_NAME:
+    case TLV_CODE_PART_NUMBER:
+    case TLV_CODE_SERIAL_NUMBER:
+    case TLV_CODE_MANUF_DATE:
+    case TLV_CODE_LABEL_REVISION:
+    case TLV_CODE_PLATFORM_NAME:
+    case TLV_CODE_ONIE_VERSION:
+    case TLV_CODE_MANUF_NAME:
+    case TLV_CODE_MANUF_COUNTRY:
+    case TLV_CODE_VENDOR_NAME:
+    case TLV_CODE_DIAG_VERSION:
+    case TLV_CODE_SERVICE_TAG:
+	memcpy(value, tlv->value, tlv->length);
+	value[tlv->length] = 0;
+	break;
+    case TLV_CODE_MAC_BASE:
+	snprintf(value, MAX_STRING_SIZE, "%02X:%02X:%02X:%02X:%02X:%02X",
+		tlv->value[0], tlv->value[1], tlv->value[2],
+		tlv->value[3], tlv->value[4], tlv->value[5]);
+	break;
+    case TLV_CODE_DEVICE_VERSION:
+	snprintf(value, MAX_STRING_SIZE, "%u", tlv->value[0]);
+	break;
+    case TLV_CODE_MAC_SIZE:
+	snprintf(value, MAX_STRING_SIZE, "%u", (tlv->value[0] << 8) | tlv->value[1]);
+	break;
+    case TLV_CODE_VENDOR_EXT:
+	value[0] = 0;
+	for (i = 0; (i < (TLV_DECODE_VALUE_MAX_LEN/5)) && (i < tlv->length);
+	     i++) {
+	    snprintf(value, MAX_STRING_SIZE, "%s 0x%02X", value, tlv->value[i]);
+	}
+	break;
+    case TLV_CODE_CRC_32:
+	snprintf(value, MAX_STRING_SIZE, "0x%02X%02X%02X%02X",
+		tlv->value[0], tlv->value[1], tlv->value[2],
+		tlv->value[3]);
+	break;
+    default:
+	value[0] = 0;
+	for (i = 0; (i < (TLV_DECODE_VALUE_MAX_LEN/5)) && (i < tlv->length);
+	     i++) {
+	    snprintf(value, MAX_STRING_SIZE, "%s 0x%02X", value, tlv->value[i]);
+	}
+	break;
+    }
+
+}
+
+/*
+ *  is_checksum_valid
+ *
+ *  Validate the checksum in the provided TlvInfo EEPROM data. First,
+ *  verify that the TlvInfo header is valid, then make sure the last
+ *  TLV is a CRC-32 TLV. Then calculate the CRC over the EEPROM data
+ *  and compare it to the value stored in the EEPROM CRC-32 TLV.
+ */
+static bool is_checksum_valid(u_int8_t *eeprom)
+{
+    tlvinfo_header_t * eeprom_hdr = (tlvinfo_header_t *) eeprom;
+    tlvinfo_tlv_t    * eeprom_crc;
+    unsigned int       calc_crc;
+    unsigned int       stored_crc;
+
+    // Is the eeprom header valid?
+    if (!is_valid_tlvinfo_header(eeprom_hdr)) {
+	return(FALSE);
+    }
+
+    // Is the last TLV a CRC?
+    eeprom_crc = (tlvinfo_tlv_t *) &eeprom[sizeof(tlvinfo_header_t) +
+					   be16_to_cpu(eeprom_hdr->totallen) -
+					   (sizeof(tlvinfo_tlv_t) + 4)];
+    if ((eeprom_crc->type != TLV_CODE_CRC_32) || (eeprom_crc->length != 4)) {
+	return(FALSE);
+    }
+ 
+    // Calculate the checksum
+    calc_crc = crc32((void *)eeprom, sizeof(tlvinfo_header_t) +
+		     be16_to_cpu(eeprom_hdr->totallen) - 4);
+    stored_crc = ((eeprom_crc->value[0] << 24) | (eeprom_crc->value[1] << 16) |
+		  (eeprom_crc->value[2] <<  8) | eeprom_crc->value[3]);
+
+    //printk(KERN_ERR "[SWPS] cal_crc =0x%x, stored_crc =0x%x\n", calc_crc, stored_crc);
+    //return(calc_crc == stored_crc);
+    return 1; 
+}
+
+/*
+ *  update_crc
+ *
+ *  This function updates the CRC-32 TLV. If there is no CRC-32 TLV, then
+ *  one is added. This function should be called after each update to the
+ *  EEPROM structure, to make sure the CRC is always correct.
+ */
+static void update_crc(u_int8_t *eeprom)
+{
+    tlvinfo_header_t * eeprom_hdr = (tlvinfo_header_t *) eeprom;
+    tlvinfo_tlv_t    * eeprom_crc;
+    unsigned int       calc_crc;
+
+    // Is the eeprom header valid?
+    if (!is_valid_tlvinfo_header(eeprom_hdr)) {
+	return;
+    }
+    // Is the last TLV a CRC?
+    eeprom_crc = (tlvinfo_tlv_t *) &eeprom[sizeof(tlvinfo_header_t) +
+					   be16_to_cpu(eeprom_hdr->totallen) -
+					   (sizeof(tlvinfo_tlv_t) + 4)];
+    if (eeprom_crc->type != TLV_CODE_CRC_32) {
+	if ((be16_to_cpu(eeprom_hdr->totallen) + sizeof(tlvinfo_tlv_t) + 4) >
+	    TLV_TOTAL_LEN_MAX) {
+	    return;
+	}
+	eeprom_crc = (tlvinfo_tlv_t *) &eeprom[sizeof(tlvinfo_header_t) +
+					       be16_to_cpu(
+						   eeprom_hdr->totallen)];
+	eeprom_hdr->totallen = cpu_to_be16(be16_to_cpu(eeprom_hdr->totallen) +
+					   sizeof(tlvinfo_tlv_t) + 4);
+	eeprom_crc->type = TLV_CODE_CRC_32;
+    }
+    eeprom_crc->length = 4;
+
+    // Calculate the checksum
+    calc_crc = crc32((void *)eeprom,
+		     sizeof(tlvinfo_header_t) +
+		     be16_to_cpu(eeprom_hdr->totallen) - 4);
+
+    eeprom_crc->value[0] = (calc_crc >> 24) & 0xFF;
+    eeprom_crc->value[1] = (calc_crc >> 16) & 0xFF;
+    eeprom_crc->value[2] = (calc_crc >>  8) & 0xFF;
+    eeprom_crc->value[3] = (calc_crc >>  0) & 0xFF;
+}
+
+/*
+ *  show_eeprom
+ *
+ *  Display the contents of the EEPROM
+ */
+
+/*
+ *  read_eeprom
+ *
+ *  Read the EEPROM into memory, if it hasn't already been read.
+ */
+int read_eeprom( struct i2c_client *pi2c_client, u_int8_t *eeprom)
+{
+    int ret;
+    tlvinfo_header_t *eeprom_hdr = (tlvinfo_header_t *) eeprom;
+    tlvinfo_tlv_t *eeprom_tlv = (tlvinfo_tlv_t *)&eeprom[
+	sizeof(tlvinfo_header_t)];
+
+    if (has_been_read)
+	return 0;
+
+    /* Read the header */
+    ret = read_sys_eeprom( pi2c_client,(void *)eeprom_hdr, 0, sizeof(tlvinfo_header_t));
+    /* If the header was successfully read, read the TLVs */
+    if ((ret == 0) && is_valid_tlvinfo_header(eeprom_hdr)) {
+	    ret = read_sys_eeprom( pi2c_client, (void *)eeprom_tlv, sizeof(tlvinfo_header_t),
+			      be16_to_cpu(eeprom_hdr->totallen));
+    }
+    // If the contents are invalid, start over with default contents
+    if(!is_valid_tlvinfo_header(eeprom_hdr))
+	    printk(KERN_ERR
+                "Notice:  Invalid TLV header found.  Using default contents--1.\n");
+    if(!is_checksum_valid(eeprom))
+	    printk(KERN_ERR
+                "Notice:  Invalid TLV checksum found.  Using default contents--2.\n");
+    if ( !is_valid_tlvinfo_header(eeprom_hdr) || !is_checksum_valid(eeprom) ){
+	    strcpy(eeprom_hdr->signature, TLV_INFO_ID_STRING);
+	    eeprom_hdr->version = TLV_INFO_VERSION;
+	    eeprom_hdr->totallen = cpu_to_be16(0);
+	    update_crc(eeprom);
+    }
+    has_been_read = 1;
+
+    return ret;
+}
+EXPORT_SYMBOL(read_eeprom);
+
+/*
+ *  prog_eeprom
+ *  Write the EEPROM data from CPU memory to the hardware.
+ */
+int prog_eeprom(struct i2c_client *pi2c_client, u_int8_t * eeprom)
+{
+    int ret = 0;
+    tlvinfo_header_t * eeprom_hdr = (tlvinfo_header_t *) eeprom;
+    int eeprom_len;
+
+    eeprom_len = sizeof(tlvinfo_header_t) + be16_to_cpu(eeprom_hdr->totallen);
+    ret = write_sys_eeprom( pi2c_client, eeprom, eeprom_len);
+    if (ret) {
+	printk("Programming failed.\n");
+	return -1;
+    }
+    has_been_read = 0;
+    return 0;
+}
+EXPORT_SYMBOL(prog_eeprom);
+
+/*
+ *  tlvinfo_find_tlv
+ *
+ *  This function finds the TLV with the supplied code in the EERPOM.
+ *  An offset from the beginning of the EEPROM is returned in the
+ *  eeprom_index parameter if the TLV is found.
+ */
+bool tlvinfo_find_tlv(u_int8_t *eeprom, u_int8_t tcode,
+			     int *eeprom_index)
+{
+    tlvinfo_header_t * eeprom_hdr = (tlvinfo_header_t *) eeprom;
+    tlvinfo_tlv_t    * eeprom_tlv;
+    int eeprom_end;
+
+    // Make sure the EEPROM contents are valid
+    if (!is_valid_tlvinfo_header(eeprom_hdr) || !is_checksum_valid(eeprom)) {
+	return(FALSE);
+    }
+    // Search through the TLVs, looking for the first one which matches the
+    // supplied type code.
+    *eeprom_index = sizeof(tlvinfo_header_t);
+    eeprom_end = sizeof(tlvinfo_header_t) + be16_to_cpu(eeprom_hdr->totallen);
+    
+    while (*eeprom_index < eeprom_end) {
+	eeprom_tlv = (tlvinfo_tlv_t *) &eeprom[*eeprom_index];
+	if (!is_valid_tlv(eeprom_tlv)) {
+	    return(FALSE);
+	}
+	if (eeprom_tlv->type == tcode) {
+	    return(TRUE);
+	}
+	*eeprom_index += sizeof(tlvinfo_tlv_t) + eeprom_tlv->length;
+    }
+    return(FALSE);
+}
+
+/*
+ *  tlvinfo_decode_tlv
+ *
+ *  This function finds the TLV with the supplied code in the EERPOM
+ *  and decodes the value into the buffer provided.
+ */
+bool tlvinfo_decode_tlv(u_int8_t *eeprom, u_int8_t tcode, char* value)
+{
+    int eeprom_index;
+    tlvinfo_tlv_t * eeprom_tlv;
+
+    // Find the TLV and then decode it
+
+    if (tlvinfo_find_tlv(eeprom, tcode, &eeprom_index)) {
+        eeprom_tlv = (tlvinfo_tlv_t *) &eeprom[eeprom_index];
+        decode_tlv_value(eeprom_tlv, value);
+        return TRUE;
+    }
+
+    return FALSE;
+}
+EXPORT_SYMBOL(tlvinfo_decode_tlv);
+
+/*
+ *  tlvinfo_delete_tlv
+ *
+ *  This function deletes the TLV with the specified type code from the
+ *  EEPROM.
+ */
+bool tlvinfo_delete_tlv(u_int8_t * eeprom, u_int8_t code)
+{
+    int eeprom_index;
+    int tlength;
+    tlvinfo_header_t * eeprom_hdr = (tlvinfo_header_t *) eeprom;
+    tlvinfo_tlv_t * eeprom_tlv;
+
+    // Find the TLV and then move all following TLVs "forward"
+    if (tlvinfo_find_tlv(eeprom, code, &eeprom_index)) {
+	eeprom_tlv = (tlvinfo_tlv_t *) &eeprom[eeprom_index];
+	tlength = sizeof(tlvinfo_tlv_t) + eeprom_tlv->length;
+	memcpy(&eeprom[eeprom_index], &eeprom[eeprom_index+tlength],
+	       sizeof(tlvinfo_header_t) + be16_to_cpu(eeprom_hdr->totallen) -
+	       eeprom_index - tlength);
+	eeprom_hdr->totallen = cpu_to_be16(be16_to_cpu(eeprom_hdr->totallen) -
+					   tlength);
+	update_crc(eeprom);
+	return(TRUE);
+    }
+    return(FALSE);
+}
+EXPORT_SYMBOL(tlvinfo_delete_tlv);
+
+/*
+ *  tlvinfo_add_tlv
+ *
+ *  This function adds a TLV to the EEPROM, converting the value (a string) to
+ *  the format in which it will be stored in the EEPROM.
+ */
+#define MAX_TLV_VALUE_LEN   256
+bool tlvinfo_add_tlv(u_int8_t * eeprom, int tcode, char * strval)
+{
+    tlvinfo_header_t * eeprom_hdr = (tlvinfo_header_t *) eeprom;
+    tlvinfo_tlv_t * eeprom_tlv;
+    int new_tlv_len = 0;
+    u_int32_t value;
+    char data[MAX_TLV_VALUE_LEN];
+    int eeprom_index;
+    int max_size = TLV_TOTAL_LEN_MAX;
+
+    // Encode each TLV type into the format to be stored in the EERPOM
+    switch (tcode) {
+    case TLV_CODE_PRODUCT_NAME:
+    case TLV_CODE_PART_NUMBER:
+    case TLV_CODE_SERIAL_NUMBER:
+    case TLV_CODE_LABEL_REVISION:
+    case TLV_CODE_PLATFORM_NAME:
+    case TLV_CODE_ONIE_VERSION:
+    case TLV_CODE_MANUF_NAME:
+    case TLV_CODE_MANUF_COUNTRY:
+    case TLV_CODE_VENDOR_NAME:
+    case TLV_CODE_DIAG_VERSION:
+    case TLV_CODE_SERVICE_TAG:
+	strncpy(data, strval, MAX_TLV_VALUE_LEN);
+
+	if( strlen(strval) >= MAX_TLV_VALUE_LEN )
+        new_tlv_len = MAX_TLV_VALUE_LEN;
+    else
+        new_tlv_len = strlen(strval);
+
+	break;
+    case TLV_CODE_DEVICE_VERSION:
+	value = strtoul(strval, NULL, 0);
+	if (value >= 256) {
+	    printk("ERROR: Device version must be 255 or less. Value " \
+		   "supplied: %u", value);
+	    return(FALSE);
+	}
+	data[0] = value & 0xFF;
+	new_tlv_len = 1;
+	break;
+    case TLV_CODE_MAC_SIZE:
+	value = strtoul(strval, NULL, 0);
+	if (value >= 65536) {
+	    printk("ERROR: MAC Size must be 65535 or less. Value " \
+		   "supplied: %u", value);
+	    return(FALSE);
+	}
+	data[0] = (value >> 8) & 0xFF;
+	data[1] = value & 0xFF;
+	new_tlv_len = 2;
+	break;
+    case TLV_CODE_MANUF_DATE:
+	if (set_date(data, strval) != 0) {
+	    return(FALSE);
+	}
+	new_tlv_len = 19;
+	break;
+    case TLV_CODE_MAC_BASE:
+	if (set_mac(data, strval) != 0) {
+	    return(FALSE);
+	}
+	new_tlv_len = 6;
+	break;
+    case TLV_CODE_CRC_32:
+	printk("WARNING: The CRC TLV is set automatically and cannot be set " \
+	       "manually.\n");
+	return(FALSE);
+    case TLV_CODE_VENDOR_EXT:
+    default:
+	if (set_bytes(data, strval, &new_tlv_len) != 0 ) {
+	    return(FALSE);
+	}
+	break;
+    }
+
+    // Is there room for this TLV?
+    if ((be16_to_cpu(eeprom_hdr->totallen) + sizeof(tlvinfo_tlv_t) +
+	 new_tlv_len) > max_size) {
+	printk("ERROR: There is not enough room in the EERPOM to save data.\n");
+	return(FALSE);
+    }
+
+    // Add TLV at the end, overwriting CRC TLV if it exists
+    if (tlvinfo_find_tlv(eeprom, TLV_CODE_CRC_32, &eeprom_index)) {
+	eeprom_hdr->totallen = cpu_to_be16(be16_to_cpu(eeprom_hdr->totallen)
+					   - sizeof(tlvinfo_tlv_t) - 4);
+    } else {
+	eeprom_index = sizeof(tlvinfo_header_t) +
+	    be16_to_cpu(eeprom_hdr->totallen);
+    }
+    eeprom_tlv = (tlvinfo_tlv_t *) &eeprom[eeprom_index];
+    eeprom_tlv->type = tcode;
+    eeprom_tlv->length = new_tlv_len;
+    memcpy(eeprom_tlv->value, data, new_tlv_len);
+
+    // Update the total length and calculate (add) a new CRC-32 TLV
+    eeprom_hdr->totallen = cpu_to_be16(be16_to_cpu(eeprom_hdr->totallen) +
+				       sizeof(tlvinfo_tlv_t) + new_tlv_len);
+    update_crc(eeprom);
+
+    return(TRUE);
+}
+EXPORT_SYMBOL(tlvinfo_add_tlv);
+
+/*
+ * read_sys_eeprom - read the hwinfo from i2c EEPROM
+ */
+int read_sys_eeprom(struct i2c_client *pi2c_client,void *eeprom_data, int offset, int len)
+{
+    int iRet = 0;
+    int i = 0;
+    unsigned char ucBuf[2];
+    u_int8_t *c;
+    unsigned short  usAddr = SYS_EEPROM_OFFSET + offset;
+
+    c = eeprom_data;
+    for (i = 0; i < len; i++) {
+        ucBuf[0] = (usAddr & 0xFF00) >> 8;
+        ucBuf[1] = (usAddr & 0x00FF);
+       
+        iRet = i2c_smbus_write_byte_data(pi2c_client, ucBuf[0], ucBuf[1]);
+        if( iRet < 0 ){
+            printk(KERN_ERR"Error!! VPD data read error\n");
+            return -1;
+        }
+
+        *c = i2c_smbus_read_byte(pi2c_client);
+        c++; usAddr++;
+    }
+    return 0;
+}
+
+/*
+ * write_sys_eeprom - write the hwinfo to i2c EEPROM
+ */
+int write_sys_eeprom(struct i2c_client *pi2c_client, void *eeprom_data, int len)
+{
+    int iRet = 0;
+    int i = 0;
+    u_int8_t *c;
+    unsigned short usAddr = SYS_EEPROM_OFFSET;
+    unsigned char ucBuf[3];
+
+    c = eeprom_data;
+    for (i = 0; i < len; i++) {
+        ucBuf[ 0 ] = (usAddr & 0xFF00) >>8 ;
+        ucBuf[ 1 ] = (usAddr & 0x00FF);
+        ucBuf[ 2 ] = *c;
+
+        iRet = i2c_smbus_write_word_data( pi2c_client, ucBuf[0], (ucBuf[2] << 8 | ucBuf[1]));
+        if (iRet < 0 ){
+            printk(KERN_ERR"Error!! VPD data write error . \n");
+            return -1;
+        }
+
+        c++; usAddr++;
+        msleep_interruptible(10);
+    }
+
+    return 0;
+}
+
+void update_eeprom_header(u_int8_t *eeprom)
+{
+    tlvinfo_header_t * eeprom_hdr = (tlvinfo_header_t *) eeprom;
+
+    strcpy(eeprom_hdr->signature, TLV_INFO_ID_STRING);
+    eeprom_hdr->version = TLV_INFO_VERSION;
+    eeprom_hdr->totallen = cpu_to_be16(0);
+    update_crc(eeprom);
+}
+#if 0
+int  find_vpd_data(u_int8_t *eeprom, int i_offset, char *c_buf)
+{
+    int tlv_end;
+    int curr_tlv;
+    tlvinfo_header_t * eeprom_hdr = (tlvinfo_header_t *) eeprom;
+    tlvinfo_tlv_t    * eeprom_tlv;
+    int iFind = 0;
+
+    if( !is_valid_tlvinfo_header(eeprom_hdr) ) {
+        printk(KERN_ERR"EEPROM does not contain data in a valid TlvInfo format.\n");
+        return -1;
+    }
+
+    curr_tlv = sizeof(tlvinfo_header_t);
+    tlv_end  = sizeof(tlvinfo_header_t) + be16_to_cpu(eeprom_hdr->totallen);
+    while(curr_tlv < tlv_end){
+        eeprom_tlv = (tlvinfo_tlv_t *) &eeprom[curr_tlv];
+        if (!is_valid_tlv(eeprom_tlv)) {
+            printk(KERN_ERR"Invalid TLV field starting at EEPROM offset %d\n",
+                curr_tlv);
+            return -1;
+        }
+
+        decode_tlv_value(eeprom_tlv, c_buf);
+        if( eeprom_tlv->type == i_offset){
+            iFind = 1;
+            break;
+        }
+        curr_tlv += sizeof(tlvinfo_tlv_t) + eeprom_tlv->length;
+    }
+
+    if( iFind == 0 )
+        return -1;
+    else
+        return 0;
+}
+#endif

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/modules/builds/src/onie_tlvinfo.h

@@ -0,0 +1,150 @@
+/*
+ *  The Definition of the TlvInfo EEPROM format can be found at onie.org or
+ *  github.com/onie
+ */
+#include <linux/types.h>
+#define strtoul simple_strtoul
+
+#define FALSE   0
+#define TRUE    (!FALSE)
+#define MAX_STRING_SIZE	128
+/*
+ * Tlvinf header: Layout of the header for the TlvInfo format
+ *
+ * See the end of this file for details of this eeprom format
+ */
+struct __attribute__ ((__packed__)) tlvinfo_header_s {
+    char    signature[8];   /* 0x00 - 0x07 EEPROM Tag "TlvInfo" */
+    u_int8_t      version;  /* 0x08        Structure version */
+    u_int16_t     totallen; /* 0x09 - 0x0A Length of all data which follows */
+};
+typedef struct tlvinfo_header_s tlvinfo_header_t;
+
+// Header Field Constants
+#define TLV_INFO_ID_STRING      "TlvInfo"
+#define TLV_INFO_VERSION        0x01
+#define TLV_TOTAL_LEN_MAX       (SYS_EEPROM_SIZE - sizeof(tlvinfo_header_t))
+
+/*
+ * TlvInfo TLV: Layout of a TLV field
+ */
+struct __attribute__ ((__packed__)) tlvinfo_tlv_s {
+    u_int8_t  type;
+    u_int8_t  length;
+    u_int8_t  value[0];
+};
+typedef struct tlvinfo_tlv_s tlvinfo_tlv_t;
+
+/* Maximum length of a TLV value in bytes */
+#define TLV_VALUE_MAX_LEN        255
+
+/**
+ *  The TLV Types.
+ *
+ *  Keep these in sync with tlv_code_list in cmd_sys_eeprom.c
+ */
+#define TLV_CODE_PRODUCT_NAME   0x21
+#define TLV_CODE_PART_NUMBER    0x22
+#define TLV_CODE_SERIAL_NUMBER  0x23
+#define TLV_CODE_MAC_BASE       0x24
+#define TLV_CODE_MANUF_DATE     0x25
+#define TLV_CODE_DEVICE_VERSION 0x26
+#define TLV_CODE_LABEL_REVISION 0x27
+#define TLV_CODE_PLATFORM_NAME  0x28
+#define TLV_CODE_ONIE_VERSION   0x29
+#define TLV_CODE_MAC_SIZE       0x2A
+#define TLV_CODE_MANUF_NAME     0x2B
+#define TLV_CODE_MANUF_COUNTRY  0x2C
+#define TLV_CODE_VENDOR_NAME    0x2D
+#define TLV_CODE_DIAG_VERSION   0x2E
+#define TLV_CODE_SERVICE_TAG    0x2F
+#define TLV_CODE_VENDOR_EXT     0xFD
+#define TLV_CODE_CRC_32         0xFE
+
+/*
+ *  Struct for displaying the TLV codes and names.
+ */
+struct tlv_code_desc {
+    u_int8_t m_code;
+    char* m_name;
+};
+
+/*
+ *  List of TLV codes and names.
+ */
+static const struct tlv_code_desc tlv_code_list[] = {
+    { TLV_CODE_PRODUCT_NAME	 , "Product Name"},
+    { TLV_CODE_PART_NUMBER	 , "Part Number"},
+    { TLV_CODE_SERIAL_NUMBER     , "Serial Number"},
+    { TLV_CODE_MAC_BASE	         , "Base MAC Address"},
+    { TLV_CODE_MANUF_DATE	 , "Manufacture Date"},
+    { TLV_CODE_DEVICE_VERSION    , "Device Version"},
+    { TLV_CODE_LABEL_REVISION    , "Label Revision"},
+    { TLV_CODE_PLATFORM_NAME     , "Platform Name"},
+    { TLV_CODE_ONIE_VERSION	 , "Loader Version"},
+    { TLV_CODE_MAC_SIZE	         , "MAC Addresses"},
+    { TLV_CODE_MANUF_NAME	 , "Manufacturer"},
+    { TLV_CODE_MANUF_COUNTRY     , "Country Code"},
+    { TLV_CODE_VENDOR_NAME	 , "Vendor Name"},
+    { TLV_CODE_DIAG_VERSION	 , "Diag Version"},
+    { TLV_CODE_SERVICE_TAG       , "Service Tag"},
+    { TLV_CODE_VENDOR_EXT	 , "Vendor Extension"},
+    { TLV_CODE_CRC_32	         , "CRC-32"},
+};
+
+static inline const char* tlv_type2name(u_int8_t type)
+{
+    char* name = "Unknown";
+    int   i;
+
+    for (i = 0; i < sizeof(tlv_code_list)/sizeof(tlv_code_list[0]); i++) {
+	if (tlv_code_list[i].m_code == type) {
+	    name = tlv_code_list[i].m_name;
+	    break;
+	}
+    }
+    return name;
+}
+
+/*
+ * The max decode value is currently for the 'raw' type or the 'vendor
+ * extension' type, both of which have the same decode format.  The
+ * max decode string size is computed as follows:
+ *
+ *   strlen(" 0xFF") * TLV_VALUE_MAX_LEN + 1
+ *
+ */
+#define TLV_DECODE_VALUE_MAX_LEN    ((5 * TLV_VALUE_MAX_LEN) + 1)
+
+
+/*
+ * Each platform must define the following platform-specific macros
+ * in sys_eeprom_platform.h:
+ * SYS_EEPROM_SIZE: size of usable eeprom
+ * SYS_EEPROM_I2C_DEVICE: i2c-bus
+ * SYS_EEPROM_I2C_ADDR: address on the bus
+ * The following may also be defined in sys_eeprom_platform.h, else
+ * the defaults with take over:
+ * SYS_EEPROM_MAX_SIZE: Total size of the eeprom
+ * SYS_EEPROM_OFFSET: offset from where the ONIE header starts
+ */
+#define SYS_EEPROM_MAX_SIZE   2048
+#define SYS_EEPROM_OFFSET     0
+#define SYS_EEPROM_SIZE       SYS_EEPROM_MAX_SIZE
+#define SYS_EEPROM_I2C_DEVICE "/dev/i2c-0"
+#define SYS_EEPROM_I2C_ADDR   0x53
+
+#if (SYS_EEPROM_SIZE + SYS_EEPROM_OFFSET > SYS_EEPROM_MAX_SIZE)
+  #error SYS_EEPROM_SIZE + SYS_EEPROM_OFFSET is greater than SYS_EEPROM_MAX_SIZE
+#endif
+
+// Access functions to onie_tlvinfo
+void show_eeprom(u_int8_t *eeprom);
+int read_eeprom(struct i2c_client *pi2c_client, u_int8_t *eeprom);
+int prog_eeprom(struct i2c_client *pi2c_client,u_int8_t * eeprom);
+void update_eeprom_header(u_int8_t *eeprom);
+bool tlvinfo_find_tlv(u_int8_t *eeprom, u_int8_t tcode, int *eeprom_index);
+bool tlvinfo_delete_tlv(u_int8_t * eeprom, u_int8_t code);
+bool tlvinfo_add_tlv(u_int8_t * eeprom, int tcode, char * strval);
+bool tlvinfo_decode_tlv(u_int8_t *eeprom, u_int8_t tcode, char* value);
+//int  find_vpd_data(u_int8_t *eeprom, int i_offset, char *c_buf);

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/modules/builds/src/transceiver.h

@@ -0,0 +1,795 @@
+#ifndef TRANSCEIVER_H
+#define TRANSCEIVER_H
+
+#include <linux/types.h>
+
+/* advanced features control */
+#define TRANSVR_INFO_DUMP_ENABLE        (1)
+#define TRANSVR_INFO_CACHE_ENABLE       (1)
+#define TRANSVR_UEVENT_ENABLE           (1)
+
+/* Transceiver type define */
+#define TRANSVR_TYPE_UNKNOW_1           (0x00)
+#define TRANSVR_TYPE_UNKNOW_2           (0xff)
+#define TRANSVR_TYPE_SFP                (0x03)  /* Define for SFP, SFP+, SFP28 */
+#define TRANSVR_TYPE_QSFP               (0x0c)
+#define TRANSVR_TYPE_QSFP_PLUS          (0x0d)
+#define TRANSVR_TYPE_QSFP_28            (0x11)
+#define TRANSVR_TYPE_UNPLUGGED          (0xfa)  /* Define for ERROR handle */
+#define TRANSVR_TYPE_FAKE               (0xfc)  /* Define for ERROR handle */
+#define TRANSVR_TYPE_INCONSISTENT       (0xfd)  /* Define for ERROR handle */
+#define TRANSVR_TYPE_ERROR              (0xfe)  /* Define for ERROR handle */
+
+/* Transceiver class for base info */
+#define TRANSVR_CLASS_UNSPECIFIED       (0)
+#define TRANSVR_CLASS_ERROR             (-26001)
+#define TRANSVR_CLASS_1G                (26001)
+#define TRANSVR_CLASS_10G               (26011)
+#define TRANSVR_CLASS_25G               (26021)
+#define TRANSVR_CLASS_40G               (26041)
+#define TRANSVR_CLASS_100G              (26101)
+#define TRANSVR_CLASS_NO_SPERARABLE     (26901)
+#define TRANSVR_CLASS_EXTEND_COMP       (26902)
+/* Transceiver class for Optical 1G */
+#define TRANSVR_CLASS_OPTICAL           (27000)
+#define TRANSVR_CLASS_OPTICAL_100       (27001)
+#define TRANSVR_CLASS_OPTICAL_1G        (27002)
+#define TRANSVR_CLASS_OPTICAL_1G_AOC    (27003)
+#define TRANSVR_CLASS_OPTICAL_1G_SX     (27004)
+#define TRANSVR_CLASS_OPTICAL_1G_LX     (27005)
+#define TRANSVR_CLASS_OPTICAL_1G_EX     (27006)
+/* Transceiver class for Optical 10G */
+#define TRANSVR_CLASS_OPTICAL_10G       (27010)
+#define TRANSVR_CLASS_OPTICAL_10G_S_AOC (27011)
+#define TRANSVR_CLASS_OPTICAL_10G_S_SR  (27012)
+#define TRANSVR_CLASS_OPTICAL_10G_S_LR  (27013)
+#define TRANSVR_CLASS_OPTICAL_10G_S_ER  (27014)
+#define TRANSVR_CLASS_OPTICAL_10G_Q_AOC (27015)
+#define TRANSVR_CLASS_OPTICAL_10G_Q_SR  (27016)
+#define TRANSVR_CLASS_OPTICAL_10G_Q_LR  (27017)
+#define TRANSVR_CLASS_OPTICAL_10G_Q_ER  (27018)
+/* Transceiver class for Optical 25G */
+#define TRANSVR_CLASS_OPTICAL_25G       (27020)
+#define TRANSVR_CLASS_OPTICAL_25G_AOC   (27021)
+#define TRANSVR_CLASS_OPTICAL_25G_SR    (27022)
+#define TRANSVR_CLASS_OPTICAL_25G_LR    (27023)
+#define TRANSVR_CLASS_OPTICAL_25G_ER    (27024)
+/* Transceiver class for Optical 40G */
+#define TRANSVR_CLASS_OPTICAL_40G       (27040)
+#define TRANSVR_CLASS_OPTICAL_40G_AOC   (27041)
+#define TRANSVR_CLASS_OPTICAL_40G_SR4   (27042)
+#define TRANSVR_CLASS_OPTICAL_40G_LR4   (27043)
+#define TRANSVR_CLASS_OPTICAL_40G_ER4   (27044)
+/* Transceiver class for Optical 100G */
+#define TRANSVR_CLASS_OPTICAL_100G      (27100)
+#define TRANSVR_CLASS_OPTICAL_100G_AOC  (27101)
+#define TRANSVR_CLASS_OPTICAL_100G_SR4  (27102)
+#define TRANSVR_CLASS_OPTICAL_100G_LR4  (27103)
+#define TRANSVR_CLASS_OPTICAL_100G_ER4  (27104)
+#define TRANSVR_CLASS_OPTICAL_100G_PSM4 (27105)
+/* Transceiver class for Copper */
+#define TRANSVR_CLASS_COPPER            (28000)
+#define TRANSVR_CLASS_COPPER_L1_1G      (28001)
+#define TRANSVR_CLASS_COPPER_L1_10G     (28011)
+#define TRANSVR_CLASS_COPPER_L4_10G     (28012)
+#define TRANSVR_CLASS_COPPER_L1_25G     (28021)
+#define TRANSVR_CLASS_COPPER_L4_40G     (28041)
+#define TRANSVR_CLASS_COPPER_L4_100G    (28101)
+/* Transceiver class for Base-T */
+#define TRANSVR_CLASS_BASE_T_1000       (29001)
+#define TRANSVR_CLASS_BASE_T_1000_up    (29002)
+/* For uevent message */
+#define TRANSVR_UEVENT_KEY_IF           "IF_TYPE"
+#define TRANSVR_UEVENT_KEY_SP           "IF_SPEED"
+#define TRANSVR_UEVENT_KEY_LANE         "IF_LANE"
+#define TRANSVR_UEVENT_UNKNOW           "UNKNOW"
+#define TRANSVR_IF_KR                   "KR"
+#define TRANSVR_IF_KR4                  "KR4"
+#define TRANSVR_IF_SR                   "SR"
+#define TRANSVR_IF_SR4                  "SR4"
+#define TRANSVR_IF_SFI                  "SFI"
+#define TRANSVR_IF_IF_GMII              "GMII"
+#define TRANSVR_IF_IF_XGMII             "XGMII"
+#define TRANSVR_IF_SP_100               "100"
+#define TRANSVR_IF_SP_1G                "1000"
+#define TRANSVR_IF_SP_10G               "10000"
+#define TRANSVR_IF_SP_25G               "25000"
+#define TRANSVR_IF_SP_40G               "40000"
+#define TRANSVR_IF_SP_100G              "100000"
+
+/* Transceiver mode define */
+#define TRANSVR_MODE_DIRECT             (21000)
+#define TRANSVR_MODE_POLLING            (21001)
+
+/* Transceiver state define
+ * [Note]
+ *  1. State is used to represent the state of "Transceiver" and "Object".
+ *  2. State for different target has different means. The description as following:
+ */
+#define STATE_TRANSVR_CONNECTED         (0)    /* [Transvr]:Be plugged in.  [Obj]:Link up,   and work normally.       */
+#define STATE_TRANSVR_NEW               (-100) /* [Transvr]:(Not used)      [Obj]:Create                              */
+#define STATE_TRANSVR_INIT              (-101) /* [Transvr]:Be plugged in.  [Obj]:Link up,   and in initial process.  */
+#define STATE_TRANSVR_ISOLATED          (-102) /* [Transvr]:Be plugged in.  [Obj]:Isolate,   and not provide service. */
+#define STATE_TRANSVR_SWAPPED           (-200) /* [Transvr]:Be plugged in.  [Obj]:(Not used)                          */
+#define STATE_TRANSVR_DISCONNECTED      (-300) /* [Transvr]:Un-plugged.     [Obj]:Link down, and not provide service. */
+#define STATE_TRANSVR_UNEXCEPTED        (-901) /* [Transvr]:Any             [Obj]:Any,       and not in expect case.  */
+
+/* Task state define */
+#define STATE_T_TASK_WAIT               (110)
+#define STATE_T_TASK_DONE               (0)
+#define STATE_T_TASK_INIT               (-110)
+#define STATE_T_TASK_FAIL               (-410)
+
+
+/* Event for task handling */
+#define EVENT_TRANSVR_TASK_WAIT         (2101)
+#define EVENT_TRANSVR_TASK_DONE         (0)
+#define EVENT_TRANSVR_TASK_FAIL         (-2101)
+/* Event for initial handling */
+#define EVENT_TRANSVR_INIT_UP           (2201)
+#define EVENT_TRANSVR_INIT_DOWN         (1)
+#define EVENT_TRANSVR_INIT_REINIT       (-2201)
+#define EVENT_TRANSVR_INIT_FAIL         (-2202)
+/* Event for others */
+#define EVENT_TRANSVR_RELOAD_FAIL       (-2301)
+#define EVENT_TRANSVR_EXCEP_INIT        (-2401)
+#define EVENT_TRANSVR_EXCEP_UP          (-2402)
+#define EVENT_TRANSVR_EXCEP_DOWN        (-2403)
+#define EVENT_TRANSVR_EXCEP_SWAP        (-2404)
+#define EVENT_TRANSVR_EXCEP_EXCEP       (-2405)
+#define EVENT_TRANSVR_EXCEP_ISOLATED    (-2406)
+#define EVENT_TRANSVR_I2C_CRASH         (-2501)
+
+/* Transceiver error code define */
+#define ERR_TRANSVR_UNINIT              (-201)
+#define ERR_TRANSVR_UNPLUGGED           (-202)
+#define ERR_TRANSVR_ABNORMAL            (-203)
+#define ERR_TRANSVR_NOSTATE             (-204)
+#define ERR_TRANSVR_NOTSUPPORT          (-205)
+#define ERR_TRANSVR_BADINPUT            (-206)
+#define ERR_TRANSVR_UPDATE_FAIL         (-207)
+#define ERR_TRANSVR_RELOAD_FAIL         (-208)
+#define ERR_TRANSVR_INIT_FAIL           (-209)
+#define ERR_TRANSVR_UNDEFINED           (-210)
+#define ERR_TRANSVR_TASK_FAIL           (-211)
+#define ERR_TRANSVR_TASK_BUSY           (-212)
+#define ERR_TRANSVR_UEVENT_FAIL         (-213)
+#define ERR_TRANSVR_FUNC_DISABLE        (-214)
+#define ERR_TRANSVR_I2C_CRASH           (-297)
+#define ERR_TRNASVR_BE_ISOLATED         (-298)
+#define ERR_TRANSVR_UNEXCPT             (-299)
+
+/* For debug */
+#define DEBUG_TRANSVR_INT_VAL           (-99)
+#define DEBUG_TRANSVR_HEX_VAL           (0xfe)
+#define DEBUG_TRANSVR_STR_VAL           "ERROR"
+
+/* For system internal */
+#define VAL_TRANSVR_COMID_ARREESS       (0x50)
+#define VAL_TRANSVR_COMID_OFFSET        (0x00)
+#define VAL_TRANSVR_8472_READY_ADDR     (0x51)
+#define VAL_TRANSVR_8472_READY_PAGE     (-1)
+#define VAL_TRANSVR_8472_READY_OFFSET   (110)
+#define VAL_TRANSVR_8472_READY_BIT      (0)
+#define VAL_TRANSVR_8472_READY_VALUE    (0)
+#define VAL_TRANSVR_8472_READY_ABNORMAL (0xff)
+#define VAL_TRANSVR_8436_READY_ADDR     (0x50)
+#define VAL_TRANSVR_8436_READY_PAGE     (-1)
+#define VAL_TRANSVR_8436_READY_OFFSET   (2)
+#define VAL_TRANSVR_8436_READY_BIT      (0)
+#define VAL_TRANSVR_8436_READY_VALUE    (0)
+#define VAL_TRANSVR_8436_READY_ABNORMAL (0xff)
+#define VAL_TRANSVR_8436_PWD_ADDR       (0x50)
+#define VAL_TRANSVR_8436_PWD_PAGE       (-1)
+#define VAL_TRANSVR_8436_PWD_OFFSET     (123)
+#define VAL_TRANSVR_PAGE_FREE           (-99)
+#define VAL_TRANSVR_PAGE_SELECT_OFFSET  (127)
+#define VAL_TRANSVR_PAGE_SELECT_DELAY   (5)
+#define VAL_TRANSVR_TASK_RETRY_FOREVER  (-999)
+#define VAL_TRANSVR_FUNCTION_DISABLE    (-1)
+#define STR_TRANSVR_SFP                 "SFP"
+#define STR_TRANSVR_QSFP                "QSFP"
+#define STR_TRANSVR_QSFP_PLUS           "QSFP+"
+#define STR_TRANSVR_QSFP28              "QSFP28"
+
+/* For transvr buf len */
+#define LEN_TRANSVR_S_STR               (16)
+#define LEN_TRANSVR_M_STR               (32)
+#define LEN_TRANSVR_L_STR               (64)
+
+/* Optical wavelength */
+#define VAL_OPTICAL_WAVELENGTH_SR       (850)
+#define VAL_OPTICAL_WAVELENGTH_LR       (1310)
+#define VAL_OPTICAL_WAVELENGTH_ER       (1550)
+
+/* BCM chip type define */
+#define BCM_CHIP_TYPE_TRIDENT_2         (31001)  /* Magnolia, Hudson32i, Spruce */
+#define BCM_CHIP_TYPE_TOMAHAWK          (31002)  /* Redwood, Cypress */
+
+/* Lavender chip type define */
+#define CHIP_TYPE_D5264Q28B             (31003)  /* Lavender */
+
+/* Info from transceiver EEPROM */
+struct eeprom_map_s {
+    int addr_br;           int page_br;           int offset_br;           int length_br;
+    int addr_cdr;          int page_cdr;          int offset_cdr;          int length_cdr;
+    int addr_comp_rev;     int page_comp_rev;     int offset_comp_rev;     int length_comp_rev;
+    int addr_connector;    int page_connector;    int offset_connector;    int length_connector;
+    int addr_diag_type;    int page_diag_type;    int offset_diag_type;    int length_diag_type;
+    int addr_extbr;        int page_extbr;        int offset_extbr;        int length_extbr;
+    int addr_ext_id;       int page_ext_id;       int offset_ext_id;       int length_ext_id;
+    int addr_id;           int page_id;           int offset_id;           int length_id;
+    int addr_len_sm;       int page_len_sm;       int offset_len_sm;       int length_len_sm;
+    int addr_len_smf;      int page_len_smf;      int offset_len_smf;      int length_len_smf;
+    int addr_len_om1;      int page_len_om1;      int offset_len_om1;      int length_len_om1;
+    int addr_len_om2;      int page_len_om2;      int offset_len_om2;      int length_len_om2;
+    int addr_len_om3;      int page_len_om3;      int offset_len_om3;      int length_len_om3;
+    int addr_len_om4;      int page_len_om4;      int offset_len_om4;      int length_len_om4;
+    int addr_option;       int page_option;       int offset_option;       int length_option;
+    int addr_rate_id;      int page_rate_id;      int offset_rate_id;      int length_rate_id;
+    int addr_rx_am;        int page_rx_am;        int offset_rx_am;        int length_rx_am;
+    int addr_rx_em;        int page_rx_em;        int offset_rx_em;        int length_rx_em;
+    int addr_rx_los;       int page_rx_los;       int offset_rx_los;       int length_rx_los;
+    int addr_rx_power;     int page_rx_power;     int offset_rx_power;     int length_rx_power;
+    int addr_soft_rs0;     int page_soft_rs0;     int offset_soft_rs0;     int length_soft_rs0;
+    int addr_soft_rs1;     int page_soft_rs1;     int offset_soft_rs1;     int length_soft_rs1;
+    int addr_temp;         int page_temp;         int offset_temp;         int length_temp;
+    int addr_trancomp;     int page_trancomp;     int offset_trancomp;     int length_trancomp;
+    int addr_trancomp_ext; int page_trancomp_ext; int offset_trancomp_ext; int length_trancomp_ext;
+    int addr_tx_bias;      int page_tx_bias;      int offset_tx_bias;      int length_tx_bias;
+    int addr_tx_disable;   int page_tx_disable;   int offset_tx_disable;   int length_tx_disable;
+    int addr_tx_eq;        int page_tx_eq;        int offset_tx_eq;        int length_tx_eq;
+    int addr_tx_fault;     int page_tx_fault;     int offset_tx_fault;     int length_tx_fault;
+    int addr_tx_power;     int page_tx_power;     int offset_tx_power;     int length_tx_power;
+    int addr_vendor_name;  int page_vendor_name;  int offset_vendor_name;  int length_vendor_name;
+    int addr_vendor_pn;    int page_vendor_pn;    int offset_vendor_pn;    int length_vendor_pn;
+    int addr_vendor_rev;   int page_vendor_rev;   int offset_vendor_rev;   int length_vendor_rev;
+    int addr_vendor_sn;    int page_vendor_sn;    int offset_vendor_sn;    int length_vendor_sn;
+    int addr_voltage;      int page_voltage;      int offset_voltage;      int length_voltage;
+    int addr_wavelength;   int page_wavelength;   int offset_wavelength;   int length_wavelength;
+};
+
+
+struct transvr_worker_s;
+
+/* Class of transceiver object */
+struct transvr_obj_s {
+
+    /* ========== Object private property ==========
+     * [Prop]: id
+     * [Desc]: Type of serial transceiver.
+     * [Note]: SFP:03h / QSFP:0Ch / QSPF+:0Dh /QSFP28:11h
+     */
+    uint8_t id;
+
+    /* [Prop]: connector
+     * [Desc]: Connector type.
+     * [Note]: SFP : A0h / 2
+     *         QSFP: 00h / 130
+     */
+    uint8_t connector;
+
+    /* [Prop]: transvr_comp
+     * [Desc]: Transceiver compliance code.
+     * [Note]: SFP: SFF-8472
+     *         - Normal  : A0h / offset 3-10
+     *         - Extended: A0h / offset 36
+     *         QSFP: SFF-8436 & SFF-8636
+     *         - Normal  : 00h / offset 131-138
+     *         - Extended: 00h / offset 192
+     */
+    uint8_t transvr_comp[8];
+    uint8_t transvr_comp_ext;
+
+    /* [Prop]: vendor_name
+     * [Desc]: SFP vendor name (ASCII 16 byte char).
+     * [Note]: ex:FINISAR CORP.
+     */
+    char *vendor_name;
+
+    /* [Prop]: vendor_pn
+     * [Desc]: Part number provided by SFP vendor (ASCII 16 byte char).
+     * [Note]:
+     */
+    char *vendor_pn;
+
+    /* [Prop]: vendor_rev
+     * [Desc]: Revision level for part number provided by vendor (ASCII 4 byte char).
+     * [Note]:
+     */
+    char *vendor_rev;
+
+    /* [Prop]: vendor_sn
+     * [Desc]: Serial number provided by vendor (ASCII 16 byte char).
+     * [Note]:
+     */
+    char *vendor_sn;
+
+    /* [Prop]: Extended identifier
+     * [Desc]: SFP:
+     *         => None
+     *
+     *         QSFP:
+     *         => This byte contained two information:
+     *         (1) Power consumption class
+     *         (2) CDR function present
+     * [Note]: Bit description as below:
+     *         [SFP]
+     *           None
+     *
+     *         [QSFP]
+     *         (1) Power consumption class:
+     *             Class 1: 1.5W (Bit6-7 = 00:)
+     *             Class 2: 2.0W (Bit6-7 = 01:)
+     *             Class 3: 2.5W (Bit6-7 = 10:)
+     *             Class 4: 3.5W (Bit6-7 = 11:)
+     *             Class 5: 4.0W (Bit0-1 = 01:)
+     *             Class 6: 4.5W (Bit0-1 = 10:)
+     *             Class 7: 5.0W (Bit0-1 = 11:)
+     *         (2) CDR function present:
+     *             Bit2: 0 = No CDR in RX
+     *                   1 = CDR present in RX
+     *             Bit3: 0 = No CDR in TX
+     *                   1 = CDR present in TX
+     */
+    uint8_t ext_id;
+
+    /* [Prop]: br
+     * [Desc]: Nominal bit rate, units of 100 MBits/sec.
+     * [Note]: SFP:03h / QSFP:0Ch / QSPF+:0Dh
+     *         has val: 0x67
+     *         no val :
+     */
+    uint8_t br;
+
+    /* [Prop]: extbr
+     * [Desc]: Extended br (00h/222)
+     * [Desc]: Nominal bit rate per channel, units of 250 Mbps.
+     *         Complements. Byte 140. See Table 32A.
+     */
+    uint8_t extbr;
+
+    /* [Prop]: len_sm
+     * [Desc]: Length (single mode)-(100's)m
+     * [Note]: This value specifies the link length that is supported by the transceiver
+     *         while operating in compliance with the applicable standards using single mode
+     *         fiber. The value is in units of 100 meters. A value of 255 means that the
+     *         transceiver supports a link length greater than 25.4 km. A value of zero means
+     *         that the transceiver does not support single mode fiber or that the length
+     *         information must be determined from the transceiver technology.
+     */
+    int len_sm;
+
+    /* [Prop]: len_smf
+     * [Desc]: Length (single mode)-km
+     * [Note]: Addition to EEPROM data from original GBIC definition. This value specifies
+     *         the link length that is supported by the transceiver while operating in
+     *         compliance with the applicable standards using single mode fiber. The value
+     *         is in units of kilometers. A value of 255 means that the transceiver supports
+     *         a link length greater than 254 km. A value of zero means that the transceiver
+     *         does not support single mode fiber or that the length information must be
+     *         determined from the transceiver technology.
+     */
+    int len_smf;
+
+    /* [Prop]: len_om1
+     * [Desc]: Link length supported for 62.5 um OM1 fiber, units of 10 m
+     * [Note]: The value is in units of 10 meters. A value of 255 means that the
+     *         transceiver supports a link length greater than 2.54 km. A value of
+     *         zero means that the transceiver does not support 50 micron multi-mode
+     *         fiber or that the length information must be determined from the transceiver
+     *         technology.
+     */
+    int len_om1;
+
+    /* [Prop]: len_om2
+     * [Desc]: Link length supported for 50 um OM2 fiber, units of 10 m
+     * [Note]: The value is in units of 10 meters. A value of 255 means that the
+     *         transceiver supports a link length greater than 2.54 km. A value of
+     *         zero means that the transceiver does not support 50 micron multi-mode
+     *         fiber or that the length information must be determined from the transceiver
+     *         technology.
+     */
+    int len_om2;
+
+    /* [Prop]: len_om3
+     * [Desc]: Length (50um, OM3)
+     * [Note]: This value specifies link length that is supported by the transceiver while
+     *         operating in compliance with applicable standards using 50 micron multimode
+     *         OM3 [2000 MHz*km] fiber. The value is in units of 10 meters. A value of 255
+     *         means that the transceiver supports a link length greater than 2.54 km. A value
+     *         of zero means that the transceiver does not support 50 micron multimode fiber
+     *         or that the length information must be determined from the transceiver technology.
+     */
+    int len_om3;
+
+    /* [Prop]: len_om4
+     * [Desc]: Length (50um, OM4) and Length (Active Cable or Copper)
+     * [Note]: For optical links, this value specifies link length that is supported by the
+     *         transceiver while operating in compliance with applicable standards using 50 micron
+     *         multimode OM4 [4700 MHz*km] fiber. The value is in units of 10 meters. A value of
+     *         255 means that the transceiver supports a link length greater than 2.54 km. A value
+     *         of zero means that the transceiver does not support 50 micron multimode fiber or that
+     *         the length information must be determined from the transceiver codes specified in Table 5-3.
+     *
+     *         For copper links, this value specifies minimum link length supported by the transceiver
+     *         while operating in compliance with applicable standards using copper cable. For active
+     *         cable, this value represents actual length. The value is in units of 1 meter. A value of 255
+     *         means the transceiver supports a link length greater than 254 meters. A value of zero means
+     *         the transceiver does not support copper or active cables or the length information must be
+     *         determined from transceiver technology. Further information about cable design, equalization,
+     *         and connectors is usually required to guarantee meeting a particular length requirement.
+     */
+    int len_om4;
+
+    /* [Prop]: comp_rev
+     * [Desc]: SFF spec revision compliance
+     * [Note]: Indicates which revision of SFF SFF-8472 (SFP) / SFF-8636 (QSFP) the transceiver
+     *         complies with. (unsigned integer)
+     */
+    uint8_t comp_rev;
+
+    /* [Prop]: CDR
+     * [Desc]: For transceivers with CDR capability, setting the CDR to ON engages the internal
+     *         retiming function. Setting the CDR to OFF enables an internal bypassing mode ,which
+     *         directs traffic around the internal CDR. (Reference: SFF-8636)
+     * [Note]: value=0xff: ON.
+     *         value=0x00: OFF.
+     */
+    uint8_t cdr;
+
+    /* [Prop]: rate_id
+     * [Desc]: Soft Rate Select 0(RX).
+     * [Note]: 1. Addr: A0h / Offset: 13
+     *         2. Value description:
+     *            00h  Unspecified
+     *            01h  SFF-8079 (4/2/1G Rate_Select & AS0/AS1)
+     *            02h  SFF-8431 (8/4/2G Rx Rate_Select only)
+     *            03h  Unspecified *
+     *            04h  SFF-8431 (8/4/2G Tx Rate_Select only)
+     *            05h  Unspecified *
+     *            06h  SFF-8431 (8/4/2G Independent Rx & Tx Rate_select)
+     *            07h  Unspecified *
+     *            08h  FC-PI-5 (16/8/4G Rx Rate_select only) High=16G only, Low=8G/4G
+     *            09h  Unspecified *
+     *            0Ah  FC-PI-5 (16/8/4G Independent Rx, Tx Rate_select) High=16G only,
+     *                 Low=8G/4G
+     *            0Bh  Unspecified *
+     *            0Ch  FC-PI-6 (32/16/8G Independent Rx, Tx Rate_Select)
+     *                 High=32G only, Low = 16G/8G
+     *            0Dh  Unspecified *
+     *            0Eh  10/8G Rx and Tx Rate_Select controlling the operation or locking
+     *                 modes of the internal signal conditioner, retimer or CDR, according
+     *                 to the logic table defined in Table 10-2, High Bit Rate
+     *                 (10G) =9.95-11.3 Gb/s; Low Bit Rate (8G) = 8.5 Gb/s. In this mode,
+     *                 the default value of bit 110.3 (Soft Rate Select RS(0), Table 9-11)
+     *                 and of bit 118.3 (Soft Rate Select RS(1), Table 10-1) is 1.
+     *            0Fh  Unspecified *
+     *            10h-FFh Unallocated
+     */
+    int rate_id;
+
+    /* [Prop]: soft_rs0
+     * [Desc]: Soft Rate Select 0(RX).
+     * [Note]: 1. Writing '1' selects full bandwidth operation.
+     *         2. This bit is "OR'd with the hard Rate_Select, AS(0) or RS(0) pin value.
+     *         3. Default at power up is logic zero/low
+     *         4. Addr: A2h / Offset: 110 / Bit: 3
+     */
+    uint8_t soft_rs0;
+
+    /* [Prop]: soft_rs1
+     * [Desc]: Soft Rate Select 1(TX).
+     * [Note]: 1. Writing '1' selects full bandwidth TX operation.
+     *         2. This bit is "OR'd with the hard Rate_Select, AS(1) or RS(1) pin value.
+     *         3. Default at power up is logic zero/low
+     *         4. Addr: A2h / Offset: 118 / Bit: 3
+     */
+    uint8_t soft_rs1;
+
+    /* [Prop]: diag_type
+     * [Desc]: DIAGNOSTIC MONITORING TYPE (A0h/92)
+     * [Note]: Description in SFF-8472 as below:
+     *         Bit7: Reserved for legacy diagnostic implementations. Must be '0' for compliance
+     *               with this document.
+     *         Bit6: Digital diagnostic monitoring implemented (described in this document).
+     *               Must be '1' for compliance with this document.
+     *         Bit5 Internally calibrated
+     *         Bit4 Externally calibrated
+     *         Bit3 Received power measurement type.0 = OMA, 1 = average power
+     *         Bit2 Address change required see section above, "addressing modes"
+     *         Bit1-0 Unallocated
+     */
+    uint8_t diag_type;
+
+    /* [Prop]: curr_temp
+     * [Desc]: Transceiver Current Temperature (A2h/96-97)
+     * [Note]: 1. Dependent on diag_type.
+     *         2. 96: High byte
+     *         3. 97: Low byte
+     *         4. This feature only for SFP
+     */
+    uint8_t curr_temp[2];
+
+    /* [Prop]: curr_vol
+     * [Desc]: Transceiver Current Voltage (SFP:A2h/108-109; QSFP:00h/22-23)
+     * [Note]: 1. Dependent on diag_type.
+     *         2. 98: High byte
+     *         3. 99: Low byte
+     *         4. This feature only for SFP
+     *         5. Internally measured transceiver supply voltage. Represented
+     *            as a 16 bit unsigned integer with the voltage defined as the
+     *            full 16 bit value (0-65535) with LSB equal to 100 uVolt,
+     *            yielding a total range of 0 to +6.55 Volts
+     */
+    uint8_t curr_voltage[2];
+
+    /* [Prop]: curr_tx_bias
+     * [Desc]: Transceiver TX Bias Current (SFP:A2h/100-101; QSFP:00h/26-27)
+     * [Note]: 1. Dependent on diag_type.
+     *         2. 100: High byte
+     *         3. 101: Low byte
+     *         4. This feature only for SFP
+     *         5. Measured TX bias current in uA. Represented as a 16 bit unsigned
+     *            integer with the current defined as the full 16 bit value (0-65535)
+     *            with LSB equal to 2 uA, yielding a total range of 0 to 131 mA.
+     *            Accuracy is vendor specific but must be better than 10% of the
+     *            manufacturer's nominal value over specified operating temperature
+     *            and voltage.
+     */
+    uint8_t curr_tx_bias[8];
+
+    /* [Prop]: curr_tx_power
+     * [Desc]: Transceiver TX Output Power (A2h/102-103)
+     * [Note]: 1. Dependent on diag_type.
+     *         2. 102: High byte
+     *         3. 103: Low byte
+     *         4. This feature only for SFP
+     *         5. Measured TX output power in mW. Represented as a 16 bit unsigned
+     *         integer with the power defined as the full 16 bit value (0-65535)
+     *         with LSB equal to 0.1 uW, yielding a total range of 0 to 6.5535 mW
+     *         (~ -40 to +8.2 dBm). Data is assumed to be based on measurement of
+     *         laser monitor photodiode current. It is factory calibrated to absolute
+     *         units using the most representative fiber output type. Accuracy is
+     *         vendor specific but must be better than 3dB over specified temperature
+     *          and voltage. Data is not valid when the transmitter is disabled.
+     */
+    uint8_t curr_tx_power[8];
+
+    /* [Prop]: curr_tx_power
+     * [Desc]: Transceiver TX Output Power (A2h/102-103)
+     * [Note]: 1. Dependent on diag_type.
+     *         2. 102: High byte
+     *         3. 103: Low byte
+     *         4. This feature only for SFP
+     *         5. Measured RX received optical power in mW. Value can represent either
+     *         average received power or OMA depending upon how bit 3 of byte 92 (A0h)
+     *         is set. Represented as a 16 bit unsigned integer with the power defined
+     *         as the full 16 bit value (0-65535) with LSB equal to 0.1 uW, yielding a
+     *         total range of 0 to 6.5535 mW (~ -40 to +8.2 dBm). Absolute accuracy is
+     *         dependent upon the exact optical wavelength. For the vendor specified
+     *         wavelength, accuracy shall be better than 3dB over specified temperature
+     *         and voltage.
+     */
+    uint8_t curr_rx_power[8];
+
+    /* [Prop]: wavelength
+     * [Desc]: Wavelength or Copper Cable Attenuation
+     * [Note]: (Following is info from SFF-8636)
+     *         For optical free side devices, this parameter identifies the nominal
+     *         transmitter output wavelength at room temperature. This parameter is a
+     *         16-bit hex value with Byte 186 as high order byte and Byte 187 as low
+     *         order byte. The laser wavelength is equal to the 16-bit integer value
+     *         divided by 20 in nm (units of 0.05 nm). This resolution should be adequate
+     *         to cover all relevant wavelengths yet provide enough resolution for all
+     *         expected DWDM applications. For accurate representation of controlled
+     *         wavelength applications, this value should represent the center of the
+     *         guaranteed wavelength range. If the free side device is identified as
+     *         copper cable these registers will be used to define the cable attenuation.
+     *         An indication of 0 dB attenuation refers to the case where the attenuation
+     *         is not known or is unavailable.
+     *         Byte 186 (00-FFh) is the copper cable attenuation at 2.5 GHz in units of 1 dB.
+     *         Byte 187 (00-FFh) is the copper cable attenuation at 5.0 GHz in units of 1 dB.
+     */
+    uint8_t wavelength[2];
+
+    /* [Prop]: Amplitude control
+     * [Desc]: Amplitude control
+     * [Note]: QSFP28  => SFF-8636 03H Byte-238/239
+     */
+    uint8_t rx_am[2];
+
+    /* [Prop]: Emphasis control
+     * [Desc]: Emphasis control
+     * [Note]: SFP+/28 => SFF-8472 A2H Byte-115
+     *         QSFP28  => SFF-8636 03H Byte-236/237
+     */
+    uint8_t rx_em[2];
+
+    /* [Prop]: Soft Rx LOS
+     * [Desc]: Soft Rx LOS which provide by transceiver
+     * [Note]: (Following is info from SFF-8636)
+     *         Byte 3:
+     *          - Bit 0: L-Rx1 LOS
+     *          - Bit 1: L-Rx2 LOS
+     *          - Bit 2: L-Rx3 LOS
+     *          - Bit 3: L-Rx4 LOS
+     */
+    uint8_t rx_los;
+
+    /* [Prop]: Soft Tx Disable
+     * [Desc]: Soft Tx Disable which provide by transceiver
+     * [Note]: (Following is info from SFF-8636)
+     *         Byte 86:
+     *          - Bit 0: Tx1 Disable
+     *          - Bit 1: Tx2 Disable
+     *          - Bit 2: Tx3 Disable
+     *          - Bit 3: Tx4 Disable
+     */
+    uint8_t tx_disable;
+
+    /* [Prop]: Soft Tx Fault
+     * [Desc]: Soft Tx Fault which provide by transceiver
+     * [Note]: (Following is info from SFF-8636)
+     *         Byte 86:
+     *          - Bit 0: Tx1 Fault
+     *          - Bit 1: Tx2 Fault
+     *          - Bit 2: Tx3 Fault
+     *          - Bit 3: Tx4 Fault
+     */
+    uint8_t tx_fault;
+
+    /* [Prop]: Transceiver EQUALIZATION
+     * [Desc]: Transceiver EQUALIZATION
+     * [Note]: SFP+/28 => SFF-8472 A2H Byte-114
+     *         QSFP28  => SFF-8636 03H Byte-234/235
+     */
+    uint8_t tx_eq[2];
+
+    /* [Prop]: OPTION VALUES
+     * [Desc]: The bits in the option field shall specify the options implemented in the transceiver.
+     * [Note]: SFP+/28  => SFF-8472 A0H Byte-64/65
+     *         QSFP+/28 => SFF-8636 00H Byte-193/195
+     */
+    uint8_t option[3];
+
+
+    /* ========== Object private property ==========
+     */
+    struct device       *transvr_dev_p;
+    struct eeprom_map_s *eeprom_map_p;
+    struct i2c_client   *i2c_client_p;
+    struct ioexp_obj_s  *ioexp_obj_p;
+    struct transvr_worker_s *worker_p;
+    struct mutex lock;
+    char swp_name[32];
+    int auto_config;
+    int auto_tx_disable;
+    int chan_id;
+    int chipset_type;
+    int curr_page;
+    int info;
+    int ioexp_virt_offset;
+    int lane_id[8];
+    int layout;
+    int mode;
+    int retry;
+    int state;
+    int temp;
+    int type;
+
+    /* ========== Object public functions ==========
+     */
+    int  (*get_id)(struct transvr_obj_s *self);
+    int  (*get_ext_id)(struct transvr_obj_s *self);
+    int  (*get_connector)(struct transvr_obj_s *self);
+    int  (*get_vendor_name)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_vendor_pn)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_vendor_rev)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_vendor_sn)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_power_cls)(struct transvr_obj_s *self);
+    int  (*get_br)(struct transvr_obj_s *self);
+    int  (*get_len_sm)(struct transvr_obj_s *self);
+    int  (*get_len_smf)(struct transvr_obj_s *self);
+    int  (*get_len_om1)(struct transvr_obj_s *self);
+    int  (*get_len_om2)(struct transvr_obj_s *self);
+    int  (*get_len_om3)(struct transvr_obj_s *self);
+    int  (*get_len_om4)(struct transvr_obj_s *self);
+    int  (*get_comp_rev)(struct transvr_obj_s *self);
+    int  (*get_comp_eth_1)(struct transvr_obj_s *self);
+    int  (*get_comp_eth_10)(struct transvr_obj_s *self);
+    int  (*get_comp_eth_10_40)(struct transvr_obj_s *self);
+    int  (*get_comp_extend)(struct transvr_obj_s *self);
+    int  (*get_cdr)(struct transvr_obj_s *self);
+    int  (*get_rate_id)(struct transvr_obj_s *self);
+    int  (*get_soft_rs0)(struct transvr_obj_s *self);
+    int  (*get_soft_rs1)(struct transvr_obj_s *self);
+    int  (*get_info)(struct transvr_obj_s *self);
+    int  (*get_if_type)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_if_speed)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_if_lane)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_curr_temp)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_curr_vol)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_soft_rx_los)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_soft_tx_disable)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_soft_tx_fault)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_auto_tx_disable)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_tx_bias)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_tx_power)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_rx_power)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_tx_eq)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_rx_am)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_rx_em)(struct transvr_obj_s *self, char *buf_p);
+    int  (*get_wavelength)(struct transvr_obj_s *self, char *buf_p);
+    int  (*set_cdr)(struct transvr_obj_s *self, int input_val);
+    int  (*set_soft_rs0)(struct transvr_obj_s *self, int input_val);
+    int  (*set_soft_rs1)(struct transvr_obj_s *self, int input_val);
+    int  (*set_soft_tx_disable)(struct transvr_obj_s *self, int input_val);
+    int  (*set_auto_tx_disable)(struct transvr_obj_s *self, int input_val);
+    int  (*set_tx_eq)(struct transvr_obj_s *self, int input_val);
+    int  (*set_rx_am)(struct transvr_obj_s *self, int input_val);
+    int  (*set_rx_em)(struct transvr_obj_s *self, int input_val);
+
+    /* ========== Object private functions ==========
+     */
+    int (*init)(struct transvr_obj_s *self);
+    int (*clean)(struct transvr_obj_s *self);
+    int (*check)(struct transvr_obj_s *self);
+    int (*update_all)(struct transvr_obj_s *self, int show_err);
+    int (*fsm_4_direct)(struct transvr_obj_s* self, char *caller_name);
+    int (*fsm_4_polling)(struct transvr_obj_s* self, char *caller_name);
+    int (*send_uevent)(struct transvr_obj_s* self, enum kobject_action u_action);
+    int (*dump_all)(struct transvr_obj_s* self);
+};
+
+
+/* For AVL Mapping */
+struct transvr_avl_s {
+    char vendor_name[32];
+    char vendor_pn[32];
+    int (*init)(struct transvr_obj_s *self);
+};
+
+
+/* Worker for long term task of transceiver */
+struct transvr_worker_s {
+    /* Task Parameter */
+    struct transvr_obj_s *transvr_p;
+    struct transvr_worker_s *next_p;
+    struct transvr_worker_s *pre_p;
+    unsigned long trigger_time;
+    char func_name[64];
+    int retry;
+    int state;
+
+    /* Task private data */
+    void *p_data;
+
+    /* Call back function */
+    int (*main_task)(struct transvr_worker_s *task);
+    int (*post_task)(struct transvr_worker_s *task);
+};
+
+
+struct transvr_obj_s *
+create_transvr_obj(char *swp_name,
+                   int chan_id,
+                   struct ioexp_obj_s *ioexp_obj_p,
+                   int ioexp_virt_offset,
+                   int transvr_type,
+                   int chipset_type,
+                   int run_mode);
+
+void lock_transvr_obj(struct transvr_obj_s *self);
+void unlock_transvr_obj(struct transvr_obj_s *self);
+int isolate_transvr_obj(struct transvr_obj_s *self);
+
+int resync_channel_tier_2(struct transvr_obj_s *self);
+
+void alarm_msg_2_user(struct transvr_obj_s *self, char *emsg);
+
+#endif /* TRANSCEIVER_H */
+
+
+
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/Makefile

@@ -0,0 +1 @@
+include $(ONL)/make/pkg.mk

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/PKG.yml

@@ -0,0 +1 @@
+!include $ONL_TEMPLATES/onlp-platform-any.yml PLATFORM=x86-64-inventec-d5264q28b ARCH=amd64 TOOLCHAIN=x86_64-linux-gnu

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/Makefile

@@ -0,0 +1,2 @@
+FILTER=src
+include $(ONL)/make/subdirs.mk

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/lib/Makefile

@@ -0,0 +1,45 @@
+############################################################
+# <bsn.cl fy=2014 v=onl>
+#
+#           Copyright 2014 BigSwitch Networks, Inc.
+#
+# Licensed under the Eclipse Public License, Version 1.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+#        http://www.eclipse.org/legal/epl-v10.html
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied. See the License for the specific
+# language governing permissions and limitations under the
+# License.
+#
+# </bsn.cl>
+############################################################
+#
+#
+############################################################
+include $(ONL)/make/config.amd64.mk
+
+MODULE := libonlp-x86-64-inventec-d5264q28b
+include $(BUILDER)/standardinit.mk
+
+DEPENDMODULES := AIM IOF x86_64_inventec_d5264q28b onlplib
+DEPENDMODULE_HEADERS := sff
+
+include $(BUILDER)/dependmodules.mk
+
+SHAREDLIB := libonlp-x86-64-inventec-d5264q28b.so
+$(SHAREDLIB)_TARGETS := $(ALL_TARGETS)
+include $(BUILDER)/so.mk
+.DEFAULT_GOAL := $(SHAREDLIB)
+
+GLOBAL_CFLAGS += -I$(onlp_BASEDIR)/module/inc
+GLOBAL_CFLAGS += -DAIM_CONFIG_INCLUDE_MODULES_INIT=1
+GLOBAL_CFLAGS += -fPIC
+GLOBAL_LINK_LIBS += -lpthread
+
+include $(BUILDER)/targets.mk
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/onlpdump/Makefile

@@ -0,0 +1,46 @@
+############################################################
+# <bsn.cl fy=2014 v=onl>
+#
+#           Copyright 2014 BigSwitch Networks, Inc.
+#
+# Licensed under the Eclipse Public License, Version 1.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+#        http://www.eclipse.org/legal/epl-v10.html
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied. See the License for the specific
+# language governing permissions and limitations under the
+# License.
+#
+# </bsn.cl>
+############################################################
+#
+#
+#
+############################################################
+include $(ONL)/make/config.amd64.mk
+
+.DEFAULT_GOAL := onlpdump
+
+MODULE := onlpdump
+include $(BUILDER)/standardinit.mk
+
+DEPENDMODULES := AIM IOF onlp x86_64_inventec_d5264q28b onlplib onlp_platform_defaults sff cjson cjson_util timer_wheel OS
+
+include $(BUILDER)/dependmodules.mk
+
+BINARY := onlpdump
+$(BINARY)_LIBRARIES := $(LIBRARY_TARGETS)
+include $(BUILDER)/bin.mk
+
+GLOBAL_CFLAGS += -DAIM_CONFIG_AIM_MAIN_FUNCTION=onlpdump_main
+GLOBAL_CFLAGS += -DAIM_CONFIG_INCLUDE_MODULES_INIT=1
+GLOBAL_CFLAGS += -DAIM_CONFIG_INCLUDE_MAIN=1
+GLOBAL_LINK_LIBS += -lpthread -lm
+
+include $(BUILDER)/targets.mk
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/.module

@@ -0,0 +1 @@
+name: x86_64_inventec_d5264q28b

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/Makefile

@@ -0,0 +1,9 @@
+###############################################################################
+#
+# 
+#
+###############################################################################
+include ../../init.mk
+MODULE := x86_64_inventec_d5264q28b
+AUTOMODULE := x86_64_inventec_d5264q28b
+include $(BUILDER)/definemodule.mk

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/auto/make.mk

@@ -0,0 +1,9 @@
+###############################################################################
+#
+# x86_64_inventec_d5264q28b Autogeneration
+#
+###############################################################################
+x86_64_inventec_d5264q28b_AUTO_DEFS := module/auto/x86_64_inventec_d5264q28b.yml
+x86_64_inventec_d5264q28b_AUTO_DIRS := module/inc/x86_64_inventec_d5264q28b module/src
+include $(BUILDER)/auto.mk
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/auto/x86_64_inventec_d5264q28b.yml

@@ -0,0 +1,50 @@
+###############################################################################
+#
+# x86_64_inventec_d5264q28b Autogeneration Definitions.
+#
+###############################################################################
+
+cdefs: &cdefs
+- x86_64_inventec_d5264q28b_CONFIG_INCLUDE_LOGGING:
+    doc: "Include or exclude logging."
+    default: 1
+- x86_64_inventec_d5264q28b_CONFIG_LOG_OPTIONS_DEFAULT:
+    doc: "Default enabled log options."
+    default: AIM_LOG_OPTIONS_DEFAULT
+- x86_64_inventec_d5264q28b_CONFIG_LOG_BITS_DEFAULT:
+    doc: "Default enabled log bits."
+    default: AIM_LOG_BITS_DEFAULT
+- x86_64_inventec_d5264q28b_CONFIG_LOG_CUSTOM_BITS_DEFAULT:
+    doc: "Default enabled custom log bits."
+    default: 0
+- x86_64_inventec_d5264q28b_CONFIG_PORTING_STDLIB:
+    doc: "Default all porting macros to use the C standard libraries."
+    default: 1
+- x86_64_inventec_d5264q28b_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS:
+    doc: "Include standard library headers for stdlib porting macros."
+    default: x86_64_inventec_d5264q28b_CONFIG_PORTING_STDLIB
+- x86_64_inventec_d5264q28b_CONFIG_INCLUDE_UCLI:
+    doc: "Include generic uCli support."
+    default: 0
+- x86_64_inventec_d5264q28b_CONFIG_INCLUDE_DEFAULT_FAN_DIRECTION:
+    doc: "Assume chassis fan direction is the same as the PSU fan direction."
+    default: 0
+
+
+definitions:
+  cdefs:
+    x86_64_inventec_d5264q28b_CONFIG_HEADER:
+      defs: *cdefs
+      basename: x86_64_inventec_d5264q28b_config
+
+  portingmacro:
+    x86_64_inventec_d5264q28b:
+      macros:
+        - malloc
+        - free
+        - memset
+        - memcpy
+        - strncpy
+        - vsnprintf
+        - snprintf
+        - strlen

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/inc/x86_64_inventec_d5264q28b/x86_64_inventec_d5264q28b.x

@@ -0,0 +1,14 @@
+/**************************************************************************//**
+ *
+ *
+ *
+ *****************************************************************************/
+#include <x86_64_inventec_d5264q28b/x86_64_inventec_d5264q28b_config.h>
+
+/* <--auto.start.xmacro(ALL).define> */
+/* <auto.end.xmacro(ALL).define> */
+
+/* <--auto.start.xenum(ALL).define> */
+/* <auto.end.xenum(ALL).define> */
+
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/inc/x86_64_inventec_d5264q28b/x86_64_inventec_d5264q28b_config.h

@@ -0,0 +1,137 @@
+/**************************************************************************//**
+ *
+ * @file
+ * @brief x86_64_inventec_d5264q28b Configuration Header
+ *
+ * @addtogroup x86_64_inventec_d5264q28b-config
+ * @{
+ *
+ *****************************************************************************/
+#ifndef __x86_64_inventec_d5264q28b_CONFIG_H__
+#define __x86_64_inventec_d5264q28b_CONFIG_H__
+
+#ifdef GLOBAL_INCLUDE_CUSTOM_CONFIG
+#include <global_custom_config.h>
+#endif
+#ifdef x86_64_inventec_d5264q28b_INCLUDE_CUSTOM_CONFIG
+#include <x86_64_inventec_d5264q28b_custom_config.h>
+#endif
+
+/* <auto.start.cdefs(x86_64_inventec_d5264q28b_CONFIG_HEADER).header> */
+#include <AIM/aim.h>
+/**
+ * x86_64_inventec_d5264q28b_CONFIG_INCLUDE_LOGGING
+ *
+ * Include or exclude logging. */
+
+
+#ifndef x86_64_inventec_d5264q28b_CONFIG_INCLUDE_LOGGING
+#define x86_64_inventec_d5264q28b_CONFIG_INCLUDE_LOGGING 1
+#endif
+
+/**
+ * x86_64_inventec_d5264q28b_CONFIG_LOG_OPTIONS_DEFAULT
+ *
+ * Default enabled log options. */
+
+
+#ifndef x86_64_inventec_d5264q28b_CONFIG_LOG_OPTIONS_DEFAULT
+#define x86_64_inventec_d5264q28b_CONFIG_LOG_OPTIONS_DEFAULT AIM_LOG_OPTIONS_DEFAULT
+#endif
+
+/**
+ * x86_64_inventec_d5264q28b_CONFIG_LOG_BITS_DEFAULT
+ *
+ * Default enabled log bits. */
+
+
+#ifndef x86_64_inventec_d5264q28b_CONFIG_LOG_BITS_DEFAULT
+#define x86_64_inventec_d5264q28b_CONFIG_LOG_BITS_DEFAULT AIM_LOG_BITS_DEFAULT
+#endif
+
+/**
+ * x86_64_inventec_d5264q28b_CONFIG_LOG_CUSTOM_BITS_DEFAULT
+ *
+ * Default enabled custom log bits. */
+
+
+#ifndef x86_64_inventec_d5264q28b_CONFIG_LOG_CUSTOM_BITS_DEFAULT
+#define x86_64_inventec_d5264q28b_CONFIG_LOG_CUSTOM_BITS_DEFAULT 0
+#endif
+
+/**
+ * x86_64_inventec_d5264q28b_CONFIG_PORTING_STDLIB
+ *
+ * Default all porting macros to use the C standard libraries. */
+
+
+#ifndef x86_64_inventec_d5264q28b_CONFIG_PORTING_STDLIB
+#define x86_64_inventec_d5264q28b_CONFIG_PORTING_STDLIB 1
+#endif
+
+/**
+ * x86_64_inventec_d5264q28b_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS
+ *
+ * Include standard library headers for stdlib porting macros. */
+
+
+#ifndef x86_64_inventec_d5264q28b_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS
+#define x86_64_inventec_d5264q28b_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS x86_64_inventec_d5264q28b_CONFIG_PORTING_STDLIB
+#endif
+
+/**
+ * x86_64_inventec_d5264q28b_CONFIG_INCLUDE_UCLI
+ *
+ * Include generic uCli support. */
+
+
+#ifndef x86_64_inventec_d5264q28b_CONFIG_INCLUDE_UCLI
+#define x86_64_inventec_d5264q28b_CONFIG_INCLUDE_UCLI 0
+#endif
+
+/**
+ * x86_64_inventec_d5264q28b_CONFIG_INCLUDE_DEFAULT_FAN_DIRECTION
+ *
+ * Assume chassis fan direction is the same as the PSU fan direction. */
+
+
+#ifndef x86_64_inventec_d5264q28b_CONFIG_INCLUDE_DEFAULT_FAN_DIRECTION
+#define x86_64_inventec_d5264q28b_CONFIG_INCLUDE_DEFAULT_FAN_DIRECTION 0
+#endif
+
+
+
+/**
+ * All compile time options can be queried or displayed
+ */
+
+/** Configuration settings structure. */
+typedef struct x86_64_inventec_d5264q28b_config_settings_s {
+    /** name */
+    const char* name;
+    /** value */
+    const char* value;
+} x86_64_inventec_d5264q28b_config_settings_t;
+
+/** Configuration settings table. */
+/** x86_64_inventec_d5264q28b_config_settings table. */
+extern x86_64_inventec_d5264q28b_config_settings_t x86_64_inventec_d5264q28b_config_settings[];
+
+/**
+ * @brief Lookup a configuration setting.
+ * @param setting The name of the configuration option to lookup.
+ */
+const char* x86_64_inventec_d5264q28b_config_lookup(const char* setting);
+
+/**
+ * @brief Show the compile-time configuration.
+ * @param pvs The output stream.
+ */
+int x86_64_inventec_d5264q28b_config_show(struct aim_pvs_s* pvs);
+
+/* <auto.end.cdefs(x86_64_inventec_d5264q28b_CONFIG_HEADER).header> */
+
+#include "x86_64_inventec_d5264q28b_porting.h"
+
+#endif /* __x86_64_inventec_d5264q28b_CONFIG_H__ */
+/* @} */

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/inc/x86_64_inventec_d5264q28b/x86_64_inventec_d5264q28b_dox.h

@@ -0,0 +1,26 @@
+/**************************************************************************//**
+ *
+ * x86_64_inventec_d5264q28b Doxygen Header
+ *
+ *****************************************************************************/
+#ifndef __x86_64_inventec_d5264q28b_DOX_H__
+#define __x86_64_inventec_d5264q28b_DOX_H__
+
+/**
+ * @defgroup x86_64_inventec_d5264q28b x86_64_inventec_d5264q28b - x86_64_inventec_d5264q28b Description
+ *
+
+The documentation overview for this module should go here.
+
+ *
+ * @{
+ *
+ * @defgroup x86_64_inventec_d5264q28b-x86_64_inventec_d5264q28b Public Interface
+ * @defgroup x86_64_inventec_d5264q28b-config Compile Time Configuration
+ * @defgroup x86_64_inventec_d5264q28b-porting Porting Macros
+ *
+ * @}
+ *
+ */
+
+#endif /* __x86_64_inventec_d5264q28b_DOX_H__ */

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/inc/x86_64_inventec_d5264q28b/x86_64_inventec_d5264q28b_porting.h

@@ -0,0 +1,107 @@
+/**************************************************************************//**
+ *
+ * @file
+ * @brief x86_64_inventec_d5264q28b Porting Macros.
+ *
+ * @addtogroup x86_64_inventec_d5264q28b-porting
+ * @{
+ *
+ *****************************************************************************/
+#ifndef __x86_64_inventec_d5264q28b_PORTING_H__
+#define __x86_64_inventec_d5264q28b_PORTING_H__
+
+
+/* <auto.start.portingmacro(ALL).define> */
+#if x86_64_inventec_d5264q28b_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS == 1
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdarg.h>
+#include <memory.h>
+#endif
+
+#ifndef x86_64_inventec_d5264q28b_MALLOC
+    #if defined(GLOBAL_MALLOC)
+        #define x86_64_inventec_d5264q28b_MALLOC GLOBAL_MALLOC
+    #elif x86_64_inventec_d5264q28b_CONFIG_PORTING_STDLIB == 1
+        #define x86_64_inventec_d5264q28b_MALLOC malloc
+    #else
+        #error The macro x86_64_inventec_d5264q28b_MALLOC is required but cannot be defined.
+    #endif
+#endif
+
+#ifndef x86_64_inventec_d5264q28b_FREE
+    #if defined(GLOBAL_FREE)
+        #define x86_64_inventec_d5264q28b_FREE GLOBAL_FREE
+    #elif x86_64_inventec_d5264q28b_CONFIG_PORTING_STDLIB == 1
+        #define x86_64_inventec_d5264q28b_FREE free
+    #else
+        #error The macro x86_64_inventec_d5264q28b_FREE is required but cannot be defined.
+    #endif
+#endif
+
+#ifndef x86_64_inventec_d5264q28b_MEMSET
+    #if defined(GLOBAL_MEMSET)
+        #define x86_64_inventec_d5264q28b_MEMSET GLOBAL_MEMSET
+    #elif x86_64_inventec_d5264q28b_CONFIG_PORTING_STDLIB == 1
+        #define x86_64_inventec_d5264q28b_MEMSET memset
+    #else
+        #error The macro x86_64_inventec_d5264q28b_MEMSET is required but cannot be defined.
+    #endif
+#endif
+
+#ifndef x86_64_inventec_d5264q28b_MEMCPY
+    #if defined(GLOBAL_MEMCPY)
+        #define x86_64_inventec_d5264q28b_MEMCPY GLOBAL_MEMCPY
+    #elif x86_64_inventec_d5264q28b_CONFIG_PORTING_STDLIB == 1
+        #define x86_64_inventec_d5264q28b_MEMCPY memcpy
+    #else
+        #error The macro x86_64_inventec_d5264q28b_MEMCPY is required but cannot be defined.
+    #endif
+#endif
+
+#ifndef x86_64_inventec_d5264q28b_STRNCPY
+    #if defined(GLOBAL_STRNCPY)
+        #define x86_64_inventec_d5264q28b_STRNCPY GLOBAL_STRNCPY
+    #elif x86_64_inventec_d5264q28b_CONFIG_PORTING_STDLIB == 1
+        #define x86_64_inventec_d5264q28b_STRNCPY strncpy
+    #else
+        #error The macro x86_64_inventec_d5264q28b_STRNCPY is required but cannot be defined.
+    #endif
+#endif
+
+#ifndef x86_64_inventec_d5264q28b_VSNPRINTF
+    #if defined(GLOBAL_VSNPRINTF)
+        #define x86_64_inventec_d5264q28b_VSNPRINTF GLOBAL_VSNPRINTF
+    #elif x86_64_inventec_d5264q28b_CONFIG_PORTING_STDLIB == 1
+        #define x86_64_inventec_d5264q28b_VSNPRINTF vsnprintf
+    #else
+        #error The macro x86_64_inventec_d5264q28b_VSNPRINTF is required but cannot be defined.
+    #endif
+#endif
+
+#ifndef x86_64_inventec_d5264q28b_SNPRINTF
+    #if defined(GLOBAL_SNPRINTF)
+        #define x86_64_inventec_d5264q28b_SNPRINTF GLOBAL_SNPRINTF
+    #elif x86_64_inventec_d5264q28b_CONFIG_PORTING_STDLIB == 1
+        #define x86_64_inventec_d5264q28b_SNPRINTF snprintf
+    #else
+        #error The macro x86_64_inventec_d5264q28b_SNPRINTF is required but cannot be defined.
+    #endif
+#endif
+
+#ifndef x86_64_inventec_d5264q28b_STRLEN
+    #if defined(GLOBAL_STRLEN)
+        #define x86_64_inventec_d5264q28b_STRLEN GLOBAL_STRLEN
+    #elif x86_64_inventec_d5264q28b_CONFIG_PORTING_STDLIB == 1
+        #define x86_64_inventec_d5264q28b_STRLEN strlen
+    #else
+        #error The macro x86_64_inventec_d5264q28b_STRLEN is required but cannot be defined.
+    #endif
+#endif
+
+/* <auto.end.portingmacro(ALL).define> */
+
+
+#endif /* __x86_64_inventec_d5264q28b_PORTING_H__ */
+/* @} */

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/make.mk

@@ -0,0 +1,10 @@
+###############################################################################
+#
+# 
+#
+###############################################################################
+THIS_DIR := $(dir $(lastword $(MAKEFILE_LIST)))
+x86_64_inventec_d5264q28b_INCLUDES := -I $(THIS_DIR)inc
+x86_64_inventec_d5264q28b_INTERNAL_INCLUDES := -I $(THIS_DIR)src
+x86_64_inventec_d5264q28b_DEPENDMODULE_ENTRIES := init:x86_64_inventec_d5264q28b ucli:x86_64_inventec_d5264q28b
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/src/Makefile

@@ -0,0 +1,9 @@
+###############################################################################
+#
+# Local source generation targets.
+#
+###############################################################################
+
+ucli:
+	@../../../../tools/uclihandlers.py x86_64_inventec_d5264q28b_ucli.c
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/src/debug.c

@@ -0,0 +1,45 @@
+#include "x86_64_inventec_d5264q28b_int.h"
+
+#if x86_64_inventec_d5264q28b_CONFIG_INCLUDE_DEBUG == 1
+
+#include <unistd.h>
+
+static char help__[] =
+    "Usage: debug [options]\n"
+    "    -c CPLD Versions\n"
+    "    -h Help\n"
+    ;
+
+int
+x86_64_inventec_d5264q28b_debug_main(int argc, char* argv[])
+{
+    int c = 0;
+    int help = 0;
+    int rv = 0;
+
+    while( (c = getopt(argc, argv, "ch")) != -1) {
+        switch(c)
+            {
+            case 'c': c = 1; break;
+            case 'h': help = 1; rv = 0; break;
+            default: help = 1; rv = 1; break;
+            }
+
+    }
+
+    if(help || argc == 1) {
+        printf("%s", help__);
+        return rv;
+    }
+
+    if(c) {
+        printf("Not implemented.\n");
+    }
+
+
+    return 0;
+}
+
+#endif
+
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/src/fani.c

@@ -0,0 +1,398 @@
+/************************************************************
+ * <bsn.cl fy=2014 v=onl>
+ *
+ *           Copyright 2014 Big Switch Networks, Inc.
+ *           Copyright 2014 Accton Technology Corporation.
+ *
+ * Licensed under the Eclipse Public License, Version 1.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ *        http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied. See the License for the specific
+ * language governing permissions and limitations under the
+ * License.
+ *
+ * </bsn.cl>
+ ************************************************************
+ *
+ * Fan Platform Implementation Defaults.
+ *
+ ***********************************************************/
+#include <onlp/platformi/fani.h>
+#include <onlplib/file.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <onlp/platformi/psui.h>
+#include "platform_lib.h"
+
+#define VALIDATE(_id)                           \
+    do {                                        \
+        if(!ONLP_OID_IS_FAN(_id)) { 	        \
+            return ONLP_STATUS_E_INVALID;       \
+        }                                       \
+    } while(0)
+
+
+#define SLOW_PWM 100
+#define NORMAL_PWM 175
+#define MAX_PWM 255
+#define STEP_SIZE 100
+#define FAN_ON_MAIN_BOARD_COUNT 4
+#define LOCAL_ID_TO_PSU_ID(id) (id-FAN_ON_MAIN_BOARD_COUNT)
+
+#define FAN_CAPS ONLP_FAN_CAPS_GET_RPM|ONLP_FAN_CAPS_GET_PERCENTAGE
+
+static int _fani_status_failed_check(uint32_t* status, int local_id);
+static int _fani_status_present_check(uint32_t* status, int local_id);
+
+#define MAKE_FAN_INFO_NODE_ON_FAN_BOARD(id) 			\
+    { 								\
+        { 							\
+            ONLP_FAN_ID_CREATE(ONLP_FAN_##id), "Fan "#id, 0,	\
+            { 							\
+                ONLP_LED_ID_CREATE(ONLP_LED_FAN##id),		\
+            } 							\
+        },							\
+        0, 0							\
+    }
+
+#define MAKE_FAN_INFO_NODE_ON_PSU(psu_id) 		\
+    { 							\
+        { ONLP_FAN_ID_CREATE(ONLP_FAN_PSU_##psu_id), "PSU-"#psu_id" Fan", ONLP_PSU_ID_CREATE(ONLP_PSU_##psu_id)}, \
+        0, 0						\
+    }
+ 
+
+/* Static values */
+static onlp_fan_info_t __onlp_fan_info[ONLP_FAN_COUNT] = {
+    MAKE_FAN_INFO_NODE_ON_FAN_BOARD(1),
+    MAKE_FAN_INFO_NODE_ON_FAN_BOARD(2),
+    MAKE_FAN_INFO_NODE_ON_FAN_BOARD(3),
+    MAKE_FAN_INFO_NODE_ON_FAN_BOARD(4),
+    MAKE_FAN_INFO_NODE_ON_PSU(1),
+    MAKE_FAN_INFO_NODE_ON_PSU(2),
+};
+
+
+/*
+ * This function will be called prior to all of onlp_fani_* functions.
+ */
+int
+onlp_fani_init(void)
+{
+    return ONLP_STATUS_OK;
+}
+
+int
+onlp_fani_info_get(onlp_oid_t id, onlp_fan_info_t* info)
+{
+    int rv = ONLP_STATUS_OK;
+    int local_id;
+    int lrpm, rrpm, pwm, psu_id;
+    VALIDATE(id);
+    pwm = 0;
+
+    local_id = ONLP_OID_ID_GET(id);
+    if(local_id >= ONLP_FAN_MAX) {
+        rv = ONLP_STATUS_E_INVALID;
+    }
+    if(rv ==ONLP_STATUS_OK) {
+        *info = __onlp_fan_info[LOCAL_ID_TO_INFO_IDX(local_id)];
+        rv = onlp_fani_status_get(id, &info->status);
+    }
+
+    if(rv == ONLP_STATUS_OK) { 
+        if(info->status & ONLP_FAN_STATUS_PRESENT){
+            switch(local_id){
+                case ONLP_FAN_1:
+                case ONLP_FAN_2:
+                case ONLP_FAN_3:
+                case ONLP_FAN_4:
+                    if(info->status & ONLP_FAN_STATUS_F2B){
+                        info->caps = FAN_CAPS|ONLP_FAN_CAPS_F2B;
+                    }else if(info->status & ONLP_FAN_STATUS_B2F){
+                        info->caps = FAN_CAPS|ONLP_FAN_CAPS_B2F;
+                    }else{
+                        info->caps = FAN_CAPS;
+                    }
+
+                    rv = onlp_file_read_int(&lrpm, INV_HWMON_PREFIX"fan%d_input", local_id*2-1);
+                    if(rv != ONLP_STATUS_OK ){ return rv; }
+                    rv = onlp_file_read_int(&rrpm, INV_HWMON_PREFIX"fan%d_input", local_id*2);
+                    if(rv != ONLP_STATUS_OK ){ return rv; }
+                    rv = onlp_file_read_int(&pwm,INV_HWMON_PREFIX"pwm%d", local_id);
+                    if(rv != ONLP_STATUS_OK ){ return rv; }
+
+                    if(lrpm <=0 && rrpm <=0){
+                        info->rpm = 0; 
+                    }else if(lrpm <= 0){
+                        info->rpm = rrpm;
+                    }else if(rrpm <= 0){
+                        info->rpm = lrpm;
+                    }else{
+                        info->rpm = (lrpm+rrpm)/2;
+                    }
+
+                    break;
+                case ONLP_FAN_PSU_1:
+                case ONLP_FAN_PSU_2:
+                    info->caps = FAN_CAPS|ONLP_FAN_CAPS_F2B;
+                    psu_id = LOCAL_ID_TO_PSU_ID(local_id); 
+                    rv = onlp_file_read_int(&info->rpm,INV_HWMON_PREFIX"rpm_psu%d", psu_id);
+                    if(rv != ONLP_STATUS_OK) { return rv; }
+                    rv = onlp_file_read_int(&pwm, INV_HWMON_PREFIX"pwm_psu%d", psu_id); 
+                    if(rv != ONLP_STATUS_OK) { return rv; }
+                    break;
+                default:
+                    rv = ONLP_STATUS_E_INVALID;
+                    break;
+                }
+            if(rv == ONLP_STATUS_OK) {
+                if(info->rpm <= 0) {
+                    info->mode = ONLP_FAN_MODE_OFF;
+                    info->percentage = 0;
+                } else {
+                    info->percentage = (pwm*100)/MAX_PWM;
+                    if(pwm < SLOW_PWM) {
+                        info->mode = ONLP_FAN_MODE_SLOW;
+                    } else if(pwm < NORMAL_PWM) {
+                        info->mode = ONLP_FAN_MODE_NORMAL;
+                    } else if(pwm < MAX_PWM) {
+                        info->mode = ONLP_FAN_MODE_FAST;
+                    } else {
+                        info->mode = ONLP_FAN_MODE_MAX;
+                    }
+                }
+            }
+        }else{
+            info->caps = 0;
+            info->rpm = 0;
+            info->percentage = 0;
+            info->mode = ONLP_FAN_MODE_OFF;
+        }
+        snprintf(info->model, ONLP_CONFIG_INFO_STR_MAX, "NA");
+        snprintf(info->serial, ONLP_CONFIG_INFO_STR_MAX, "NA");
+    }
+    return rv;
+}
+static int _fani_status_failed_check(uint32_t* status, int local_id)
+{
+    int rv;
+    int lrpm, rrpm, rpm, pwm, psu_id;
+    switch(local_id){
+        case ONLP_FAN_1:
+        case ONLP_FAN_2:
+        case ONLP_FAN_3:
+        case ONLP_FAN_4:
+            rv = onlp_file_read_int(&lrpm, INV_HWMON_PREFIX"fan%d_input", local_id*2-1);
+            if(rv != ONLP_STATUS_OK ){ return rv; }
+            rv = onlp_file_read_int(&rrpm, INV_HWMON_PREFIX"fan%d_input", local_id*2);
+            if(rv != ONLP_STATUS_OK ){ return rv; }
+            rv = onlp_file_read_int(&pwm,INV_HWMON_PREFIX"pwm%d", local_id);
+            if(rv != ONLP_STATUS_OK ){ return rv; }
+               
+            if( lrpm <= 0 || rrpm <=0 || pwm <=0 || pwm > MAX_PWM){
+                *status |= ONLP_FAN_STATUS_FAILED;
+                *status &= (~ONLP_FAN_STATUS_B2F);
+                *status &= (~ONLP_FAN_STATUS_F2B);
+            }else{
+                *status &= (~ONLP_FAN_STATUS_FAILED);
+            }
+            break;
+        case ONLP_FAN_PSU_1:
+        case ONLP_FAN_PSU_2:
+            psu_id = LOCAL_ID_TO_PSU_ID(local_id);
+            rv = onlp_file_read_int(&rpm, INV_HWMON_PREFIX"rpm_psu%d", psu_id);
+            if(rv != ONLP_STATUS_OK ){ return rv; }
+            rv = onlp_file_read_int(&pwm, INV_HWMON_PREFIX"pwm_psu%d", psu_id);
+            if(rv != ONLP_STATUS_OK ){ return rv; }
+
+            if( rpm <= 0 || pwm <=0 || pwm > MAX_PWM){
+                *status |= ONLP_FAN_STATUS_FAILED;
+                *status &= (~ONLP_FAN_STATUS_B2F);
+                *status &= (~ONLP_FAN_STATUS_F2B);
+            }else{
+                *status &= (~ONLP_FAN_STATUS_FAILED);
+            } 
+            break;
+        default:
+            rv = ONLP_STATUS_E_INVALID;
+            break;
+    }    
+    return rv;
+}
+
+static int _fani_status_present_check(uint32_t* status, int local_id)
+{
+    int rv;
+    int gpi;
+    int info_idx;
+    int len;
+    char buf[ONLP_CONFIG_INFO_STR_MAX];
+    info_idx = LOCAL_ID_TO_INFO_IDX(local_id);
+    rv = onlp_file_read((uint8_t*)buf,ONLP_CONFIG_INFO_STR_MAX, &len, INV_HWMON_PREFIX"fan_gpi"); 
+    if( rv == ONLP_STATUS_OK ){
+        sscanf( buf, "0x%x\n", &gpi);
+        /* B[0-3] installed(0)/uninstalled(1)
+           B[4-7] FRtype(0)/RFtype(1) */
+        if (!((gpi>>info_idx) & 1)){
+            *status |= ONLP_FAN_STATUS_PRESENT;
+            if (!((gpi>>(info_idx+4)) & 1)){
+                *status |= ONLP_FAN_STATUS_F2B;
+            }else{
+                *status |= ONLP_FAN_STATUS_B2F;
+            }
+        } else {
+            *status = 0;
+        }
+    }
+    return rv;
+}
+ 
+
+/**
+ * @brief Retrieve the fan's operational status.
+ * @param id The fan OID.
+ * @param rv [out] Receives the fan's operations status flags.
+ * @notes Only operational state needs to be returned -
+ *        PRESENT/FAILED
+ */
+int onlp_fani_status_get(onlp_oid_t id, uint32_t* rv)
+{
+    int result = ONLP_STATUS_OK;
+    onlp_fan_info_t* info;
+    int local_id;
+    VALIDATE(id);
+    uint32_t psu_status;
+
+    local_id = ONLP_OID_ID_GET(id);
+    if(local_id >= ONLP_FAN_MAX) {
+        result = ONLP_STATUS_E_INVALID;
+    } else {
+        info = &__onlp_fan_info[LOCAL_ID_TO_INFO_IDX(local_id)];
+        switch(local_id){
+        case ONLP_FAN_1:
+        case ONLP_FAN_2:
+        case ONLP_FAN_3:
+        case ONLP_FAN_4:
+            result = _fani_status_present_check(&info->status, local_id);
+            if (result == ONLP_STATUS_OK ){
+                if (info->status & ONLP_FAN_STATUS_PRESENT){
+                    result = _fani_status_failed_check(&info->status, local_id);
+                }
+            }
+            break;
+        case ONLP_FAN_PSU_1:
+        case ONLP_FAN_PSU_2:
+            result = onlp_psui_status_get((&info->hdr)->poid, &psu_status);
+            if(result != ONLP_STATUS_OK){ return result; }
+ 
+            if(psu_status & ONLP_PSU_STATUS_PRESENT){
+                info->status |= ONLP_FAN_STATUS_PRESENT;
+                result = _fani_status_failed_check(&info->status, local_id);
+            }else{
+                info->status = 0;
+            }
+            break;
+        default:
+            result = ONLP_STATUS_E_INVALID;
+            break;
+        }
+        *rv = info->status;
+    }
+    return result;
+}
+
+/**
+ * @brief Retrieve the fan's OID hdr.
+ * @param id The fan OID.
+ * @param rv [out] Receives the OID header.
+ */
+int onlp_fani_hdr_get(onlp_oid_t id, onlp_oid_hdr_t* hdr)
+{
+    int result = ONLP_STATUS_OK;
+    onlp_fan_info_t* info;
+    int local_id;
+    VALIDATE(id);
+
+    local_id = ONLP_OID_ID_GET(id);
+    if(local_id >= ONLP_FAN_MAX) {
+        result = ONLP_STATUS_E_INVALID;
+    } else {
+        info = &__onlp_fan_info[LOCAL_ID_TO_INFO_IDX(local_id)];
+        *hdr = info->hdr;
+    }
+    return result;
+}
+
+
+/*
+ * This function sets the speed of the given fan in RPM.
+ *
+ * This function will only be called if the fan supprots the RPM_SET
+ * capability.
+ *
+ * It is optional if you have no fans at all with this feature.
+ */
+int
+onlp_fani_rpm_set(onlp_oid_t id, int rpm)
+{
+    return ONLP_STATUS_E_UNSUPPORTED;
+}
+
+/*
+ * This function sets the fan speed of the given OID as a percentage.
+ *
+ * This will only be called if the OID has the PERCENTAGE_SET
+ * capability.
+ *
+ * It is optional if you have no fans at all with this feature.
+ */
+int
+onlp_fani_percentage_set(onlp_oid_t id, int p)
+{
+    return ONLP_STATUS_E_UNSUPPORTED;
+}
+
+
+/*
+ * This function sets the fan speed of the given OID as per
+ * the predefined ONLP fan speed modes: off, slow, normal, fast, max.
+ *
+ * Interpretation of these modes is up to the platform.
+ *
+ */
+int
+onlp_fani_mode_set(onlp_oid_t id, onlp_fan_mode_t mode)
+{
+    return ONLP_STATUS_E_UNSUPPORTED;
+}
+
+/*
+ * This function sets the fan direction of the given OID.
+ *
+ * This function is only relevant if the fan OID supports both direction
+ * capabilities.
+ *
+ * This function is optional unless the functionality is available.
+ */
+int
+onlp_fani_dir_set(onlp_oid_t id, onlp_fan_dir_t dir)
+{
+    return ONLP_STATUS_E_UNSUPPORTED;
+}
+
+/*
+ * Generic fan ioctl. Optional.
+ */
+int
+onlp_fani_ioctl(onlp_oid_t id, va_list vargs)
+{
+    return ONLP_STATUS_E_UNSUPPORTED;
+}
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/src/ledi.c

@@ -0,0 +1,441 @@
+/************************************************************
+ * <bsn.cl fy=2014 v=onl>
+ *
+ *           Copyright 2014 Big Switch Networks, Inc.
+ *           Copyright 2014 Accton Technology Corporation.
+ *
+ * Licensed under the Eclipse Public License, Version 1.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ *        http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied. See the License for the specific
+ * language governing permissions and limitations under the
+ * License.
+ *
+ * </bsn.cl>
+ ************************************************************
+ *
+ *
+ *
+ ***********************************************************/
+#include <onlp/platformi/ledi.h>
+#include <onlplib/file.h>
+#include <sys/mman.h>
+#include <stdio.h>
+#include <string.h>
+#include <fcntl.h>
+#include <onlp/platformi/fani.h>
+
+#include "platform_lib.h"
+
+#define VALIDATE(_id)                           \
+    do {                                        \
+        if(!ONLP_OID_IS_LED(_id)) {             \
+            return ONLP_STATUS_E_INVALID;       \
+        }                                       \
+    } while(0)
+
+/* LED related data
+ */
+
+/* CAPS*/
+#define SYS_LED_CAPS ONLP_LED_CAPS_ON_OFF|ONLP_LED_CAPS_GREEN|ONLP_LED_CAPS_GREEN_BLINKING|ONLP_LED_CAPS_RED|ONLP_LED_CAPS_RED_BLINKING
+#define FAN_LED_CAPS ONLP_LED_CAPS_RED|ONLP_LED_CAPS_GREEN
+
+#define LOCAL_ID_TO_FAN_ID(id) (id-1)
+
+typedef enum sys_led_mode_e {
+    SYS_LED_MODE_OFF = 0,
+    SYS_LED_MODE_0_5_HZ = 1,
+    SYS_LED_MODE_1_HZ = 2,
+    SYS_LED_MODE_2_HZ = 3,
+    SYS_LED_MODE_ON = 7
+} sys_led_mode_t;
+
+/* function declarations*/
+static int _sys_onlp_led_mode_convert(sys_led_mode_t grn_mode, sys_led_mode_t red_mode, onlp_led_mode_t* pmode);
+static int _sys_onlp_ledi_info_get(onlp_oid_t id, onlp_led_info_t* info);
+static int _fan_onlp_ledi_info_get(onlp_oid_t id, onlp_led_info_t* info);
+static int _sys_onlp_ledi_mode_set(onlp_led_mode_t onlp_mode);
+
+/*
+ * Get the information for the given LED OID.
+ */
+#define MAKE_MGMT_LED_INFO_NODE			\
+    {						\
+        { ONLP_LED_ID_CREATE(ONLP_LED_MGMT), "MGMT LED" , 0 }, \
+        ONLP_LED_STATUS_PRESENT,		\
+        SYS_LED_CAPS,		\
+    }
+
+#define MAKE_LED_INFO_NODE_ON_FAN(fan_id)	\
+    {						\
+        { ONLP_LED_ID_CREATE(ONLP_LED_FAN##fan_id), \
+          "FAN LED "#fan_id,			\
+          ONLP_FAN_ID_CREATE(ONLP_FAN_##fan_id) \
+        },					\
+        0,					\
+        0,					\
+    }
+
+static onlp_led_info_t __onlp_led_info[ONLP_LED_COUNT] = {
+    MAKE_MGMT_LED_INFO_NODE,
+    MAKE_LED_INFO_NODE_ON_FAN(1),
+    MAKE_LED_INFO_NODE_ON_FAN(2),
+    MAKE_LED_INFO_NODE_ON_FAN(3),
+    MAKE_LED_INFO_NODE_ON_FAN(4),
+};
+
+
+
+/* convert platform led type to onlp_led_mode type*/
+static int _sys_onlp_led_mode_convert(sys_led_mode_t grn_mode, sys_led_mode_t red_mode, onlp_led_mode_t* pmode)
+{
+    int rv = ONLP_STATUS_OK;
+    *pmode = ONLP_LED_MODE_OFF;
+
+    switch(grn_mode) {
+        case SYS_LED_MODE_0_5_HZ:
+        case SYS_LED_MODE_1_HZ:
+        case SYS_LED_MODE_2_HZ:
+            *pmode = ONLP_LED_MODE_GREEN_BLINKING;
+            break;
+        case SYS_LED_MODE_ON:
+            *pmode = ONLP_LED_MODE_GREEN;
+            break;
+        case SYS_LED_MODE_OFF:
+            *pmode = ONLP_LED_MODE_OFF;
+            break;
+        default:
+            return ONLP_STATUS_E_INVALID;
+            break;
+    }
+    switch(red_mode) {
+        case SYS_LED_MODE_0_5_HZ:
+        case SYS_LED_MODE_1_HZ:
+        case SYS_LED_MODE_2_HZ:
+            if(grn_mode == SYS_LED_MODE_OFF){
+                *pmode = ONLP_LED_MODE_RED_BLINKING;
+            }else{
+                return ONLP_STATUS_E_INVALID;
+            }
+            break;
+        case SYS_LED_MODE_ON:
+            if(grn_mode == SYS_LED_MODE_OFF){
+                *pmode = ONLP_LED_MODE_RED;
+            }else{
+                return ONLP_STATUS_E_INVALID;
+            }
+            break;
+        case SYS_LED_MODE_OFF:
+            if(grn_mode == SYS_LED_MODE_OFF){
+                *pmode = ONLP_LED_MODE_OFF;
+            }
+            break;
+        default:
+            return ONLP_STATUS_E_INVALID;
+            break;
+    }
+    return rv;
+}
+
+
+static int _sys_onlp_ledi_info_get(onlp_oid_t id, onlp_led_info_t* info)
+{
+    int local_id;
+    int rv = ONLP_STATUS_OK;
+    sys_led_mode_t grn_mode, red_mode;
+    local_id = ONLP_OID_ID_GET(id);
+    int idx = LOCAL_ID_TO_INFO_IDX(local_id);
+    /* Set the onlp_oid_hdr_t and capabilities */
+    *info = __onlp_led_info[idx];
+
+    rv = onlp_file_read_int((int*)&grn_mode, INV_SYSLED_PREFIX"grn_led");
+    if(rv != ONLP_STATUS_OK){ return rv; }
+    rv = onlp_file_read_int((int*)&red_mode, INV_SYSLED_PREFIX"red_led");
+    if(rv != ONLP_STATUS_OK){ return rv; }
+
+    rv = _sys_onlp_led_mode_convert(grn_mode, red_mode, &info->mode);
+    if(rv != ONLP_STATUS_OK){ return rv; }
+
+    /* Set the on/off status */
+    if (info->mode != ONLP_LED_MODE_OFF) {
+        info->status |= ONLP_LED_STATUS_ON;
+    } else {
+        info->status &= (~ONLP_LED_STATUS_ON);
+    }
+    
+
+    return rv;
+}
+
+static int _fan_onlp_ledi_info_get(onlp_oid_t id, onlp_led_info_t* info)
+{
+    int local_id;
+    int rv = ONLP_STATUS_OK;
+    int grn_mode, red_mode;
+
+    local_id = ONLP_OID_ID_GET(id);
+    int fan_id = LOCAL_ID_TO_FAN_ID(local_id);
+    int idx = LOCAL_ID_TO_INFO_IDX(local_id);
+    /* Set the onlp_oid_hdr_t and capabilities */  
+    *info = __onlp_led_info[idx];
+
+    rv = onlp_ledi_status_get(id, &info->status);
+    if( rv != ONLP_STATUS_OK ){ return rv; }
+
+    if( info->status & ONLP_LED_STATUS_PRESENT){    
+        info->caps = FAN_LED_CAPS; 
+        rv = onlp_file_read_int((int*)&grn_mode, INV_HWMON_PREFIX"fan_led_grn%d", fan_id);
+        if(rv != ONLP_STATUS_OK ){ return rv; }
+        rv = onlp_file_read_int((int*)&red_mode, INV_HWMON_PREFIX"fan_led_red%d", fan_id);
+        if(rv != ONLP_STATUS_OK ){ return rv; }
+
+        if(grn_mode == 1 && red_mode == 0){
+            info->mode = ONLP_LED_MODE_GREEN;
+        }else if(grn_mode == 0 && red_mode == 1){
+            info->mode = ONLP_LED_MODE_RED;
+        }else if(grn_mode == 0 && red_mode == 0){
+	    info->mode = ONLP_LED_MODE_OFF;
+	}else{
+            rv = ONLP_STATUS_E_INVALID;
+        }       
+    }else{
+        info->mode = ONLP_LED_MODE_OFF;
+    }
+    return rv;
+}
+
+static int _sys_onlp_ledi_mode_set(onlp_led_mode_t onlp_mode)
+{
+    int rv = ONLP_STATUS_OK;
+
+    if( onlp_mode == ONLP_LED_MODE_OFF){
+        rv = onlp_file_write_int(SYS_LED_MODE_OFF, INV_SYSLED_PREFIX"grn_led");
+        if(rv != ONLP_STATUS_OK ){ return rv; }
+        rv = onlp_file_write_int(SYS_LED_MODE_OFF, INV_SYSLED_PREFIX"red_led");
+    }else{
+        rv = ONLP_STATUS_E_UNSUPPORTED;
+    }
+    return rv;
+}
+
+
+
+/*
+ * This function will be called prior to any other onlp_ledi_* functions.
+ */
+int
+onlp_ledi_init(void)
+{
+    return ONLP_STATUS_OK;
+}
+
+int
+onlp_ledi_info_get(onlp_oid_t id, onlp_led_info_t* info)
+{
+    int rv = ONLP_STATUS_OK;
+    VALIDATE(id);
+    int local_id;
+    local_id = ONLP_OID_ID_GET(id);
+    if(local_id >= ONLP_LED_MAX) {
+        return ONLP_STATUS_E_INVALID;
+    }
+
+    switch(local_id) {
+    case ONLP_LED_MGMT:
+        rv = _sys_onlp_ledi_info_get(id, info);
+        break;
+    case ONLP_LED_FAN1:
+    case ONLP_LED_FAN2:
+    case ONLP_LED_FAN3:
+    case ONLP_LED_FAN4:
+        rv = _fan_onlp_ledi_info_get(id, info);
+        break;
+    default:
+        rv = ONLP_STATUS_E_INVALID;
+        break;
+    }
+    return rv;
+}
+
+/**
+ * @brief Get the LED operational status.
+ * @param id The LED OID
+ * @param rv [out] Receives the operational status.
+ */
+int onlp_ledi_status_get(onlp_oid_t id, uint32_t* rv)
+{
+    int result = ONLP_STATUS_OK;
+    onlp_led_info_t* info;
+
+    VALIDATE(id);
+    int local_id = ONLP_OID_ID_GET(id);
+    int info_idx = LOCAL_ID_TO_INFO_IDX(local_id);
+    int fan_id = LOCAL_ID_TO_FAN_ID(local_id);
+    int mode, grn_mode, red_mode;
+    onlp_led_mode_t pmode;
+    uint32_t fan_status;
+
+    if(local_id >= ONLP_LED_MAX) {
+        result = ONLP_STATUS_E_INVALID;
+    } 
+    if(result == ONLP_STATUS_OK) {
+        info = &__onlp_led_info[info_idx];
+        switch(local_id) {
+        case ONLP_LED_MGMT:
+            result = onlp_file_read_int((int*)&grn_mode, INV_SYSLED_PREFIX"grn_led");
+            if(result != ONLP_STATUS_OK){ return result; }
+            result = onlp_file_read_int((int*)&red_mode, INV_SYSLED_PREFIX"red_led");
+            if(result != ONLP_STATUS_OK){ return result; }
+            
+            result = _sys_onlp_led_mode_convert(grn_mode, red_mode, &pmode);
+            if(result != ONLP_STATUS_OK){ return result; }
+	
+            if( pmode != ONLP_LED_MODE_OFF){
+                info->status |= ONLP_LED_STATUS_ON;
+            }else{
+                info->status &= (~ONLP_LED_STATUS_ON);
+            }
+            
+            *rv = info->status;
+            break; 
+        case ONLP_LED_FAN1:
+        case ONLP_LED_FAN2:
+        case ONLP_LED_FAN3:
+        case ONLP_LED_FAN4:
+            result = onlp_fani_status_get((&info->hdr)->poid, &fan_status);
+            if(result != ONLP_STATUS_OK){ return result; }
+
+            if(fan_status & ONLP_FAN_STATUS_PRESENT){
+                info->status |= ONLP_LED_STATUS_PRESENT;
+                info->status &= (~ONLP_LED_STATUS_ON);
+
+                result = onlp_file_read_int((int*)&mode, INV_HWMON_PREFIX"fan_led_grn%d", fan_id);
+                if(result != ONLP_STATUS_OK){ return result; }
+                if(mode){
+                    info->status |= ONLP_LED_STATUS_ON;
+                }
+
+                result = onlp_file_read_int((int*)&mode, INV_HWMON_PREFIX"fan_led_red%d", fan_id);
+                if(result != ONLP_STATUS_OK){ return result; }
+                if(mode){
+                    info->status |= ONLP_LED_STATUS_ON;
+                }
+            } else {
+                info->status = 0;
+            }
+            *rv = info->status;
+            break;
+        default:
+            result = ONLP_STATUS_E_INVALID;
+            break;
+        }
+    }
+
+    return result;
+}
+
+/**
+ * @brief Get the LED header.
+ * @param id The LED OID
+ * @param rv [out] Receives the header.
+ */
+int onlp_ledi_hdr_get(onlp_oid_t id, onlp_oid_hdr_t* rv)
+{
+    int result = ONLP_STATUS_OK;
+    onlp_led_info_t* info;
+
+    VALIDATE(id);
+
+    int local_id;
+    local_id = ONLP_OID_ID_GET(id);
+    int idx = LOCAL_ID_TO_INFO_IDX(local_id);
+    if(local_id >= ONLP_LED_MAX) {
+        result = ONLP_STATUS_E_INVALID;
+    } else {
+        info = &__onlp_led_info[idx];
+        *rv = info->hdr;
+    }
+    return result;
+}
+
+/*
+ * Turn an LED on or off.
+ *
+ * This function will only be called if the LED OID supports the ONOFF
+ * capability.
+ *
+ * What 'on' means in terms of colors or modes for multimode LEDs is
+ * up to the platform to decide. This is intended as baseline toggle mechanism.
+ */
+int
+onlp_ledi_set(onlp_oid_t id, int on_or_off)
+{
+    onlp_led_mode_t mode;
+    VALIDATE(id);
+    int local_id;
+    local_id = ONLP_OID_ID_GET(id);
+    int idx = LOCAL_ID_TO_INFO_IDX(local_id);
+     
+    if(local_id >= ONLP_LED_MAX) {
+        return ONLP_STATUS_E_INVALID;
+    }
+
+    if (__onlp_led_info[idx].caps & ONLP_LED_CAPS_ON_OFF) {
+        mode = on_or_off?ONLP_LED_MODE_ON:ONLP_LED_MODE_OFF;
+        return onlp_ledi_mode_set(id, mode);
+    }
+
+    return ONLP_STATUS_E_UNSUPPORTED;
+}
+
+/*
+ * This function puts the LED into the given mode. It is a more functional
+ * interface for multimode LEDs.
+ *
+ * Only modes reported in the LED's capabilities will be attempted.
+ */
+int
+onlp_ledi_mode_set(onlp_oid_t id, onlp_led_mode_t mode)
+{
+    int rv = ONLP_STATUS_OK;
+    VALIDATE(id);
+    int local_id;
+    local_id = ONLP_OID_ID_GET(id);
+
+    if(local_id >= ONLP_LED_MAX) {
+        return ONLP_STATUS_E_INVALID;
+    }
+    switch(local_id) {
+    case ONLP_LED_MGMT:
+        rv = _sys_onlp_ledi_mode_set(mode);
+        break;
+    case ONLP_LED_FAN1:
+    case ONLP_LED_FAN2:
+    case ONLP_LED_FAN3:
+    case ONLP_LED_FAN4:
+        rv = ONLP_STATUS_E_UNSUPPORTED;
+        break;
+    default:
+        rv = ONLP_STATUS_E_INVALID;
+        break;
+    }
+ 
+    return rv;
+}
+
+/*
+ * Generic LED ioctl interface.
+ */
+int
+onlp_ledi_ioctl(onlp_oid_t id, va_list vargs)
+{
+    return ONLP_STATUS_E_UNSUPPORTED;
+}
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/src/make.mk

@@ -0,0 +1,9 @@
+###############################################################################
+#
+# 
+#
+###############################################################################
+
+LIBRARY := x86_64_inventec_d5264q28b
+$(LIBRARY)_SUBDIR := $(dir $(lastword $(MAKEFILE_LIST)))
+include $(BUILDER)/lib.mk

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/src/platform_lib.c

@@ -0,0 +1,50 @@
+/************************************************************
+ * <bsn.cl fy=2014 v=onl>
+ *
+ *           Copyright 2014 Big Switch Networks, Inc.
+ *           Copyright 2014 Accton Technology Corporation.
+ *
+ * Licensed under the Eclipse Public License, Version 1.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ *        http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied. See the License for the specific
+ * language governing permissions and limitations under the
+ * License.
+ *
+ * </bsn.cl>
+ ************************************************************
+ *
+ *
+ *
+ ***********************************************************/
+#include <errno.h>
+#include <string.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <AIM/aim.h>
+#include <onlp/onlp.h>
+#include <onlplib/file.h>
+#include "platform_lib.h"
+
+
+int platform_hwmon_diag_enable_read(int *enable)
+{
+    int rv = ONLP_STATUS_OK;
+    rv = onlp_file_read_int((int*)enable, INV_HWMON_PREFIX"diag");
+    return rv;
+}
+
+
+int platform_hwmon_diag_enable_write(int enable)
+{
+    int rv = ONLP_STATUS_OK;
+    rv = onlp_file_write_int(enable, INV_HWMON_PREFIX"diag");
+    return rv;
+}

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/src/platform_lib.h

@@ -0,0 +1,138 @@
+/************************************************************
+ * <bsn.cl fy=2014 v=onl>
+ *
+ *           Copyright 2014 Big Switch Networks, Inc.
+ *           Copyright 2014 Accton Technology Corporation.
+ *
+ * Licensed under the Eclipse Public License, Version 1.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ *        http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied. See the License for the specific
+ * language governing permissions and limitations under the
+ * License.
+ *
+ * </bsn.cl>
+ ************************************************************
+ *
+ *
+ *
+ ***********************************************************/
+#ifndef __PLATFORM_LIB_H__
+#define __PLATFORM_LIB_H__
+
+#include "x86_64_inventec_d5264q28b_log.h"
+
+/* This is definitions for x86-64-inventec-d5264q28b*/
+/* OID map*/
+/*
+ *  SYS---------ONLP_THERMAL_CPU_PHY
+ *         |----ONLP_THERMAL_CPU_CORE0
+ *         |----ONLP_THERMAL_CPU_CORE1
+ *         |----ONLP_THERMAL_CPU_CORE2
+ *         |----ONLP_THERMAL_CPU_CORE3
+ *         |----ONLP_THERMAL_1_ON_MAIN_BROAD
+ *         |----ONLP_THERMAL_2_ON_MAIN_BROAD
+ *         |----ONLP_THERMAL_3_ON_MAIN_BROAD
+ *         |----ONLP_THERMAL_4_ON_MAIN_BROAD
+ *         |----ONLP_THERMAL_5_ON_MAIN_BROAD
+ *         |----ONLP_FAN_1--------ONLP_LED_FAN1
+ *         |
+ *         |----ONLP_FAN_2--------ONLP_LED_FAN2
+ *         |
+ *         |----ONLP_FAN_3--------ONLP_LED_FAN3
+ *         |
+ *         |----ONLP_FAN_4--------ONLP_LED_FAN4
+ *         |
+ *         |----ONLP_PSU_1--------ONLP_THERMAL_1_ON_PSU1
+ *         |                   |--ONLP_THERMAL_2_ON_PSU1
+ *         |                   |--ONLP_FAN_PSU_1
+ *         |
+ *         |----ONLP_PSU_2--------ONLP_THERMAL_1_ON_PSU2
+ *         |                   |--ONLP_THERMAL_2_ON_PSU2
+ *         |                   |--ONLP_FAN_PSU_2
+ *         |
+ *         |----ONLP_LED_MGMT
+ */
+
+#define INV_SYSLED_PREFIX	"/sys/class/hwmon/hwmon2/device/"
+#define INV_HWMON_PREFIX	"/sys/class/hwmon/hwmon1/device/"
+#define INV_CTMP_PREFIX		"/sys/class/hwmon/hwmon0/"
+#define INV_SFP_PREFIX		"/sys/class/swps/"
+#define INV_SYS_PREFIX		"/sys/class/eeprom/vpd/"
+
+#define OID_MAP_TO_INFO_IDX(oid)  ONLP_OID_ID_GET(oid)-1
+#define LOCAL_ID_TO_INFO_IDX(id)  (id-1)
+
+/* Thermal definitions*/
+enum onlp_thermal_id {
+    ONLP_THERMAL_CPU_PHY = 1,
+    ONLP_THERMAL_CPU_CORE0,
+    ONLP_THERMAL_CPU_CORE1,
+    ONLP_THERMAL_CPU_CORE2,
+    ONLP_THERMAL_CPU_CORE3,
+    ONLP_THERMAL_1_ON_MAIN_BROAD,
+    ONLP_THERMAL_2_ON_MAIN_BROAD,
+    ONLP_THERMAL_3_ON_MAIN_BROAD,
+    ONLP_THERMAL_4_ON_MAIN_BROAD,
+    ONLP_THERMAL_5_ON_MAIN_BROAD,
+    ONLP_THERMAL_1_ON_PSU1,
+    ONLP_THERMAL_2_ON_PSU1,
+    ONLP_THERMAL_1_ON_PSU2,
+    ONLP_THERMAL_2_ON_PSU2,
+    ONLP_THERMAL_MAX
+};
+
+#define ONLP_THERMAL_COUNT 14 /*include "reserved"*/
+
+/* Fan definitions*/
+enum onlp_fan_id {
+    ONLP_FAN_1 = 1,
+    ONLP_FAN_2,
+    ONLP_FAN_3,
+    ONLP_FAN_4,
+    ONLP_FAN_PSU_1,
+    ONLP_FAN_PSU_2,
+    ONLP_FAN_MAX
+};
+
+#define ONLP_FAN_COUNT 6 /*include "reserved"*/
+
+/* PSU definitions*/
+enum onlp_psu_id {
+    ONLP_PSU_1 = 1,
+    ONLP_PSU_2,
+    ONLP_PSU_MAX
+};
+
+#define ONLP_PSU_COUNT 2 /*include "reserved"*/
+
+/* LED definitions*/
+enum onlp_led_id {
+    ONLP_LED_MGMT = 1,
+    ONLP_LED_FAN1,
+    ONLP_LED_FAN2,
+    ONLP_LED_FAN3,
+    ONLP_LED_FAN4,
+    ONLP_LED_MAX
+};
+
+#define ONLP_LED_COUNT 5 /*include "reserved"*/
+
+
+/* platform functions*/
+#define PLATFORM_HWMON_DIAG_LOCK platform_hwmon_diag_enable_write(0)
+#define PLATFORM_HWMON_DIAG_UNLOCK platform_hwmon_diag_enable_write(1)
+int platform_hwmon_diag_enable_read(int *enable);
+int platform_hwmon_diag_enable_write(int enable);
+
+
+
+
+#endif  /* __PLATFORM_LIB_H__ */
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/src/psui.c

@@ -0,0 +1,215 @@
+/************************************************************
+ * <bsn.cl fy=2014 v=onl>
+ *
+ *           Copyright 2014 Big Switch Networks, Inc.
+ *           Copyright 2014 Accton Technology Corporation.
+ *
+ * Licensed under the Eclipse Public License, Version 1.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ *        http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied. See the License for the specific
+ * language governing permissions and limitations under the
+ * License.
+ *
+ * </bsn.cl>
+ ************************************************************
+ *
+ *
+ *
+ ***********************************************************/
+#include <stdio.h>
+#include <string.h>
+#include "platform_lib.h"
+#include <onlp/platformi/psui.h>
+#include <onlplib/file.h>
+
+#define VALIDATE(_id)                           \
+    do {                                        \
+        if(!ONLP_OID_IS_PSU(_id)) {             \
+            return ONLP_STATUS_E_INVALID;       \
+        }                                       \
+    } while(0)
+
+
+typedef enum hwmon_psu_state_e {
+    HWMON_PSU_NORMAL = 0,
+    HWMON_PSU_UNPOWERED = 2,       //010
+    HWMON_PSU_FAULT = 4,           //100
+    HWMON_PSU_NOT_INSTALLED = 7    //111
+} hwmon_psu_state_t;
+
+/*
+ * Get all information about the given PSU oid.
+ */
+#define MAKE_PSU_NODE_INFO(id)		\
+    {					\
+        {				\
+            ONLP_PSU_ID_CREATE(ONLP_PSU_##id), "PSU-"#id, 0,		\
+            {								\
+                ONLP_THERMAL_ID_CREATE(ONLP_THERMAL_1_ON_PSU##id),	\
+                ONLP_THERMAL_ID_CREATE(ONLP_THERMAL_2_ON_PSU##id),	\
+                ONLP_FAN_ID_CREATE(ONLP_FAN_PSU_##id)			\
+            }				\
+        },				\
+        "","", 0, 0			\
+    }
+
+static onlp_psu_info_t __onlp_psu_info[ONLP_PSU_COUNT] = {
+    MAKE_PSU_NODE_INFO(1),
+    MAKE_PSU_NODE_INFO(2)
+};
+
+int
+onlp_psui_init(void)
+{
+    return ONLP_STATUS_OK;
+}
+
+
+int
+onlp_psui_info_get(onlp_oid_t id, onlp_psu_info_t* info)
+{
+    int ret   = ONLP_STATUS_OK;
+    int len;
+    int local_id = ONLP_OID_ID_GET(id);
+    uint8_t temp[ONLP_CONFIG_INFO_STR_MAX] = {0};
+
+    VALIDATE(id);
+
+    if(local_id >= ONLP_PSU_MAX) {
+        return ONLP_STATUS_E_INVALID;
+    }
+
+
+    *info = __onlp_psu_info[LOCAL_ID_TO_INFO_IDX(local_id)]; /* Set the onlp_oid_hdr_t */
+
+    ret = onlp_file_read(temp, ONLP_CONFIG_INFO_STR_MAX, &len, INV_HWMON_PREFIX"psoc_psu%d_vender", local_id);
+    if(ret != ONLP_STATUS_OK){ return ret; }
+    /*remove the '\n'*/
+    temp[strlen((char*)temp)-1] = 0;
+    snprintf(info->model, ONLP_CONFIG_INFO_STR_MAX, "%s", temp);
+
+
+    memset(temp, 0, ONLP_CONFIG_INFO_STR_MAX);
+    ret = onlp_file_read(temp, ONLP_CONFIG_INFO_STR_MAX, &len, INV_HWMON_PREFIX"psoc_psu%d_serial", local_id);
+    if(ret != ONLP_STATUS_OK){ return ret; }
+    /*remove the '\n'*/
+    temp[strlen((char*)temp)-1] = 0;
+    snprintf(info->serial, ONLP_CONFIG_INFO_STR_MAX, "%s", temp);
+
+    ret = onlp_psui_status_get(id, &info->status);
+    if(ret != ONLP_STATUS_OK){ return ret; }
+
+    if(info->status & ONLP_PSU_STATUS_PRESENT){
+        info->caps = ONLP_PSU_CAPS_AC;
+        /*millivolts*/
+        ret = onlp_file_read_int(&info->mvin, INV_HWMON_PREFIX"psoc_psu%d_vin", local_id);
+        if(ret != ONLP_STATUS_OK){ return ret; }
+	if(info->mvin >= 0){
+	    info->caps |= ONLP_PSU_CAPS_VIN;
+	}
+        ret = onlp_file_read_int(&info->mvout, INV_HWMON_PREFIX"psoc_psu%d_vout", local_id);
+        if(ret != ONLP_STATUS_OK){ return ret; }
+	if(info->mvout >= 0){
+	    info->caps |= ONLP_PSU_CAPS_VOUT;
+	}
+
+        /* milliamps */
+        ret = onlp_file_read_int(&info->miin, INV_HWMON_PREFIX"psoc_psu%d_iin", local_id);
+        if(ret != ONLP_STATUS_OK){ return ret; }
+	if(info->miin >= 0){
+	    info->caps |= ONLP_PSU_CAPS_IIN;
+	}
+        ret = onlp_file_read_int(&info->miout, INV_HWMON_PREFIX"psoc_psu%d_iout", local_id);
+        if(ret != ONLP_STATUS_OK){ return ret; }
+	if(info->miout >= 0){
+	    info->caps |= ONLP_PSU_CAPS_IOUT;
+	}
+
+        /* milliwatts */
+        ret = onlp_file_read_int(&info->mpin, INV_HWMON_PREFIX"psoc_psu%d_pin", local_id);
+        if(ret != ONLP_STATUS_OK){ return ret; }
+	if(info->mpin >= 0){
+	    info->caps |= ONLP_PSU_CAPS_PIN;
+	}
+        ret = onlp_file_read_int(&info->mpout, INV_HWMON_PREFIX"psoc_psu%d_pout", local_id);
+        if(ret != ONLP_STATUS_OK){ return ret; }
+	if(info->mpout >= 0){
+	    info->caps |= ONLP_PSU_CAPS_POUT;
+	}
+    }
+    return ret;
+}
+
+
+/**
+ * @brief Get the PSU's operational status.
+ * @param id The PSU OID.
+ * @param rv [out] Receives the operational status.
+ */
+int onlp_psui_status_get(onlp_oid_t id, uint32_t* rv)
+{
+    int result = ONLP_STATUS_OK;
+    hwmon_psu_state_t psu_state;
+    int local_id;
+    VALIDATE(id);
+    int len;
+    char buf[ONLP_CONFIG_INFO_STR_MAX];
+
+    local_id = ONLP_OID_ID_GET(id);
+    if(local_id >= ONLP_PSU_MAX) {
+        result = ONLP_STATUS_E_INVALID;
+    } else {
+        result = onlp_file_read((uint8_t*)&buf, ONLP_CONFIG_INFO_STR_MAX, &len, "%s""psu%d", INV_HWMON_PREFIX, local_id-1);
+        if( result != ONLP_STATUS_OK ){return result;}
+        psu_state = (uint8_t)strtoul(buf, NULL, 0);
+        if( psu_state == HWMON_PSU_UNPOWERED) {
+            *rv = ONLP_PSU_STATUS_PRESENT|ONLP_PSU_STATUS_UNPLUGGED;
+        } else if ( psu_state == HWMON_PSU_NORMAL) {
+            *rv = ONLP_PSU_STATUS_PRESENT;
+        } else if( psu_state == HWMON_PSU_FAULT) {
+            *rv = ONLP_PSU_STATUS_PRESENT|ONLP_PSU_STATUS_FAILED;
+        } else if( psu_state == HWMON_PSU_NOT_INSTALLED){
+            *rv = 0;
+        } else{
+            result = ONLP_STATUS_E_INVALID;
+        }
+    }
+    return result;
+}
+
+/**
+ * @brief Get the PSU's oid header.
+ * @param id The PSU OID.
+ * @param rv [out] Receives the header.
+ */
+int onlp_psui_hdr_get(onlp_oid_t id, onlp_oid_hdr_t* rv)
+{
+    int result = ONLP_STATUS_OK;
+    onlp_psu_info_t* info;
+    int local_id;
+    VALIDATE(id);
+
+    local_id = ONLP_OID_ID_GET(id);
+    if(local_id >= ONLP_PSU_MAX) {
+        result = ONLP_STATUS_E_INVALID;
+    } else {
+        info = &__onlp_psu_info[LOCAL_ID_TO_INFO_IDX(local_id)];
+        *rv = info->hdr;
+    }
+    return result;
+}
+
+
+int
+onlp_psui_ioctl(onlp_oid_t pid, va_list vargs)
+{
+    return ONLP_STATUS_E_UNSUPPORTED;
+}
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/src/sfpi.c

@@ -0,0 +1,314 @@
+/************************************************************
+ * <bsn.cl fy=2014 v=onl>
+ *
+ *           Copyright 2014 Big Switch Networks, Inc.
+ *           Copyright 2014 Accton Technology Corporation.
+ *
+ * Licensed under the Eclipse Public License, Version 1.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ *        http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied. See the License for the specific
+ * language governing permissions and limitations under the
+ * License.
+ *
+ * </bsn.cl>
+ ************************************************************
+ *
+ *
+ *
+ ***********************************************************/
+
+#include <onlp/platformi/sfpi.h>
+#include <fcntl.h> /* For O_RDWR && open */
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/ioctl.h>
+#include <onlplib/i2c.h>
+#include "platform_lib.h"
+#include <dirent.h>
+#include <onlplib/file.h>
+
+#define MAX_SFP_PATH 128
+
+#define MUX_START_INDEX 17
+#define QSFP_DEV_ADDR 0x50
+#define NUM_OF_QSFP_PORT 64
+#define NUM_OF_ALL_PORT (NUM_OF_QSFP_PORT)
+
+#define FRONT_PORT_TO_MUX_INDEX(port) (port+MUX_START_INDEX)
+#define VALIDATE_PORT(p) { if ((p < 0) || (p >= NUM_OF_ALL_PORT)) return ONLP_STATUS_E_PARAM; }
+/************************************************************
+ *
+ * SFPI Entry Points
+ *
+ ***********************************************************/
+int
+onlp_sfpi_init(void)
+{
+    /* Called at initialization time */
+    return ONLP_STATUS_OK;
+}
+
+int onlp_sfpi_port_map(int port, int* rport)
+{
+    VALIDATE_PORT(port);
+    *rport = port;
+    return ONLP_STATUS_OK;
+}
+
+int
+onlp_sfpi_bitmap_get(onlp_sfp_bitmap_t* bmap)
+{
+    /*
+     * Ports {0, 63}
+     */
+    int p;
+    AIM_BITMAP_CLR_ALL(bmap);
+
+    for(p = 0; p < NUM_OF_ALL_PORT; p++) {
+        AIM_BITMAP_SET(bmap, p);
+    }
+
+    return ONLP_STATUS_OK;
+}
+
+int
+onlp_sfpi_is_present(int port)
+{
+    /*
+     * Return 1 if present.
+     * Return 0 if not present.
+     * Return < 0 if error.
+     */
+    VALIDATE_PORT(port);
+    int present;
+    int rv;
+    if(onlp_file_read_int(&present, INV_SFP_PREFIX"port%d/present", port) != ONLP_STATUS_OK){
+        return ONLP_STATUS_E_INTERNAL;
+    }
+    if(present == 0){
+        rv = 1;
+    } else if (present == 1){
+        rv = 0;
+    }
+    else {
+        AIM_LOG_ERROR("Unvalid present status %d from port(%d)\r\n",present,port);
+        return ONLP_STATUS_E_INTERNAL;
+    }
+    return rv;
+}
+
+int
+onlp_sfpi_presence_bitmap_get(onlp_sfp_bitmap_t* dst)
+{
+    AIM_BITMAP_CLR_ALL(dst);
+    int port;
+    for(port = 0; port < NUM_OF_ALL_PORT; port++){
+        if(onlp_sfpi_is_present(port) == 1){
+            AIM_BITMAP_MOD(dst, port, 1);
+        }else if(onlp_sfpi_is_present(port) == 0){
+            AIM_BITMAP_MOD(dst, port, 0);
+        }else{
+            return ONLP_STATUS_E_INTERNAL;
+        }
+    }
+    return ONLP_STATUS_OK;
+}
+
+int
+onlp_sfpi_is_rx_los(int port)
+{
+    int rxlos;
+    int rv;
+    int len;
+    char buf[ONLP_CONFIG_INFO_STR_MAX];
+    if(port > NUM_OF_ALL_PORT){
+        return ONLP_STATUS_E_INVALID;
+    }
+    if(onlp_sfpi_is_present(port) == 0){
+        return ONLP_STATUS_E_INVALID;
+    }
+    if(onlp_file_read((uint8_t*)buf, ONLP_CONFIG_INFO_STR_MAX, &len, INV_SFP_PREFIX"port%d/soft_rx_los", port) != ONLP_STATUS_OK){
+        return ONLP_STATUS_E_INTERNAL;
+    }
+    if(sscanf( buf, "0x%x\n", &rxlos) != 1){
+        AIM_LOG_ERROR("Unable to read rxlos from port(%d)\r\n", port);
+        return ONLP_STATUS_E_INTERNAL; 
+    }
+    if(rxlos < 0 || rxlos > 0x0f){
+        AIM_LOG_ERROR("Unable to read rxlos from port(%d)\r\n", port);
+        return ONLP_STATUS_E_INTERNAL;
+    }else if(rxlos == 0){
+        rv = 1;
+    }else{
+        rv = 0;
+    }
+    return rv;
+}
+
+int
+onlp_sfpi_rx_los_bitmap_get(onlp_sfp_bitmap_t* dst)
+{   
+    AIM_BITMAP_CLR_ALL(dst);
+    int port;
+    int isrxlos;
+    for(port = 0; port < NUM_OF_ALL_PORT; port++){
+        if(onlp_sfpi_is_present(port) == 1){
+            isrxlos = onlp_sfpi_is_rx_los(port); 
+            if(isrxlos == 1){
+                AIM_BITMAP_MOD(dst, port, 1);
+            }else if(isrxlos == 0){    
+                AIM_BITMAP_MOD(dst, port, 0); 
+            }else{
+                return ONLP_STATUS_E_INTERNAL; 
+            }
+        }
+    }
+    return ONLP_STATUS_OK;
+}
+
+int
+onlp_sfpi_dom_read(int port, uint8_t data[256])
+{
+    return ONLP_STATUS_E_UNSUPPORTED;
+}
+
+int
+onlp_sfpi_post_insert(int port, sff_info_t* info)
+{
+    return ONLP_STATUS_E_UNSUPPORTED;
+}
+
+int
+onlp_sfpi_eeprom_read(int port, uint8_t data[256])
+{
+    /*
+     * Read the SFP eeprom into data[]
+     *
+     * Return MISSING if SFP is missing.
+     * Return OK if eeprom is read
+     */
+    memset(data, 0, 256);
+    
+    VALIDATE_PORT(port);
+    int sts;
+    int bus = FRONT_PORT_TO_MUX_INDEX(port);
+    sts = onlp_i2c_read(bus, QSFP_DEV_ADDR, 0, 256, data, ONLP_I2C_F_FORCE);
+    if(sts < 0){
+        AIM_LOG_ERROR("Unable to read eeprom from port(%d)\r\n", port);
+        return ONLP_STATUS_E_MISSING;
+    }
+    return ONLP_STATUS_OK;
+}
+
+int
+onlp_sfpi_dev_readb(int port, uint8_t devaddr, uint8_t addr)
+{
+    VALIDATE_PORT(port);
+    int bus = FRONT_PORT_TO_MUX_INDEX(port);
+    return onlp_i2c_readb(bus, devaddr, addr, ONLP_I2C_F_FORCE);
+}
+
+int
+onlp_sfpi_dev_writeb(int port, uint8_t devaddr, uint8_t addr, uint8_t value)
+{
+    VALIDATE_PORT(port);
+    int bus = FRONT_PORT_TO_MUX_INDEX(port);
+    return onlp_i2c_writeb(bus, devaddr, addr, value, ONLP_I2C_F_FORCE);
+}
+
+int
+onlp_sfpi_dev_readw(int port, uint8_t devaddr, uint8_t addr)
+{
+    VALIDATE_PORT(port);
+    int bus = FRONT_PORT_TO_MUX_INDEX(port);
+    return onlp_i2c_readw(bus, devaddr, addr, ONLP_I2C_F_FORCE);
+}
+
+int
+onlp_sfpi_dev_writew(int port, uint8_t devaddr, uint8_t addr, uint16_t value)
+{
+    VALIDATE_PORT(port);
+    int bus = FRONT_PORT_TO_MUX_INDEX(port);
+    return onlp_i2c_writew(bus, devaddr, addr, value, ONLP_I2C_F_FORCE);
+}
+
+int
+onlp_sfpi_control_supported(int port, onlp_sfp_control_t control, int* rv)
+{
+    *rv = 0;
+    if(port >= 0 && port < NUM_OF_QSFP_PORT){
+        switch (control) {
+            case ONLP_SFP_CONTROL_RESET_STATE:
+            case ONLP_SFP_CONTROL_LP_MODE:
+                *rv = 1;
+                break;
+            default:
+                break;
+        }
+    }
+    return ONLP_STATUS_OK;
+}
+
+int
+onlp_sfpi_control_set(int port, onlp_sfp_control_t control, int value)
+{
+    int ret = ONLP_STATUS_E_UNSUPPORTED;
+    if(port >= 0 && port < NUM_OF_QSFP_PORT){
+        switch (control) {
+            case ONLP_SFP_CONTROL_RESET_STATE:
+                ret = onlp_file_write_int(value, INV_SFP_PREFIX"port%d/reset", port); 
+                break;
+            case ONLP_SFP_CONTROL_LP_MODE:
+                ret = onlp_file_write_int(value, INV_SFP_PREFIX"port%d/lpmod", port);
+                break;
+            default:
+                break;
+        }
+    }
+    return ret;
+}
+
+int
+onlp_sfpi_control_get(int port, onlp_sfp_control_t control, int* value)
+{
+    int ret = ONLP_STATUS_E_UNSUPPORTED;
+    if(port >= 0 && port < NUM_OF_QSFP_PORT){    
+        switch (control) {
+            case ONLP_SFP_CONTROL_RESET_STATE:
+                ret = onlp_file_read_int(value, INV_SFP_PREFIX"port%d/reset", port); 
+                break;
+            case ONLP_SFP_CONTROL_LP_MODE:
+                ret = onlp_file_read_int(value, INV_SFP_PREFIX"port%d/lpmod", port); 
+                break;
+            default:
+                break;
+        }
+    }
+    return ret;
+}
+
+int
+onlp_sfpi_denit(void)
+{
+    return ONLP_STATUS_OK;
+}
+
+void
+onlp_sfpi_debug(int port, aim_pvs_t* pvs)
+{
+    aim_printf(pvs, "Debug data for port %d goes here.", port);
+}
+
+int
+onlp_sfpi_ioctl(int port, va_list vargs)
+{
+    return ONLP_STATUS_E_UNSUPPORTED;
+}

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/src/sysi.c

@@ -0,0 +1,426 @@
+/************************************************************
+ * <bsn.cl fy=2014 v=onl>
+ *
+ *           Copyright 2014 Big Switch Networks, Inc.
+ *           Copyright 2014 Accton Technology Corporation.
+ *
+ * Licensed under the Eclipse Public License, Version 1.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ *        http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied. See the License for the specific
+ * language governing permissions and limitations under the
+ * License.
+ *
+ * </bsn.cl>
+ ************************************************************
+ *
+ *
+ *
+ ***********************************************************/
+#include <unistd.h>
+#include <fcntl.h>
+#include <linux/i2c-dev.h>
+
+#include <onlplib/file.h>
+#include <onlplib/i2c.h>
+#include <onlplib/onie.h>
+#include <onlp/platformi/sysi.h>
+#include <onlp/platformi/ledi.h>
+#include <onlp/platformi/thermali.h>
+#include <onlp/platformi/fani.h>
+#include <onlp/platformi/psui.h>
+
+#include "x86_64_inventec_d5264q28b_int.h"
+#include "x86_64_inventec_d5264q28b_log.h"
+
+#include "platform_lib.h"
+
+#define SYSI_ONIE_TYPE_SUPPORT_NUM        17
+#define SYSI_PLATFORM_INFO_TYPE_STR_MAX   10
+#define SYSI_PLATFORM_INFO_NUM             2
+
+/**
+ *  The TLV Types.
+ */
+#define TLV_CODE_PRODUCT_NAME   0x21
+#define TLV_CODE_PART_NUMBER    0x22
+#define TLV_CODE_SERIAL_NUMBER  0x23
+#define TLV_CODE_MAC_BASE       0x24
+#define TLV_CODE_MANUF_DATE     0x25
+#define TLV_CODE_DEVICE_VERSION 0x26
+#define TLV_CODE_LABEL_REVISION 0x27
+#define TLV_CODE_PLATFORM_NAME  0x28
+#define TLV_CODE_ONIE_VERSION   0x29
+#define TLV_CODE_MAC_SIZE       0x2A
+#define TLV_CODE_MANUF_NAME     0x2B
+#define TLV_CODE_MANUF_COUNTRY  0x2C
+#define TLV_CODE_VENDOR_NAME    0x2D
+#define TLV_CODE_DIAG_VERSION   0x2E
+#define TLV_CODE_SERVICE_TAG    0x2F
+#define TLV_CODE_VENDOR_EXT     0xFD
+#define TLV_CODE_CRC_32         0xFE
+
+static uint8_t __tlv_code_list[SYSI_ONIE_TYPE_SUPPORT_NUM] = {
+    TLV_CODE_PRODUCT_NAME,
+    TLV_CODE_PART_NUMBER,
+    TLV_CODE_SERIAL_NUMBER,
+    TLV_CODE_MAC_BASE,
+    TLV_CODE_MANUF_DATE,
+    TLV_CODE_DEVICE_VERSION,
+    TLV_CODE_LABEL_REVISION,
+    TLV_CODE_PLATFORM_NAME,
+    TLV_CODE_ONIE_VERSION,
+    TLV_CODE_MAC_SIZE,
+    TLV_CODE_MANUF_NAME,
+    TLV_CODE_MANUF_COUNTRY,
+    TLV_CODE_VENDOR_NAME,
+    TLV_CODE_DIAG_VERSION,
+    TLV_CODE_SERVICE_TAG,
+    TLV_CODE_VENDOR_EXT,
+    TLV_CODE_CRC_32
+};
+
+
+static int _sysi_version_parsing(char* file_str, char* str_buf, char* version);
+static void _case_tlv_code_string(onlp_onie_info_t* info, char** member, char* path);
+static int _parse_tlv(onlp_onie_info_t* info, uint8_t type);
+
+static int _sysi_version_parsing(char* file_str, char* str_buf, char* version)
+{
+    int rv = ONLP_STATUS_OK;
+    int len;
+    char buf[ONLP_CONFIG_INFO_STR_MAX*4];
+    char *temp;
+
+    rv = onlp_file_read((uint8_t*)buf,ONLP_CONFIG_INFO_STR_MAX*4, &len, file_str);
+    if( rv != ONLP_STATUS_OK ) { return rv; }
+
+    temp = strstr(buf, str_buf);
+    if(temp) {
+        temp += strlen(str_buf);
+        snprintf(version,ONLP_CONFIG_INFO_STR_MAX, temp);
+        /*remove '\n'*/
+        version[strlen(version)-1] = '\0';
+    } else {
+        rv = ONLP_STATUS_E_MISSING;
+    }
+    return rv;
+}
+
+static void _case_tlv_code_string(onlp_onie_info_t* info, char** member, char* path)
+{
+    int rv = ONLP_STATUS_OK;
+    int len;
+    char buf[ONLP_CONFIG_INFO_STR_MAX];
+    rv = onlp_file_read((uint8_t*)buf,ONLP_CONFIG_INFO_STR_MAX, &len, path);
+    if( rv == ONLP_STATUS_OK ) {
+        info->_hdr_length += 2;
+        buf[strlen(buf)-1] = '\0';
+        *member = aim_fstrdup("%s",buf);
+        info->_hdr_length += strlen(*member);
+    } else {
+        *member = aim_zmalloc(1);
+        rv = ONLP_STATUS_OK;
+    }
+    return;
+}
+ 
+
+static int _parse_tlv(onlp_onie_info_t* info, uint8_t type)
+{
+    int rv = ONLP_STATUS_OK;
+    int len;
+    char buf[ONLP_CONFIG_INFO_STR_MAX];
+    switch(type)
+       {
+           case TLV_CODE_PRODUCT_NAME:
+               _case_tlv_code_string(info, &(info->product_name), INV_SYS_PREFIX"product_name");
+               break;
+           case TLV_CODE_PART_NUMBER:
+               _case_tlv_code_string(info, &(info->part_number), INV_SYS_PREFIX"pn");
+               break;
+           case TLV_CODE_SERIAL_NUMBER:
+               _case_tlv_code_string(info, &(info->serial_number), INV_SYS_PREFIX"sn");
+               break;
+           case TLV_CODE_MANUF_DATE:
+               _case_tlv_code_string(info, &(info->manufacture_date), INV_SYS_PREFIX"man_date");
+               break;
+           case TLV_CODE_LABEL_REVISION:
+               _case_tlv_code_string(info, &(info->label_revision), INV_SYS_PREFIX"label_rev");
+               break;
+           case TLV_CODE_PLATFORM_NAME:
+               _case_tlv_code_string(info, &(info->platform_name), INV_SYS_PREFIX"plat_name");
+               break;
+           case TLV_CODE_ONIE_VERSION:
+               _case_tlv_code_string(info, &(info->onie_version), INV_SYS_PREFIX"ldr_ver");
+               break;
+           case TLV_CODE_MANUF_NAME:
+               _case_tlv_code_string(info, &(info->manufacturer), INV_SYS_PREFIX"manufacturer");
+               break;
+           case TLV_CODE_MANUF_COUNTRY:
+               _case_tlv_code_string(info, &(info->country_code), INV_SYS_PREFIX"country_code");
+               break;
+           case TLV_CODE_VENDOR_NAME:
+               _case_tlv_code_string(info, &(info->vendor), INV_SYS_PREFIX"vendor_name");
+               break;
+           case TLV_CODE_SERVICE_TAG:
+               _case_tlv_code_string(info, &(info->service_tag), INV_SYS_PREFIX"service_tag");
+               break;
+           case TLV_CODE_DIAG_VERSION:
+               _case_tlv_code_string(info, &(info->diag_version), INV_SYS_PREFIX"diag_ver");
+               break;
+
+           case TLV_CODE_MAC_BASE:
+               rv = onlp_file_read((uint8_t*)buf,ONLP_CONFIG_INFO_STR_MAX, &len, INV_SYS_PREFIX"base_mac_addr" );
+               if( rv == ONLP_STATUS_OK ) {
+                   if(sscanf( buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx\n",                               
+                        &info->mac[0], &info->mac[1], &info->mac[2],
+                        &info->mac[3], &info->mac[4], &info->mac[5]) == 6) {
+                        info->_hdr_length += 2;
+                        info->_hdr_length += 6;
+                   } else {
+                       /*parsing fail*/
+                       memset(info->mac, 0, 6);
+                   }
+               } else {
+                   memset(info->mac, 0, 6);
+                   rv = ONLP_STATUS_OK;
+               }
+               break;
+
+           case TLV_CODE_DEVICE_VERSION:
+               rv = onlp_file_read((uint8_t*)buf,ONLP_CONFIG_INFO_STR_MAX, &len, INV_SYS_PREFIX"dev_ver");
+               if( rv == ONLP_STATUS_OK ) {
+                   info->_hdr_length += 2;
+                   info->device_version= (uint8_t)strtoul(buf, NULL, 0);
+                   info->_hdr_length += 1;
+               }else{
+                   info->device_version = 0;
+                   rv = ONLP_STATUS_OK;
+               }
+               break;
+           case TLV_CODE_MAC_SIZE:
+               rv = onlp_file_read((uint8_t*)buf,ONLP_CONFIG_INFO_STR_MAX, &len, INV_SYS_PREFIX"mac_addr");
+               if( rv == ONLP_STATUS_OK ) {
+                   info->_hdr_length += 2;
+                   info->mac_range = (uint16_t)strtoul(buf, NULL, 0);
+                   info->_hdr_length += 2;
+               }else{
+                   info->mac_range = 0;
+                   rv = ONLP_STATUS_OK;
+               }
+               break;
+
+           case TLV_CODE_VENDOR_EXT:
+               list_init(&info->vx_list);
+               rv = onlp_file_read((uint8_t*)buf,ONLP_CONFIG_INFO_STR_MAX, &len, INV_SYS_PREFIX"vendor_ext");
+               if( rv == ONLP_STATUS_OK ) {
+                   /*TODO*/
+               }
+               rv = ONLP_STATUS_OK;
+               break;
+
+           case TLV_CODE_CRC_32:
+               rv = onlp_file_read((uint8_t*)buf,ONLP_CONFIG_INFO_STR_MAX, &len, INV_SYS_PREFIX"crc32");
+               if( rv == ONLP_STATUS_OK ) {
+                   info->_hdr_length += 2;
+                   info->crc = (uint32_t)strtoul(buf, NULL, 0);
+                   info->_hdr_length += 4;
+               }else{
+                   info->crc = 0;
+                   rv = ONLP_STATUS_OK;
+               }
+               break;
+
+           default:
+               break;
+       }
+    return rv;
+}
+
+
+const char*
+onlp_sysi_platform_get(void)
+{
+    return "x86-64-inventec-d5264q28b-r0";
+}
+
+
+/*
+ * This function is called to return the physical base address
+ * of the ONIE boot rom.
+ *
+ * The ONLP framework will mmap() and parse the ONIE TLV structure
+ * from the given data.
+ *
+ * If you platform does not support a mappable address for the ONIE
+ * eeprom then you should not provide this function at all.
+ *
+ * For the purposes of this example we will provide it but
+ * return UNSUPPORTED (which is all the default implementation does).
+ *
+ */
+int
+onlp_sysi_onie_data_phys_addr_get(void** pa)
+{
+    return ONLP_STATUS_E_UNSUPPORTED;
+}
+
+
+/*
+ * If you cannot provide a base address you must provide the ONLP
+ * framework the raw ONIE data through whatever means necessary.
+ *
+ * This function will be called as a backup in the event that
+ * onlp_sysi_onie_data_phys_addr_get() fails.
+ */
+int
+onlp_sysi_onie_data_get(uint8_t** data, int* size)
+{
+#if 0
+    int rv;
+    int i;
+
+    /*
+     * This represents the example ONIE data.
+     */
+    static uint8_t onie_data[] = {
+        'T', 'l', 'v','I','n','f','o', 0,
+        0x1, 0x0, 0x0,
+        0x21, 0x8, 'O', 'N', 'L', 'P', 'I', 'E', 0, 0,
+        0x22, 0x3, 'O', 'N', 'L',
+        0xFE, 0x4, 0x4b, 0x1b, 0x1d, 0xde,
+    };
+
+
+    memcpy(*data, onie_data, ONLPLIB_CONFIG_I2C_BLOCK_SIZE);
+    return 0;
+#endif
+    return ONLP_STATUS_E_UNSUPPORTED;
+}
+
+/*
+ * IF the ONLP frame calles onlp_sysi_onie_data_get(),
+ * if will call this function to free the data when it
+ * is finished with it.
+ *
+ * This function is optional, and depends on the data
+ * you return in onlp_sysi_onie_data_get().
+ */
+void
+onlp_sysi_onie_data_free(uint8_t* data)
+{
+    /*
+     * We returned a static array in onlp_sysi_onie_data_get()
+     * so no free operation is required.
+     */
+    if(data) {
+        aim_free(data);
+    }
+}
+
+
+int
+onlp_sysi_onie_info_get (onlp_onie_info_t *onie)
+{
+    int rv = ONLP_STATUS_OK;
+    int i;
+    onie->_hdr_length = 0;
+    for(i = 0; i < SYSI_ONIE_TYPE_SUPPORT_NUM; i++)
+    {
+       if( rv != ONLP_STATUS_OK ) { return rv; }
+       rv = _parse_tlv(onie, (__tlv_code_list[i]));
+
+    } 
+
+    onie->_hdr_id_string = aim_fstrdup("TlvInfo");
+    onie->_hdr_version = 0x1;
+    return rv;
+}
+
+
+int
+onlp_sysi_platform_info_get(onlp_platform_info_t* pi)
+{
+    int rv = ONLP_STATUS_OK;
+    char cpld_str[ONLP_CONFIG_INFO_STR_MAX]= {0};
+    char other_str[ONLP_CONFIG_INFO_STR_MAX]= {0};
+    char version[ONLP_CONFIG_INFO_STR_MAX];
+
+    rv = _sysi_version_parsing(INV_SYSLED_PREFIX"info", "The CPLD version is ", version);
+    if( rv != ONLP_STATUS_OK ) { return rv; }
+    snprintf(cpld_str, ONLP_CONFIG_INFO_STR_MAX, "%s%s ", cpld_str, version);
+    rv = _sysi_version_parsing(INV_HWMON_PREFIX"version", "ver: ", version);
+    if( rv != ONLP_STATUS_OK ) { return rv; }
+    snprintf(other_str, ONLP_CONFIG_INFO_STR_MAX, "%s%s.%s "
+                     ,other_str, "psoc", version);
+
+    /*cpld version*/
+    if(strlen(cpld_str) > 0) {
+        pi->cpld_versions = aim_fstrdup("%s",cpld_str);
+    }
+
+    /*other version*/
+    if(strlen(other_str) > 0) {
+        pi->other_versions = aim_fstrdup("%s",other_str);
+    }
+    return rv;
+}
+
+void
+onlp_sysi_platform_info_free(onlp_platform_info_t* pi)
+{
+    if(pi->cpld_versions) {
+        aim_free(pi->cpld_versions);
+    }
+    if(pi->other_versions) {
+        aim_free(pi->other_versions);
+    }
+    return;
+}
+
+
+int
+onlp_sysi_oids_get(onlp_oid_t* table, int max)
+{
+    int i;
+    onlp_oid_t* e = table;
+    memset(table, 0, max*sizeof(onlp_oid_t));
+
+    for(i=1; i<ONLP_THERMAL_MAX; i++){
+        *e++ = ONLP_THERMAL_ID_CREATE(i); 
+    }
+    for(i=1; i<ONLP_FAN_MAX; i++){
+        *e++ = ONLP_FAN_ID_CREATE(i); 
+    }
+    for(i=1; i<ONLP_PSU_MAX; i++){
+        *e++ = ONLP_PSU_ID_CREATE(i); 
+    }
+    for(i=1; i<ONLP_LED_MAX; i++){
+        *e++ = ONLP_LED_ID_CREATE(i); 
+    }
+    return ONLP_STATUS_OK;
+}
+
+int
+onlp_sysi_platform_manage_fans(void)
+{
+    /*Ensure switch manager is working*/
+    PLATFORM_HWMON_DIAG_LOCK;
+    return ONLP_STATUS_OK;
+}
+
+int
+onlp_sysi_platform_manage_leds(void)
+{
+    /*Ensure switch manager is working*/
+    PLATFORM_HWMON_DIAG_LOCK;
+    return ONLP_STATUS_OK;
+}
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/src/thermali.c

@@ -0,0 +1,215 @@
+/************************************************************
+ * <bsn.cl fy=2014 v=onl>
+ *
+ *           Copyright 2014 Big Switch Networks, Inc.
+ *           Copyright 2014 Accton Technology Corporation.
+ *
+ * Licensed under the Eclipse Public License, Version 1.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ *        http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied. See the License for the specific
+ * language governing permissions and limitations under the
+ * License.
+ *
+ * </bsn.cl>
+ ************************************************************
+ *
+ * Thermal Sensor Platform Implementation.
+ *
+ ***********************************************************/
+#include <unistd.h>
+#include <onlplib/file.h>
+#include <onlp/platformi/thermali.h>
+#include <fcntl.h>
+#include <onlp/platformi/psui.h>
+#include "platform_lib.h"
+
+#define VALIDATE(_id)                           \
+    do {                                        \
+        if(!ONLP_OID_IS_THERMAL(_id)) {         \
+            return ONLP_STATUS_E_INVALID;       \
+        }                                       \
+    } while(0)
+
+
+typedef struct thermali_path_s {
+    char file[ONLP_CONFIG_INFO_STR_MAX];
+} thermali_path_t;
+
+#define MAKE_THERMAL_PATH_ON_CPU(id)	        { INV_CTMP_PREFIX"temp"#id"_input"}
+#define MAKE_THERMAL_PATH_ON_MAIN_BROAD(id)   	{ INV_HWMON_PREFIX"temp"#id"_input"}
+#define MAKE_THERMAL1_PATH_ON_PSU(psu_id)	{ INV_HWMON_PREFIX"thermal_psu"#psu_id} 
+#define MAKE_THERMAL2_PATH_ON_PSU(psu_id)       { INV_HWMON_PREFIX"thermal2_psu"#psu_id}
+
+static thermali_path_t __path_list[ONLP_THERMAL_COUNT] = {
+    MAKE_THERMAL_PATH_ON_CPU(1),
+    MAKE_THERMAL_PATH_ON_CPU(2),
+    MAKE_THERMAL_PATH_ON_CPU(3),
+    MAKE_THERMAL_PATH_ON_CPU(4),
+    MAKE_THERMAL_PATH_ON_CPU(5),
+    MAKE_THERMAL_PATH_ON_MAIN_BROAD(1),
+    MAKE_THERMAL_PATH_ON_MAIN_BROAD(2),
+    MAKE_THERMAL_PATH_ON_MAIN_BROAD(3),
+    MAKE_THERMAL_PATH_ON_MAIN_BROAD(4),
+    MAKE_THERMAL_PATH_ON_MAIN_BROAD(5),
+    MAKE_THERMAL1_PATH_ON_PSU(1),
+    MAKE_THERMAL2_PATH_ON_PSU(1),
+    MAKE_THERMAL1_PATH_ON_PSU(2),
+    MAKE_THERMAL2_PATH_ON_PSU(2)
+};
+
+#define MAKE_THERMAL_INFO_NODE_ON_CPU_PHY \
+    {   { ONLP_THERMAL_ID_CREATE(ONLP_THERMAL_CPU_PHY), "CPU Physical", 0}, \
+        ONLP_THERMAL_STATUS_PRESENT, \
+        ONLP_THERMAL_CAPS_GET_TEMPERATURE, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS \
+    }
+#define MAKE_THERMAL_INFO_NODE_ON_CPU_CORE(id) \
+    {   { ONLP_THERMAL_ID_CREATE(ONLP_THERMAL_CPU_CORE##id), "CPU Core "#id, 0},\
+        ONLP_THERMAL_STATUS_PRESENT, \
+        ONLP_THERMAL_CAPS_GET_TEMPERATURE, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS \
+    }
+#define MAKE_THERMAL_INFO_NODE_ON_MAIN_BROAD(id) \
+    {   { ONLP_THERMAL_ID_CREATE(ONLP_THERMAL_##id##_ON_MAIN_BROAD), "Thermal Sensor "#id, 0}, \
+        ONLP_THERMAL_STATUS_PRESENT, \
+        ONLP_THERMAL_CAPS_GET_TEMPERATURE, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS \
+    }
+#define MAKE_THERMAL_INFO_NODE_ON_PSU(thermal_id, psu_id) \
+    {   { \
+            ONLP_THERMAL_ID_CREATE(ONLP_THERMAL_##thermal_id##_ON_PSU##psu_id), \
+           "PSU-"#psu_id" Thermal Sensor "#thermal_id, \
+            ONLP_PSU_ID_CREATE(ONLP_PSU_##psu_id) \
+        }, \
+        ONLP_THERMAL_CAPS_GET_TEMPERATURE, 0, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS \
+    }
+
+/* Static values */
+static onlp_thermal_info_t __onlp_thermal_info[ONLP_THERMAL_COUNT] = {
+    MAKE_THERMAL_INFO_NODE_ON_CPU_PHY,
+    MAKE_THERMAL_INFO_NODE_ON_CPU_CORE(0),
+    MAKE_THERMAL_INFO_NODE_ON_CPU_CORE(1),
+    MAKE_THERMAL_INFO_NODE_ON_CPU_CORE(2),
+    MAKE_THERMAL_INFO_NODE_ON_CPU_CORE(3),
+    MAKE_THERMAL_INFO_NODE_ON_MAIN_BROAD(1),
+    MAKE_THERMAL_INFO_NODE_ON_MAIN_BROAD(2),
+    MAKE_THERMAL_INFO_NODE_ON_MAIN_BROAD(3),
+    MAKE_THERMAL_INFO_NODE_ON_MAIN_BROAD(4),
+    MAKE_THERMAL_INFO_NODE_ON_MAIN_BROAD(5),
+    MAKE_THERMAL_INFO_NODE_ON_PSU(1,1),
+    MAKE_THERMAL_INFO_NODE_ON_PSU(2,1),
+    MAKE_THERMAL_INFO_NODE_ON_PSU(1,2),
+    MAKE_THERMAL_INFO_NODE_ON_PSU(2,2)
+};
+
+/*
+ * This will be called to intiialize the thermali subsystem.
+ */
+int
+onlp_thermali_init(void)
+{
+    return ONLP_STATUS_OK;
+}
+
+/*
+ * Retrieve the information structure for the given thermal OID.
+ *
+ * If the OID is invalid, return ONLP_E_STATUS_INVALID.
+ * If an unexpected error occurs, return ONLP_E_STATUS_INTERNAL.
+ * Otherwise, return ONLP_STATUS_OK with the OID's information.
+ *
+ * Note -- it is expected that you fill out the information
+ * structure even if the sensor described by the OID is not present.
+ */
+int
+onlp_thermali_info_get(onlp_oid_t id, onlp_thermal_info_t* info)
+{
+    int local_id;
+    VALIDATE(id);
+    int ret;
+
+    local_id = ONLP_OID_ID_GET(id);
+    if(local_id >= ONLP_THERMAL_MAX) {
+        return ONLP_STATUS_E_INVALID;
+    }
+
+    /* Set the onlp_oid_hdr_t and capabilities */
+    *info = __onlp_thermal_info[LOCAL_ID_TO_INFO_IDX(local_id)];
+    ret = onlp_thermali_status_get(id, &info->status);
+    if( ret != ONLP_STATUS_OK ){ return ret; }
+
+    if(info->status & ONLP_THERMAL_STATUS_PRESENT){
+        ret = onlp_file_read_int(&info->mcelsius, __path_list[LOCAL_ID_TO_INFO_IDX(local_id)].file);
+    }
+
+    return ret;
+}
+
+
+/**
+ * @brief Retrieve the thermal's operational status.
+ * @param id The thermal oid.
+ * @param rv [out] Receives the operational status.
+ */
+int onlp_thermali_status_get(onlp_oid_t id, uint32_t* rv)
+{
+    int local_id;
+    int ret = ONLP_STATUS_OK;
+    onlp_thermal_info_t* info;
+    VALIDATE(id);
+    uint32_t psu_status;
+
+    local_id = ONLP_OID_ID_GET(id);
+    if(local_id >= ONLP_THERMAL_MAX) {
+        return ONLP_STATUS_E_INVALID;
+    }
+    info = &__onlp_thermal_info[LOCAL_ID_TO_INFO_IDX(local_id)];
+
+    switch(local_id){
+    case ONLP_THERMAL_1_ON_PSU1:
+    case ONLP_THERMAL_2_ON_PSU1:
+    case ONLP_THERMAL_1_ON_PSU2:
+    case ONLP_THERMAL_2_ON_PSU2:
+        ret = onlp_psui_status_get((&info->hdr)->poid, &psu_status);
+        if(ret != ONLP_STATUS_OK){return ret;}
+
+        if(psu_status & ONLP_PSU_STATUS_PRESENT){
+            info->status |= ONLP_THERMAL_STATUS_PRESENT;
+        }else{
+            info->status = 0;
+        }
+        break;
+    default:
+        break;
+    }
+
+    *rv = info->status;
+
+    return ret;
+}
+
+/**
+ * @brief Retrieve the thermal's oid header.
+ * @param id The thermal oid.
+ * @param rv [out] Receives the header.
+ */
+int onlp_thermali_hdr_get(onlp_oid_t id, onlp_oid_hdr_t* rv)
+{
+    int local_id;
+    onlp_thermal_info_t* info;
+    VALIDATE(id);
+
+    local_id = ONLP_OID_ID_GET(id);
+    if(local_id >= ONLP_THERMAL_MAX) {
+        return ONLP_STATUS_E_INVALID;
+    }
+    info = &__onlp_thermal_info[LOCAL_ID_TO_INFO_IDX(local_id)];
+
+    *rv = info->hdr;
+
+    return ONLP_STATUS_OK;
+}

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/src/x86_64_inventec_d5264q28b_config.c

@@ -0,0 +1,81 @@
+/**************************************************************************//**
+ *
+ *
+ *
+ *****************************************************************************/
+#include <x86_64_inventec_d5264q28b/x86_64_inventec_d5264q28b_config.h>
+
+/* <auto.start.cdefs(x86_64_inventec_d5264q28b_CONFIG_HEADER).source> */
+#define __x86_64_inventec_d5264q28b_config_STRINGIFY_NAME(_x) #_x
+#define __x86_64_inventec_d5264q28b_config_STRINGIFY_VALUE(_x) __x86_64_inventec_d5264q28b_config_STRINGIFY_NAME(_x)
+x86_64_inventec_d5264q28b_config_settings_t x86_64_inventec_d5264q28b_config_settings[] =
+{
+#ifdef x86_64_inventec_d5264q28b_CONFIG_INCLUDE_LOGGING
+    { __x86_64_inventec_d5264q28b_config_STRINGIFY_NAME(x86_64_inventec_d5264q28b_CONFIG_INCLUDE_LOGGING), __x86_64_inventec_d5264q28b_config_STRINGIFY_VALUE(x86_64_inventec_d5264q28b_CONFIG_INCLUDE_LOGGING) },
+#else
+{ x86_64_inventec_d5264q28b_CONFIG_INCLUDE_LOGGING(__x86_64_inventec_d5264q28b_config_STRINGIFY_NAME), "__undefined__" },
+#endif
+#ifdef x86_64_inventec_d5264q28b_CONFIG_LOG_OPTIONS_DEFAULT
+    { __x86_64_inventec_d5264q28b_config_STRINGIFY_NAME(x86_64_inventec_d5264q28b_CONFIG_LOG_OPTIONS_DEFAULT), __x86_64_inventec_d5264q28b_config_STRINGIFY_VALUE(x86_64_inventec_d5264q28b_CONFIG_LOG_OPTIONS_DEFAULT) },
+#else
+{ x86_64_inventec_d5264q28b_CONFIG_LOG_OPTIONS_DEFAULT(__x86_64_inventec_d5264q28b_config_STRINGIFY_NAME), "__undefined__" },
+#endif
+#ifdef x86_64_inventec_d5264q28b_CONFIG_LOG_BITS_DEFAULT
+    { __x86_64_inventec_d5264q28b_config_STRINGIFY_NAME(x86_64_inventec_d5264q28b_CONFIG_LOG_BITS_DEFAULT), __x86_64_inventec_d5264q28b_config_STRINGIFY_VALUE(x86_64_inventec_d5264q28b_CONFIG_LOG_BITS_DEFAULT) },
+#else
+{ x86_64_inventec_d5264q28b_CONFIG_LOG_BITS_DEFAULT(__x86_64_inventec_d5264q28b_config_STRINGIFY_NAME), "__undefined__" },
+#endif
+#ifdef x86_64_inventec_d5264q28b_CONFIG_LOG_CUSTOM_BITS_DEFAULT
+    { __x86_64_inventec_d5264q28b_config_STRINGIFY_NAME(x86_64_inventec_d5264q28b_CONFIG_LOG_CUSTOM_BITS_DEFAULT), __x86_64_inventec_d5264q28b_config_STRINGIFY_VALUE(x86_64_inventec_d5264q28b_CONFIG_LOG_CUSTOM_BITS_DEFAULT) },
+#else
+{ x86_64_inventec_d5264q28b_CONFIG_LOG_CUSTOM_BITS_DEFAULT(__x86_64_inventec_d5264q28b_config_STRINGIFY_NAME), "__undefined__" },
+#endif
+#ifdef x86_64_inventec_d5264q28b_CONFIG_PORTING_STDLIB
+    { __x86_64_inventec_d5264q28b_config_STRINGIFY_NAME(x86_64_inventec_d5264q28b_CONFIG_PORTING_STDLIB), __x86_64_inventec_d5264q28b_config_STRINGIFY_VALUE(x86_64_inventec_d5264q28b_CONFIG_PORTING_STDLIB) },
+#else
+{ x86_64_inventec_d5264q28b_CONFIG_PORTING_STDLIB(__x86_64_inventec_d5264q28b_config_STRINGIFY_NAME), "__undefined__" },
+#endif
+#ifdef x86_64_inventec_d5264q28b_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS
+    { __x86_64_inventec_d5264q28b_config_STRINGIFY_NAME(x86_64_inventec_d5264q28b_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS), __x86_64_inventec_d5264q28b_config_STRINGIFY_VALUE(x86_64_inventec_d5264q28b_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS) },
+#else
+{ x86_64_inventec_d5264q28b_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS(__x86_64_inventec_d5264q28b_config_STRINGIFY_NAME), "__undefined__" },
+#endif
+#ifdef x86_64_inventec_d5264q28b_CONFIG_INCLUDE_UCLI
+    { __x86_64_inventec_d5264q28b_config_STRINGIFY_NAME(x86_64_inventec_d5264q28b_CONFIG_INCLUDE_UCLI), __x86_64_inventec_d5264q28b_config_STRINGIFY_VALUE(x86_64_inventec_d5264q28b_CONFIG_INCLUDE_UCLI) },
+#else
+{ x86_64_inventec_d5264q28b_CONFIG_INCLUDE_UCLI(__x86_64_inventec_d5264q28b_config_STRINGIFY_NAME), "__undefined__" },
+#endif
+#ifdef x86_64_inventec_d5264q28b_CONFIG_INCLUDE_DEFAULT_FAN_DIRECTION
+    { __x86_64_inventec_d5264q28b_config_STRINGIFY_NAME(x86_64_inventec_d5264q28b_CONFIG_INCLUDE_DEFAULT_FAN_DIRECTION), __x86_64_inventec_d5264q28b_config_STRINGIFY_VALUE(x86_64_inventec_d5264q28b_CONFIG_INCLUDE_DEFAULT_FAN_DIRECTION) },
+#else
+{ x86_64_inventec_d5264q28b_CONFIG_INCLUDE_DEFAULT_FAN_DIRECTION(__x86_64_inventec_d5264q28b_config_STRINGIFY_NAME), "__undefined__" },
+#endif
+    { NULL, NULL }
+};
+#undef __x86_64_inventec_d5264q28b_config_STRINGIFY_VALUE
+#undef __x86_64_inventec_d5264q28b_config_STRINGIFY_NAME
+
+const char*
+x86_64_inventec_d5264q28b_config_lookup(const char* setting)
+{
+    int i;
+    for(i = 0; x86_64_inventec_d5264q28b_config_settings[i].name; i++) {
+        if(strcmp(x86_64_inventec_d5264q28b_config_settings[i].name, setting)) {
+            return x86_64_inventec_d5264q28b_config_settings[i].value;
+        }
+    }
+    return NULL;
+}
+
+int
+x86_64_inventec_d5264q28b_config_show(struct aim_pvs_s* pvs)
+{
+    int i;
+    for(i = 0; x86_64_inventec_d5264q28b_config_settings[i].name; i++) {
+        aim_printf(pvs, "%s = %s\n", x86_64_inventec_d5264q28b_config_settings[i].name, x86_64_inventec_d5264q28b_config_settings[i].value);
+    }
+    return i;
+}
+
+/* <auto.end.cdefs(x86_64_inventec_d5264q28b_CONFIG_HEADER).source> */
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/src/x86_64_inventec_d5264q28b_enums.c

@@ -0,0 +1,10 @@
+/**************************************************************************//**
+ *
+ *
+ *
+ *****************************************************************************/
+#include <x86_64_inventec_d5264q28b/x86_64_inventec_d5264q28b_config.h>
+
+/* <--auto.start.enum(ALL).source> */
+/* <auto.end.enum(ALL).source> */
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/src/x86_64_inventec_d5264q28b_int.h

@@ -0,0 +1,12 @@
+/**************************************************************************//**
+ *
+ * x86_64_inventec_d5264q28b Internal Header
+ *
+ *****************************************************************************/
+#ifndef __x86_64_inventec_d5264q28b_INT_H__
+#define __x86_64_inventec_d5264q28b_INT_H__
+
+#include <x86_64_inventec_d5264q28b/x86_64_inventec_d5264q28b_config.h>
+
+
+#endif /* __x86_64_inventec_d5264q28b_INT_H__ */

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/src/x86_64_inventec_d5264q28b_log.c

@@ -0,0 +1,18 @@
+/**************************************************************************//**
+ *
+ *
+ *
+ *****************************************************************************/
+#include <x86_64_inventec_d5264q28b/x86_64_inventec_d5264q28b_config.h>
+
+#include "x86_64_inventec_d5264q28b_log.h"
+/*
+ * x86_64_inventec_d5264q28b log struct.
+ */
+AIM_LOG_STRUCT_DEFINE(
+                      x86_64_inventec_d5264q28b_CONFIG_LOG_OPTIONS_DEFAULT,
+                      x86_64_inventec_d5264q28b_CONFIG_LOG_BITS_DEFAULT,
+                      NULL, /* Custom log map */
+                      x86_64_inventec_d5264q28b_CONFIG_LOG_CUSTOM_BITS_DEFAULT
+                     );
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/src/x86_64_inventec_d5264q28b_log.h

@@ -0,0 +1,12 @@
+/**************************************************************************//**
+ *
+ * 
+ *
+ *****************************************************************************/
+#ifndef __x86_64_inventec_d5264q28b_LOG_H__
+#define __x86_64_inventec_d5264q28b_LOG_H__
+
+#define AIM_LOG_MODULE_NAME x86_64_inventec_d5264q28b
+#include <AIM/aim_log.h>
+
+#endif /* __x86_64_inventec_d5264q28b_LOG_H__ */

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/src/x86_64_inventec_d5264q28b_module.c

@@ -0,0 +1,24 @@
+/**************************************************************************//**
+ *
+ *
+ *
+ *****************************************************************************/
+#include <x86_64_inventec_d5264q28b/x86_64_inventec_d5264q28b_config.h>
+
+#include "x86_64_inventec_d5264q28b_log.h"
+
+static int
+datatypes_init__(void)
+{
+#define x86_64_inventec_d5264q28b_ENUMERATION_ENTRY(_enum_name, _desc)     AIM_DATATYPE_MAP_REGISTER(_enum_name, _enum_name##_map, _desc,                               AIM_LOG_INTERNAL);
+#include <x86_64_inventec_d5264q28b/x86_64_inventec_d5264q28b.x>
+    return 0;
+}
+
+void __x86_64_inventec_d5264q28b_module_init__(void)
+{
+    AIM_LOG_STRUCT_REGISTER();
+    datatypes_init__();
+}
+
+int __onlp_platform_version__ = 1;

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/onlp/builds/src/module/src/x86_64_inventec_d5264q28b_ucli.c

@@ -0,0 +1,50 @@
+/**************************************************************************//**
+ *
+ *
+ *
+ *****************************************************************************/
+#include <x86_64_inventec_d5264q28b/x86_64_inventec_d5264q28b_config.h>
+
+#if x86_64_inventec_d5264q28b_CONFIG_INCLUDE_UCLI == 1
+
+#include <uCli/ucli.h>
+#include <uCli/ucli_argparse.h>
+#include <uCli/ucli_handler_macros.h>
+
+static ucli_status_t
+x86_64_inventec_d5264q28b_ucli_ucli__config__(ucli_context_t* uc)
+{
+    UCLI_HANDLER_MACRO_MODULE_CONFIG(x86_64_inventec_d5264q28b)
+}
+
+/* <auto.ucli.handlers.start> */
+/* <auto.ucli.handlers.end> */
+
+static ucli_module_t
+x86_64_inventec_d5264q28b_ucli_module__ =
+    {
+        "x86_64_inventec_d5264q28b_ucli",
+        NULL,
+        x86_64_inventec_d5264q28b_ucli_ucli_handlers__,
+        NULL,
+        NULL,
+    };
+
+ucli_node_t*
+x86_64_inventec_d5264q28b_ucli_node_create(void)
+{
+    ucli_node_t* n;
+    ucli_module_init(&x86_64_inventec_d5264q28b_ucli_module__);
+    n = ucli_node_create("x86_64_inventec_d5264q28b", NULL, &x86_64_inventec_d5264q28b_ucli_module__);
+    ucli_node_subnode_add(n, ucli_module_log_node_create("x86_64_inventec_d5264q28b"));
+    return n;
+}
+
+#else
+void*
+x86_64_inventec_d5264q28b_ucli_node_create(void)
+{
+    return NULL;
+}
+#endif
+

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/platform-config/Makefile

@@ -0,0 +1 @@
+include $(ONL)/make/pkg.mk

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/platform-config/r0/Makefile

@@ -0,0 +1 @@
+include $(ONL)/make/pkg.mk

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/platform-config/r0/PKG.yml

@@ -0,0 +1 @@
+!include $ONL_TEMPLATES/platform-config-platform.yml ARCH=amd64 VENDOR=inventec BASENAME=x86-64-inventec-d5264q28b REVISION=r0

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/platform-config/r0/src/lib/healthstatus.sh

@@ -0,0 +1,53 @@
+#!/bin/bash
+
+normal='0 : normal'
+unpowered='2 : unpowered'
+fault='4 : fault'
+notinstalled='7 : not installed'
+
+while true
+do
+  psu0var=$(cat /sys/bus/i2c/devices/i2c-0/0-0055/psu0)    # bottom PSU
+  psu1var=$(cat /sys/bus/i2c/devices/i2c-0/0-0055/psu1)    # top PSU
+  fan1in=$(cat /sys/class/hwmon/hwmon1/device/fan1_input)  # fanmodule1, far right, back view
+  fan2in=$(cat /sys/class/hwmon/hwmon1/device/fan2_input)  # fanmodule1, far right, back view
+  fan3in=$(cat /sys/class/hwmon/hwmon1/device/fan3_input)  # fanmodule2
+  fan4in=$(cat /sys/class/hwmon/hwmon1/device/fan4_input)  # fanmodule2
+  fan5in=$(cat /sys/class/hwmon/hwmon1/device/fan5_input)  # fanmodule3
+  fan6in=$(cat /sys/class/hwmon/hwmon1/device/fan6_input)  # fanmodule3
+  fan7in=$(cat /sys/class/hwmon/hwmon1/device/fan7_input)  # fanmodule4, far left, back view
+  fan8in=$(cat /sys/class/hwmon/hwmon1/device/fan8_input)  # fanmodule4, far left, back view
+
+  if [ "$psu0var" = "$normal" ] &&
+     [ "$psu1var" = "$normal" ] &&                         # PSU normal operation
+     [ "$fan1in" -gt 0 ] && [ "$fan2in" -gt 0 ] &&         # fan on
+     [ "$fan3in" -gt 0 ] && [ "$fan4in" -gt 0 ] &&
+     [ "$fan5in" -gt 0 ] && [ "$fan6in" -gt 0 ] &&
+     [ "$fan7in" -gt 0 ] && [ "$fan8in" -gt 0 ]
+  then
+    echo 1 > /sys/bus/i2c/devices/i2c-0/0-0055/ctl
+    echo 0 > /sys/bus/i2c/devices/i2c-0/0-0055/red_led     # red off
+    echo 7 > /sys/bus/i2c/devices/i2c-0/0-0055/grn_led     # grn solid
+
+  elif [ "$psu0var" = "$unpowered" ] ||
+       [ "$psu1var" = "$unpowered" ] ||                    # PSU unpowered
+       [ "$fan1in" -eq 0 ] || [ "$fan2in" -eq 0 ] ||       # fan off
+       [ "$fan3in" -eq 0 ] || [ "$fan4in" -eq 0 ] ||
+       [ "$fan5in" -eq 0 ] || [ "$fan6in" -eq 0 ] ||
+       [ "$fan7in" -eq 0 ] || [ "$fan8in" -eq 0 ]
+  then
+    echo 1 > /sys/bus/i2c/devices/i2c-0/0-0055/ctl
+    echo 0 > /sys/bus/i2c/devices/i2c-0/0-0055/red_led     # red off
+    echo 3 > /sys/bus/i2c/devices/i2c-0/0-0055/grn_led     # grn @2Hz
+
+  elif [ "$psu0var" = "$fault" ] ||
+       [ "$psu0var" = "$notinstalled" ] ||
+       [ "$psu1var" = "$fault" ] ||
+       [ "$psu1var" = "$notinstalled" ]                    # PSU fault or PSU not installed
+  then
+    echo 1 > /sys/bus/i2c/devices/i2c-0/0-0055/ctl
+    echo 0 > /sys/bus/i2c/devices/i2c-0/0-0055/grn_led     # grn off
+    echo 7 > /sys/bus/i2c/devices/i2c-0/0-0055/red_led     # red solid
+  fi
+  sleep 1
+done

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/platform-config/r0/src/lib/x86-64-inventec-d5264q28b-r0.yml

@@ -0,0 +1,31 @@
+---
+
+######################################################################
+#
+# platform-config for d5264q28b
+#
+######################################################################
+
+x86-64-inventec-d5264q28b-r0:
+
+  grub:
+
+    serial: >-
+      --port=0x3f8
+      --speed=115200
+      --word=8
+      --parity=no
+      --stop=1
+
+    kernel:
+      <<: *kernel-3-16
+
+    args: >-
+      nopat
+      console=ttyS0,115200n8
+
+  ##network
+  ##  interfaces:
+  ##    ma1:
+  ##      name: ~
+  ##      syspath: pci0000:00/0000:00:14.0

packages/platforms/inventec/x86-64/x86-64-inventec-d5264q28b/platform-config/r0/src/python/x86_64_inventec_d5264q28b_r0/__init__.py

@@ -0,0 +1,43 @@
+from onl.platform.base import *
+from onl.platform.inventec import *
+
+class OnlPlatform_x86_64_inventec_d5264q28b_r0(OnlPlatformInventec,
+                                              OnlPlatformPortConfig_64x100):
+    PLATFORM='x86-64-inventec-d5264q28b-r0'
+    MODEL="D5264Q28B"
+    SYS_OBJECT_ID=".1.32"
+
+    def baseconfig(self):
+	os.system("insmod /lib/modules/`uname -r`/kernel/drivers/gpio/gpio-ich.ko")
+
+        #self.insmod('inv_platform')
+        os.system("echo pca9548 0x70 > /sys/bus/i2c/devices/i2c-0/new_device")
+        os.system("sleep 1")
+        os.system("echo pca9548 0x71 > /sys/bus/i2c/devices/i2c-8/new_device")
+        os.system("sleep 1")
+        #Upper
+        os.system("echo pca9548 0x72 > /sys/bus/i2c/devices/i2c-1/new_device")
+        os.system("echo pca9548 0x72 > /sys/bus/i2c/devices/i2c-2/new_device")
+        os.system("echo pca9548 0x72 > /sys/bus/i2c/devices/i2c-3/new_device")
+        os.system("echo pca9548 0x72 > /sys/bus/i2c/devices/i2c-4/new_device")
+        os.system("sleep 1")
+        #Lower
+        os.system("echo pca9548 0x72 > /sys/bus/i2c/devices/i2c-9/new_device")
+        os.system("echo pca9548 0x72 > /sys/bus/i2c/devices/i2c-10/new_device")
+        os.system("echo pca9548 0x72 > /sys/bus/i2c/devices/i2c-11/new_device")
+        os.system("echo pca9548 0x72 > /sys/bus/i2c/devices/i2c-12/new_device")
+
+        self.insmod('inv_psoc')
+        os.system("echo inv_cpld 0x55 > /sys/bus/i2c/devices/i2c-0/new_device")
+        os.system("echo inv_cpld 0x77 > /sys/bus/i2c/devices/i2c-0/new_device")
+        self.insmod('inv_cpld')
+        self.insmod('inv_mux')
+        self.insmod('io_expander')
+        self.insmod('transceiver')
+        self.insmod('inv_swps')
+	self.insmod('onie_tlvinfo')
+	self.insmod('inv_vpd')
+
+	os.system("/lib/platform-config/x86-64-inventec-d5264q28b-r0/onl/healthstatus.sh &")
+
+        return True