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Merge pull request #181 from jonathantsai-qci/master

Browse Source 
Add IX1 platform:
This commit is contained in:
Jeffrey Townsend
2017-04-12 10:00:31 -07:00
committed by GitHub
parent 10967d52c9 b92ca52f42
commit 9f563b877e
47 changed files with 3345 additions and 12 deletions
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461
packages/platforms/quanta/x86-64/modules/builds/qci_pmbus.c Executable file
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/*
* QUANTA Generic PMBUS driver
*
*
* Based on generic pmbus driver and ltc2978 driver
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <../drivers/hwmon/pmbus/pmbus.h>
#include <linux/delay.h>
enum projects { ly8, ix1, ix2, ix1a };
#define DELAY_TIME 1000 /* uS */
/* Needed to access the mutex. Copied from pmbus_core.c */
#define PB_STATUS_BASE 0
#define PB_STATUS_VOUT_BASE (PB_STATUS_BASE + PMBUS_PAGES)
#define PB_STATUS_IOUT_BASE (PB_STATUS_VOUT_BASE + PMBUS_PAGES)
#define PB_STATUS_FAN_BASE (PB_STATUS_IOUT_BASE + PMBUS_PAGES)
#define PB_STATUS_FAN34_BASE (PB_STATUS_FAN_BASE + PMBUS_PAGES)
#define PB_STATUS_TEMP_BASE (PB_STATUS_FAN34_BASE + PMBUS_PAGES)
#define PB_STATUS_INPUT_BASE (PB_STATUS_TEMP_BASE + PMBUS_PAGES)
#define PB_STATUS_VMON_BASE (PB_STATUS_INPUT_BASE + 1)
#define PB_NUM_STATUS_REG (PB_STATUS_VMON_BASE + 1)
struct pmbus_data {
struct device *dev;
struct device *hwmon_dev;
u32 flags; /* from platform data */
int exponent[PMBUS_PAGES];
/* linear mode: exponent for output voltages */
const struct pmbus_driver_info *info;
int max_attributes;
int num_attributes;
struct attribute_group group;
const struct attribute_group *groups[2];
struct pmbus_sensor *sensors;
struct mutex update_lock;
bool valid;
unsigned long last_updated; /* in jiffies */
/*
* A single status register covers multiple attributes,
* so we keep them all together.
*/
u8 status[PB_NUM_STATUS_REG];
u8 status_register;
u8 currpage;
};
static ssize_t qci_pmbus_show_mfr_id(struct device *dev,
struct device_attribute *da, char *buf)
{
int ret, len;
u8 block_buffer[I2C_SMBUS_BLOCK_MAX + 1], *str;
struct i2c_client *client = container_of(dev, struct i2c_client, dev);
ret = i2c_smbus_read_i2c_block_data(client, PMBUS_MFR_ID, I2C_SMBUS_BLOCK_MAX, block_buffer);
if (ret < 0) {
dev_err(&client->dev, "Failed to read Manufacturer ID\n");
return ret;
}
len = block_buffer[0];
block_buffer[(len+1)] = '\0';
str = &(block_buffer[1]);
return snprintf(buf, PAGE_SIZE, "%s\n", str);
}
static ssize_t qci_pmbus_show_mfr_model(struct device *dev,
struct device_attribute *da, char *buf)
{
int ret, len;
u8 block_buffer[I2C_SMBUS_BLOCK_MAX + 1], *str;
struct i2c_client *client = container_of(dev, struct i2c_client, dev);
ret = i2c_smbus_read_i2c_block_data(client, PMBUS_MFR_MODEL, I2C_SMBUS_BLOCK_MAX, block_buffer);
if (ret < 0) {
dev_err(&client->dev, "Failed to read Manufacturer Model\n");
return ret;
}
len = block_buffer[0];
block_buffer[(len+1)] = '\0';
str = &(block_buffer[1]);
return snprintf(buf, PAGE_SIZE, "%s\n", str);
}
static ssize_t qci_pmbus_show_mfr_revision(struct device *dev,
struct device_attribute *da, char *buf)
{
int ret, len;
u8 block_buffer[I2C_SMBUS_BLOCK_MAX + 1], *str;
struct i2c_client *client = container_of(dev, struct i2c_client, dev);
ret = i2c_smbus_read_i2c_block_data(client, PMBUS_MFR_REVISION, I2C_SMBUS_BLOCK_MAX, block_buffer);
if (ret < 0) {
dev_err(&client->dev, "Failed to read Manufacturer Revision\n");
return ret;
}
len = block_buffer[0];
block_buffer[(len+1)] = '\0';
str = &(block_buffer[1]);
return snprintf(buf, PAGE_SIZE, "%s\n", str);
}
static ssize_t qci_pmbus_show_mfr_location(struct device *dev,
struct device_attribute *da, char *buf)
{
int ret, len;
u8 block_buffer[I2C_SMBUS_BLOCK_MAX + 1], *str;
struct i2c_client *client = container_of(dev, struct i2c_client, dev);
ret = i2c_smbus_read_i2c_block_data(client, PMBUS_MFR_LOCATION, I2C_SMBUS_BLOCK_MAX, block_buffer);
if (ret < 0) {
dev_err(&client->dev, "Failed to read Manufacture Location\n");
return ret;
}
len = block_buffer[0];
block_buffer[(len+1)] = '\0';
str = &(block_buffer[1]);
return snprintf(buf, PAGE_SIZE, "%s\n", str);
}
static ssize_t qci_pmbus_show_mfr_serial(struct device *dev,
struct device_attribute *da, char *buf)
{
int ret, len;
u8 block_buffer[I2C_SMBUS_BLOCK_MAX + 1], *str;
struct i2c_client *client = container_of(dev, struct i2c_client, dev);
ret = i2c_smbus_read_i2c_block_data(client, PMBUS_MFR_SERIAL, I2C_SMBUS_BLOCK_MAX, block_buffer);
if (ret < 0) {
dev_err(&client->dev, "Failed to read Manufacturer Serial\n");
return ret;
}
len = block_buffer[0];
block_buffer[(len+1)] = '\0';
str = &(block_buffer[1]);
return snprintf(buf, PAGE_SIZE, "%s\n", str);
}
static DEVICE_ATTR(mfr_id, S_IRUGO, qci_pmbus_show_mfr_id, NULL);
static DEVICE_ATTR(mfr_model, S_IRUGO, qci_pmbus_show_mfr_model, NULL);
static DEVICE_ATTR(mfr_revision, S_IRUGO, qci_pmbus_show_mfr_revision, NULL);
static DEVICE_ATTR(mfr_location, S_IRUGO, qci_pmbus_show_mfr_location, NULL);
static DEVICE_ATTR(mfr_serial, S_IRUGO, qci_pmbus_show_mfr_serial, NULL);
static struct attribute *qci_pmbus_inventory_attrs[] = {
&dev_attr_mfr_id.attr,
&dev_attr_mfr_model.attr,
&dev_attr_mfr_revision.attr,
&dev_attr_mfr_location.attr,
&dev_attr_mfr_serial.attr,
NULL
};
static struct attribute_group qci_pmbus_inventory_attr_grp = {
.attrs = qci_pmbus_inventory_attrs
};
/* FIXME: add project specific id here */
static const struct i2c_device_id qci_pmbus_id[] = {
{"qci_pmbus_ly8", ly8},
{"qci_pmbus_ix1", ix1},
{"qci_pmbus_ix2", ix2},
{}
};
MODULE_DEVICE_TABLE(i2c, qci_pmbus_id);
/*
* Find sensor groups and status registers on each page.
*/
static void qci_pmbus_find_sensor_groups(struct i2c_client *client,
struct pmbus_driver_info *info)
{
int page;
/* Sensors detected on page 0 only */
if (pmbus_check_word_register(client, 0, PMBUS_READ_VIN))
info->func[0] |= PMBUS_HAVE_VIN;
if (pmbus_check_word_register(client, 0, PMBUS_READ_VCAP))
info->func[0] |= PMBUS_HAVE_VCAP;
if (pmbus_check_word_register(client, 0, PMBUS_READ_IIN))
info->func[0] |= PMBUS_HAVE_IIN;
if (pmbus_check_word_register(client, 0, PMBUS_READ_PIN))
info->func[0] |= PMBUS_HAVE_PIN;
if (info->func[0]
&& pmbus_check_byte_register(client, 0, PMBUS_STATUS_INPUT))
info->func[0] |= PMBUS_HAVE_STATUS_INPUT;
if (pmbus_check_byte_register(client, 0, PMBUS_FAN_CONFIG_12) &&
pmbus_check_word_register(client, 0, PMBUS_READ_FAN_SPEED_1)) {
info->func[0] |= PMBUS_HAVE_FAN12;
if (pmbus_check_byte_register(client, 0, PMBUS_STATUS_FAN_12))
info->func[0] |= PMBUS_HAVE_STATUS_FAN12;
}
if (pmbus_check_byte_register(client, 0, PMBUS_FAN_CONFIG_34) &&
pmbus_check_word_register(client, 0, PMBUS_READ_FAN_SPEED_3)) {
info->func[0] |= PMBUS_HAVE_FAN34;
if (pmbus_check_byte_register(client, 0, PMBUS_STATUS_FAN_34))
info->func[0] |= PMBUS_HAVE_STATUS_FAN34;
}
if (pmbus_check_word_register(client, 0, PMBUS_READ_TEMPERATURE_1))
info->func[0] |= PMBUS_HAVE_TEMP;
if (pmbus_check_word_register(client, 0, PMBUS_READ_TEMPERATURE_2))
info->func[0] |= PMBUS_HAVE_TEMP2;
if (pmbus_check_word_register(client, 0, PMBUS_READ_TEMPERATURE_3))
info->func[0] |= PMBUS_HAVE_TEMP3;
if (info->func[0] & (PMBUS_HAVE_TEMP | PMBUS_HAVE_TEMP2
| PMBUS_HAVE_TEMP3)
&& pmbus_check_byte_register(client, 0,
PMBUS_STATUS_TEMPERATURE))
info->func[0] |= PMBUS_HAVE_STATUS_TEMP;
/* Sensors detected on all pages */
for (page = 0; page < info->pages; page++) {
if (pmbus_check_word_register(client, page, PMBUS_READ_VOUT)) {
info->func[page] |= PMBUS_HAVE_VOUT;
if (pmbus_check_byte_register(client, page,
PMBUS_STATUS_VOUT))
info->func[page] |= PMBUS_HAVE_STATUS_VOUT;
}
if (pmbus_check_word_register(client, page, PMBUS_READ_IOUT)) {
info->func[page] |= PMBUS_HAVE_IOUT;
if (pmbus_check_byte_register(client, 0,
PMBUS_STATUS_IOUT))
info->func[page] |= PMBUS_HAVE_STATUS_IOUT;
}
if (pmbus_check_word_register(client, page, PMBUS_READ_POUT))
info->func[page] |= PMBUS_HAVE_POUT;
}
}
/*
* Identify chip parameters.
*/
static int qci_pmbus_identify(struct i2c_client *client,
struct pmbus_driver_info *info)
{
int ret = 0;
if (!info->pages) {
/*
* Check if the PAGE command is supported. If it is,
* keep setting the page number until it fails or until the
* maximum number of pages has been reached. Assume that
* this is the number of pages supported by the chip.
*/
if (pmbus_check_byte_register(client, 0, PMBUS_PAGE)) {
int page;
for (page = 1; page < PMBUS_PAGES; page++) {
if (pmbus_set_page(client, page) < 0)
break;
}
pmbus_set_page(client, 0);
info->pages = page;
} else {
info->pages = 1;
}
}
if (pmbus_check_byte_register(client, 0, PMBUS_VOUT_MODE)) {
int vout_mode;
vout_mode = pmbus_read_byte_data(client, 0, PMBUS_VOUT_MODE);
if (vout_mode >= 0 && vout_mode != 0xff) {
switch (vout_mode >> 5) {
case 0:
break;
case 1:
info->format[PSC_VOLTAGE_OUT] = vid;
break;
case 2:
info->format[PSC_VOLTAGE_OUT] = direct;
break;
default:
ret = -ENODEV;
goto abort;
}
}
}
/*
* We should check if the COEFFICIENTS register is supported.
* If it is, and the chip is configured for direct mode, we can read
* the coefficients from the chip, one set per group of sensor
* registers.
*
* To do this, we will need access to a chip which actually supports the
* COEFFICIENTS command, since the command is too complex to implement
* without testing it. Until then, abort if a chip configured for direct
* mode was detected.
*/
if (info->format[PSC_VOLTAGE_OUT] == direct) {
ret = -ENODEV;
goto abort;
}
/* if no function pre-defined, try to find sensor groups */
if (info->func[0] == 0) qci_pmbus_find_sensor_groups(client, info);
abort:
return ret;
}
int qci_pmbus_set_page(struct i2c_client *client, u8 page)
{
struct pmbus_data *data = i2c_get_clientdata(client);
int rv = 0;
int newpage;
if (page != data->currpage) {
rv = i2c_smbus_write_byte_data(client, PMBUS_PAGE, page);
udelay(DELAY_TIME);
newpage = i2c_smbus_read_byte_data(client, PMBUS_PAGE);
if (newpage != page)
rv = -EIO;
else
data->currpage = page;
}
return rv;
}
int qci_write_byte(struct i2c_client *client, int page, u8 value)
{
int rv;
if (page >= 0) {
rv = qci_pmbus_set_page(client, page);
if (rv < 0)
return rv;
}
rv = i2c_smbus_write_byte(client, value);
udelay(DELAY_TIME);
return rv;
}
int qci_write_word_data(struct i2c_client *client, int page, int reg, u16 word)
{
int rv;
rv = qci_pmbus_set_page(client, page);
if (rv < 0)
return rv;
rv = i2c_smbus_write_word_data(client, reg, word);
udelay(DELAY_TIME);
return rv;
}
static int qci_pmbus_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct device *dev = &client->dev;
struct pmbus_driver_info *info;
int ret, i;
dev_info(dev, "qci_pmbus_probe\n");
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_READ_WORD_DATA))
return -ENODEV;
info = devm_kzalloc(&client->dev, sizeof(struct pmbus_driver_info),
GFP_KERNEL);
if (!info)
return -ENOMEM;
info->func[0] = 0;
/* FIXME: add project specific function table here */
switch (id->driver_data) {
case ly8:
info->pages = 1;
info->func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_PIN | PMBUS_HAVE_STATUS_INPUT
| PMBUS_HAVE_FAN12 | PMBUS_HAVE_STATUS_FAN12
| PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT
| PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT
;
break;
case ix1:
case ix2:
info->pages = 1;
info->func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_IIN
| PMBUS_HAVE_PIN | PMBUS_HAVE_STATUS_INPUT
| PMBUS_HAVE_FAN12 | PMBUS_HAVE_STATUS_FAN12
| PMBUS_HAVE_TEMP | PMBUS_HAVE_TEMP2
| PMBUS_HAVE_TEMP3 | PMBUS_HAVE_STATUS_TEMP
| PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT
| PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT
| PMBUS_HAVE_POUT
;
break;
default:
break;
}
info->write_word_data = qci_write_word_data;
info->write_byte = qci_write_byte;
info->identify = qci_pmbus_identify; /* FIXME: reserve for future use */
/* Register sysfs hooks */
ret = sysfs_create_group(&dev->kobj, &qci_pmbus_inventory_attr_grp);
if (ret) {
dev_err(dev, "Failed to create sysfs entries\n");
return -1;
}
return pmbus_do_probe(client, id, info);
}
/* This is the driver that will be inserted */
static struct i2c_driver qci_pmbus_driver = {
.driver = {
.name = "qci-pmbus",
},
.probe = qci_pmbus_probe,
.remove = pmbus_do_remove,
.id_table = qci_pmbus_id,
};
module_i2c_driver(qci_pmbus_driver);
MODULE_AUTHOR("Jonathan Tsai (jonathan.tsai@quantatw.com)");
MODULE_VERSION("1.0");
MODULE_DESCRIPTION("QUANTA generic PMBus driver");
MODULE_LICENSE("GPL");

252
packages/platforms/quanta/x86-64/modules/builds/quanta_hwmon_ix_series.c Executable file
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/*
* <bsn.cl fy=2013 v=gpl>
*
* Copyright 2013, 2014 BigSwitch Networks, Inc.
*
* This program is free software; you can redistribute it
* and/or modify it under the terms ofthe GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version.
*
*
* </bsn.cl>
*
* A hwmon driver for the Quanta IX1/IX2
*/
#include <linux/module.h>
#include <linux/jiffies.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/log2.h>
#include <linux/kthread.h>
#include <linux/slab.h>
static const unsigned short normal_i2c[] = { 0x4E, I2C_CLIENT_END };
#define QUANTA_HWMON_REG_TEMP_INPUT_BASE 0x20
#define QUANTA_HWMON_REG_FAN_MODE 0x33
#define QUANTA_HWMON_REG_FAN_DIR 0x56
#define QUANTA_HWMON_REG_FAN_PWM_BASE 0x3C
#define QUANTA_HWMON_REG_FAN_INPUT_BASE 0x40
#define QUANTA_HWMON_FAN_MANUAL_MODE 1
#define QUANTA_HWMON_FAN_SMART_MODE 3
#define QUANTA_HWMON_NUM_FANS 6
struct quanta_hwmon_ix_series_data {
struct device *hwmon_dev;
struct attribute_group attrs;
struct mutex lock;
};
enum quanta_hwmon_ix_series_s {
quanta_ix1_hwmon,
quanta_ix2_hwmon,
};
static int quanta_hwmon_ix_series_probe(struct i2c_client *client,
const struct i2c_device_id *id);
static int quanta_hwmon_ix_series_remove(struct i2c_client *client);
static const struct i2c_device_id quanta_hwmon_ix_series_id[] = {
{ "quanta_ix1_hwmon", quanta_ix1_hwmon },
{ "quanta_ix2_hwmon", quanta_ix2_hwmon },
{ }
};
MODULE_DEVICE_TABLE(i2c, quanta_hwmon_ix_series_id);
static struct i2c_driver quanta_hwmon_ix_series_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "quanta_hwmon_ix_series",
},
.probe = quanta_hwmon_ix_series_probe,
.remove = quanta_hwmon_ix_series_remove,
.id_table = quanta_hwmon_ix_series_id,
.address_list = normal_i2c,
};
static ssize_t show_temp(struct device *dev, struct device_attribute *devattr,
char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct i2c_client *client = to_i2c_client(dev);
struct quanta_hwmon_ix_series_data *data = i2c_get_clientdata(client);
int temp;
mutex_lock(&data->lock);
temp = i2c_smbus_read_byte_data(client,
QUANTA_HWMON_REG_TEMP_INPUT_BASE
+ attr->index);
mutex_unlock(&data->lock);
return sprintf(buf, "%d\n", 1000 * temp);
}
static ssize_t show_fan(struct device *dev, struct device_attribute *devattr,
char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct i2c_client *client = to_i2c_client(dev);
struct quanta_hwmon_ix_series_data *data = i2c_get_clientdata(client);
int fan;
mutex_lock(&data->lock);
fan = i2c_smbus_read_word_swapped(client,
QUANTA_HWMON_REG_FAN_INPUT_BASE
+ 2 * attr->index);
mutex_unlock(&data->lock);
return sprintf(buf, "%d\n", fan);
}
static ssize_t show_pwm(struct device *dev, struct device_attribute *devattr,
char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct i2c_client *client = to_i2c_client(dev);
struct quanta_hwmon_ix_series_data *data = i2c_get_clientdata(client);
int pwm;
mutex_lock(&data->lock);
pwm = i2c_smbus_read_word_swapped(client,
QUANTA_HWMON_REG_FAN_PWM_BASE
+ 2 * attr->index);
mutex_unlock(&data->lock);
return sprintf(buf, "%d\n", pwm * 255 / 10000);
}
static ssize_t set_pwm(struct device *dev, struct device_attribute *devattr,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct i2c_client *client = to_i2c_client(dev);
struct quanta_hwmon_ix_series_data *data = i2c_get_clientdata(client);
long val;
int ret;
ret = kstrtol(buf, 10, &val);
if (ret)
return ret;
mutex_lock(&data->lock);
i2c_smbus_write_word_swapped(client,
QUANTA_HWMON_REG_FAN_PWM_BASE
+ 2 * attr->index, val * 10000 / 255);
mutex_unlock(&data->lock);
return count;
}
static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0);
static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 1);
static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 2);
static SENSOR_DEVICE_ATTR(temp5_input, S_IRUGO, show_temp, NULL, 4);
static SENSOR_DEVICE_ATTR(temp6_input, S_IRUGO, show_temp, NULL, 5);
static SENSOR_DEVICE_ATTR(temp7_input, S_IRUGO, show_temp, NULL, 6);//For IX2
static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0);
static SENSOR_DEVICE_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1);
static SENSOR_DEVICE_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2);
static SENSOR_DEVICE_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3);//For IX1, IX2
static SENSOR_DEVICE_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4);
static SENSOR_DEVICE_ATTR(fan6_input, S_IRUGO, show_fan, NULL, 5);
static SENSOR_DEVICE_ATTR(fan7_input, S_IRUGO, show_fan, NULL, 6);
static SENSOR_DEVICE_ATTR(fan8_input, S_IRUGO, show_fan, NULL, 7);//For IX1, IX2
static SENSOR_DEVICE_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, set_pwm, 0);
static struct attribute *quanta_hwmon_ix_series_attr_5temps_4fans[] = {
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp2_input.dev_attr.attr,
&sensor_dev_attr_temp3_input.dev_attr.attr,
&sensor_dev_attr_temp5_input.dev_attr.attr,
&sensor_dev_attr_temp6_input.dev_attr.attr,
&sensor_dev_attr_fan1_input.dev_attr.attr,
&sensor_dev_attr_fan2_input.dev_attr.attr,
&sensor_dev_attr_fan3_input.dev_attr.attr,
&sensor_dev_attr_fan4_input.dev_attr.attr,
&sensor_dev_attr_fan5_input.dev_attr.attr,
&sensor_dev_attr_fan6_input.dev_attr.attr,
&sensor_dev_attr_fan7_input.dev_attr.attr,
&sensor_dev_attr_fan8_input.dev_attr.attr,
&sensor_dev_attr_pwm1.dev_attr.attr,
NULL
};
static struct attribute *quanta_hwmon_ix_series_attr_6temps_4fans[] = {
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp2_input.dev_attr.attr,
&sensor_dev_attr_temp3_input.dev_attr.attr,
&sensor_dev_attr_temp5_input.dev_attr.attr,
&sensor_dev_attr_temp6_input.dev_attr.attr,
&sensor_dev_attr_temp7_input.dev_attr.attr,
&sensor_dev_attr_fan1_input.dev_attr.attr,
&sensor_dev_attr_fan2_input.dev_attr.attr,
&sensor_dev_attr_fan3_input.dev_attr.attr,
&sensor_dev_attr_fan4_input.dev_attr.attr,
&sensor_dev_attr_fan5_input.dev_attr.attr,
&sensor_dev_attr_fan6_input.dev_attr.attr,
&sensor_dev_attr_fan7_input.dev_attr.attr,
&sensor_dev_attr_fan8_input.dev_attr.attr,
&sensor_dev_attr_pwm1.dev_attr.attr,
NULL
};
static int quanta_hwmon_ix_series_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct quanta_hwmon_ix_series_data *data;
int err;
data = devm_kzalloc(&client->dev, sizeof(struct quanta_hwmon_ix_series_data),
GFP_KERNEL);
if (!data)
return -ENOMEM;
i2c_set_clientdata(client, data);
mutex_init(&data->lock);
dev_info(&client->dev, "%s chip found\n", client->name);
if(!strcmp(client->name, "quanta_ix1_hwmon")){
data->attrs.attrs = quanta_hwmon_ix_series_attr_5temps_4fans;
}
else{
data->attrs.attrs = quanta_hwmon_ix_series_attr_6temps_4fans;
}
err = sysfs_create_group(&client->dev.kobj, &data->attrs);
if (err)
return err;
data->hwmon_dev = hwmon_device_register(&client->dev);
if (IS_ERR(data->hwmon_dev)) {
err = PTR_ERR(data->hwmon_dev);
goto exit_remove;
}
i2c_smbus_write_byte_data(client,
QUANTA_HWMON_REG_FAN_MODE,
QUANTA_HWMON_FAN_SMART_MODE);
return 0;
exit_remove:
sysfs_remove_group(&client->dev.kobj, &data->attrs);
return err;
}
static int quanta_hwmon_ix_series_remove(struct i2c_client *client)
{
struct quanta_hwmon_ix_series_data *data = i2c_get_clientdata(client);
hwmon_device_unregister(data->hwmon_dev);
sysfs_remove_group(&client->dev.kobj, &data->attrs);
return 0;
}
module_i2c_driver(quanta_hwmon_ix_series_driver);
MODULE_AUTHOR("Jonathan Tsai (jonathan.tsai@quantatw.com)");
MODULE_VERSION("1.0");
MODULE_DESCRIPTION("Quanta IX1/IX2 hardware monitor driver");
MODULE_LICENSE("GPL");

2
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/.gitignore vendored Executable file
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@@ -0,0 +1,2 @@
*x86*64*quanta*ix1*rangeley.mk
onlpdump.mk

1
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/Makefile Executable file
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@@ -0,0 +1 @@
include $(ONL)/make/pkg.mk

1
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/modules/Makefile Executable file
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@@ -0,0 +1 @@
include $(ONL)/make/pkg.mk

1
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/modules/PKG.yml Executable file
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@@ -0,0 +1 @@
!include $ONL_TEMPLATES/platform-modules.yml ARCH=amd64 VENDOR=quanta BASENAME=x86-64-quanta-ix1-rangeley KERNELS="onl-kernel-3.16-lts-x86-64-all:amd64"

1
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/modules/builds/.gitignore vendored Executable file
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@@ -0,0 +1 @@
lib

6
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/modules/builds/Makefile Executable file
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@@ -0,0 +1,6 @@
KERNELS := onl-kernel-3.16-lts-x86-64-all:amd64
KMODULES := $(wildcard *.c)
VENDOR := quanta
BASENAME := x86-64-quanta-ix1-rangeley
ARCH := x86_64
include $(ONL)/make/kmodule.mk

330
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/modules/builds/quanta_platform_ix1.c Executable file
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/*
* Quanta Switch platform driver
*
*
* Copyright (C) 2017 Quanta Computer inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/platform_data/pca953x.h>
#include <linux/i2c/pca954x.h>
#include <linux/gpio.h>
#include <linux/i2c-mux-gpio.h>
#include <linux/platform_device.h>
#include <linux/dmi.h>
#define DRIVER_NAME "quanta-platform-ix1"
#define MAX_I2C_CLIENTS 512
#define I2C_GPIO_BASE 0x80
#define XSTR(x) STR(X)
#define STR(x) #x
enum i2c_types {
i2c_type_spd,
i2c_type_rtc,
i2c_type_pca9546,
i2c_type_pca9548,
i2c_type_pca9554,
i2c_type_pca9555,
i2c_type_pca9698,
i2c_type_qci_cpld,
i2c_type_24c02,
i2c_type_qci_pmbus_ix1,
i2c_type_quanta_ix1_hwmon,
};
char *i2c_type_names[] = {
"spd",
"ds1339",
"pca9546",
"pca9548",
"pca9554",
"pca9555",
"pca9698",
"CPLD-QSFP28",
"24c02",
"qci_pmbus_ix1",
"quanta_ix1_hwmon",
};
struct i2c_init_data {
int parent_bus;
int type;
int addr;
int busno;
int gpio_base;
char name[I2C_NAME_SIZE];
};
static struct i2c_init_data quanta_ix1_i2c_init_data[] = {
{ .parent_bus = (0x00 + 0), .type = i2c_type_pca9546, .addr = 0x71, .busno = 0x02, .name = "PCA9546(CPU)\0" },
{ .parent_bus = (0x02 + 0), .type = i2c_type_pca9555, .addr = 0x20, .gpio_base = 0x40, .name = "PCA9555_1(CPU)\0" },
{ .parent_bus = (0x00 + 0), .type = i2c_type_quanta_ix1_hwmon, .addr = 0x4e, .name = "PSoc\0" },
{ .parent_bus = (0x00 + 0), .type = i2c_type_spd, .addr = 0x52, .name = "SPD(DDR3-SODIMM0)\0" },
{ .parent_bus = (0x00 + 0), .type = i2c_type_spd, .addr = 0x53, .name = "SPD(DDR3-SODIMM1)\0" },
{ .parent_bus = (0x00 + 0), .type = i2c_type_pca9546, .addr = 0x77, .busno = 0x10, .name = "PCA9546_1\0" },
{ .parent_bus = (0x10 + 0), .type = i2c_type_pca9548, .addr = 0x73, .busno = 0x20, .name = "PCA9548_1\0" },
{ .parent_bus = (0x10 + 0), .type = i2c_type_pca9548, .addr = 0x74, .busno = 0x28, .name = "PCA9548_2\0" },
{ .parent_bus = (0x10 + 0), .type = i2c_type_pca9548, .addr = 0x75, .busno = 0x30, .name = "PCA9548_3\0" },
{ .parent_bus = (0x10 + 1), .type = i2c_type_pca9548, .addr = 0x76, .busno = 0x38, .name = "PCA9548_4\0" },
{ .parent_bus = (0x10 + 0), .type = i2c_type_qci_cpld, .addr = 0x38, .name = "qci_cpld1\0" },
{ .parent_bus = (0x10 + 0), .type = i2c_type_qci_cpld, .addr = 0x39, .name = "qci_cpld2\0" },
{ .parent_bus = (0x20 + 0), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_1_EEPROM\0" },
{ .parent_bus = (0x20 + 1), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_2_EEPROM\0" },
{ .parent_bus = (0x20 + 2), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_3_EEPROM\0" },
{ .parent_bus = (0x20 + 3), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_4_EEPROM\0" },
{ .parent_bus = (0x20 + 4), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_5_EEPROM\0" },
{ .parent_bus = (0x20 + 5), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_6_EEPROM\0" },
{ .parent_bus = (0x20 + 6), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_7_EEPROM\0" },
{ .parent_bus = (0x20 + 7), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_8_EEPROM\0" },
{ .parent_bus = (0x28 + 0), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_9_EEPROM\0" },
{ .parent_bus = (0x28 + 1), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_10_EEPROM\0" },
{ .parent_bus = (0x28 + 2), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_11_EEPROM\0" },
{ .parent_bus = (0x28 + 3), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_12_EEPROM\0" },
{ .parent_bus = (0x28 + 4), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_13_EEPROM\0" },
{ .parent_bus = (0x28 + 5), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_14_EEPROM\0" },
{ .parent_bus = (0x28 + 6), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_15_EEPROM\0" },
{ .parent_bus = (0x28 + 7), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_16_EEPROM\0" },
{ .parent_bus = (0x30 + 0), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_17_EEPROM\0" },
{ .parent_bus = (0x30 + 1), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_18_EEPROM\0" },
{ .parent_bus = (0x30 + 2), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_19_EEPROM\0" },
{ .parent_bus = (0x30 + 3), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_20_EEPROM\0" },
{ .parent_bus = (0x30 + 4), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_21_EEPROM\0" },
{ .parent_bus = (0x30 + 5), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_22_EEPROM\0" },
{ .parent_bus = (0x30 + 6), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_23_EEPROM\0" },
{ .parent_bus = (0x30 + 7), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_24_EEPROM\0" },
{ .parent_bus = (0x38 + 0), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_25_EEPROM\0" },
{ .parent_bus = (0x38 + 1), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_26_EEPROM\0" },
{ .parent_bus = (0x38 + 2), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_27_EEPROM\0" },
{ .parent_bus = (0x38 + 3), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_28_EEPROM\0" },
{ .parent_bus = (0x38 + 4), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_29_EEPROM\0" },
{ .parent_bus = (0x38 + 5), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_30_EEPROM\0" },
{ .parent_bus = (0x38 + 6), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_31_EEPROM\0" },
{ .parent_bus = (0x38 + 7), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_32_EEPROM\0" },
{ .parent_bus = (0x00 + 0), .type = i2c_type_pca9546, .addr = 0x72, .busno = 0x18, .name = "PCA9546_2\0" },
{ .parent_bus = (0x18 + 0), .type = i2c_type_qci_pmbus_ix1, .addr = 0x5f, .name = "PSU_1\0" },
{ .parent_bus = (0x18 + 1), .type = i2c_type_qci_pmbus_ix1, .addr = 0x59, .name = "PSU_2\0" },
{ .parent_bus = (0x18 + 2), .type = i2c_type_pca9555, .addr = 0x26, .gpio_base = 0x10, .name = "PCA9555-1(PSU)\0" },
{ .parent_bus = (0x18 + 2), .type = i2c_type_24c02, .addr = 0x54, .name = "Board_EEPROM\0" },
{ .parent_bus = (0x18 + 2), .type = i2c_type_pca9555, .addr = 0x23, .name = "PCA9555-2(Board ID)\0" },
{ .parent_bus = (0x18 + 3), .type = i2c_type_pca9555, .addr = 0x25, .name = "PCA9555-3(FAN IO)\0" },
};
static inline struct pca954x_platform_data *pca954x_platform_data_get(int type, int busno) {
static struct pca954x_platform_mode platform_modes[8];
static struct pca954x_platform_data platform_data;
int num_modes, i;
switch(type) {
case i2c_type_pca9546:
num_modes = 4;
break;
case i2c_type_pca9548:
num_modes = 8;
break;
default:
return (struct pca954x_platform_data *) NULL;
break;
}
for(i=0;i<num_modes;i++) {
platform_modes[i] = (struct pca954x_platform_mode) {
.adap_id = (busno + i),
.deselect_on_exit = 1,
};
}
platform_data = (struct pca954x_platform_data) {
.modes = platform_modes,
.num_modes = num_modes,
};
return &platform_data;
}
static int base_gpio_num = I2C_GPIO_BASE;
static inline struct pca953x_platform_data *pca953x_platform_data_get(int type, int gpio_base) {
static struct pca953x_platform_data platform_data;
int num_gpios, num_gpio;
switch(type) {
case i2c_type_pca9554:
num_gpios = 0x8;
break;
case i2c_type_pca9555:
num_gpios = 0x10;
break;
case i2c_type_pca9698:
num_gpios = 0x28;
break;
default:
return (struct pca953x_platform_data *) NULL;
break;
}
if(gpio_base == 0) {
num_gpio = base_gpio_num;
base_gpio_num += num_gpios;
}
else {
num_gpio = gpio_base;
}
platform_data = (struct pca953x_platform_data) {
.gpio_base = num_gpio,
};
return &platform_data;
}
static inline struct i2c_board_info *i2c_board_info_get(struct i2c_init_data data) {
struct pca954x_platform_data *mux_platform_data;
struct pca953x_platform_data *gpio_platform_data;
static struct i2c_board_info board_info;
switch(data.type) {
case i2c_type_pca9546:
case i2c_type_pca9548:
mux_platform_data = pca954x_platform_data_get(data.type, data.busno);
if(mux_platform_data == NULL) {
return (struct i2c_board_info *) NULL;
}
board_info = (struct i2c_board_info) {
.platform_data = mux_platform_data,
};
break;
case i2c_type_pca9554:
case i2c_type_pca9555:
case i2c_type_pca9698:
gpio_platform_data = pca953x_platform_data_get(data.type, data.gpio_base);
if(gpio_platform_data == NULL) {
return (struct i2c_board_info *) NULL;
}
board_info = (struct i2c_board_info) {
.platform_data = gpio_platform_data,
};
break;
case i2c_type_rtc:
case i2c_type_spd:
case i2c_type_24c02:
case i2c_type_qci_pmbus_ix1:
case i2c_type_quanta_ix1_hwmon:
case i2c_type_qci_cpld:
board_info = (struct i2c_board_info) {
.platform_data = (void *) NULL,
};
break;
default:
return (struct i2c_board_info *) NULL;
break;
}
board_info.addr = data.addr;
strcpy(board_info.type, i2c_type_names[data.type]);
return &board_info;
}
static struct platform_driver quanta_platfom_ix1_platform_driver = {
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
},
};
static struct i2c_init_data *init_data;
static int init_data_size;
static struct i2c_client *registered_i2c_clients[MAX_I2C_CLIENTS];
static int __init quanta_platfom_ix1_init(void)
{
char const *vendor, *product;
struct i2c_adapter *adapter;
struct i2c_board_info *board_info;
int i;
int ret = 0;
vendor = dmi_get_system_info(DMI_SYS_VENDOR);
product = dmi_get_system_info(DMI_PRODUCT_NAME);
init_data = quanta_ix1_i2c_init_data;
init_data_size = ARRAY_SIZE(quanta_ix1_i2c_init_data);
ret = platform_driver_register(&quanta_platfom_ix1_platform_driver);
if (ret < 0)
return ret;
/**
* Register I2C devices on new buses
*/
for(i = 0; i < init_data_size; i++) {
adapter = i2c_get_adapter(init_data[i].parent_bus);
board_info = i2c_board_info_get(init_data[i]);
pr_info("register i2c_new_device\n\t%s for bus 0x%x:0x%x. ",
init_data[i].name, init_data[i].parent_bus, init_data[i].addr);
if((registered_i2c_clients[i] = i2c_new_device(adapter, board_info)) == NULL) {
pr_err("%s: i2c_new_device for bus 0x%x:0x%x failed.",
__FUNCTION__, init_data[i].parent_bus, init_data[i].addr);
}
}
return 0;
}
static void __exit quanta_platfom_ix1_cleanup(void)
{
int i;
/**
* Unregister I2C devices
*/
for(i = 0; i < init_data_size; i++) {
if(registered_i2c_clients[i] != NULL) {
i2c_unregister_device(registered_i2c_clients[init_data_size-(i+1)]);
}
}
platform_driver_unregister(&quanta_platfom_ix1_platform_driver);
}
module_init(quanta_platfom_ix1_init);
module_exit(quanta_platfom_ix1_cleanup);
MODULE_AUTHOR("Jonathan Tsai (jonathan.tsai@quantatw.com)");
MODULE_VERSION("1.0");
MODULE_DESCRIPTION("Quanta Platform IX1");
MODULE_LICENSE("GPL");

1
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/Makefile Executable file
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include $(ONL)/make/pkg.mk

1
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/PKG.yml Executable file
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!include $ONL_TEMPLATES/onlp-platform-any.yml PLATFORM=x86-64-quanta-ix1-rangeley ARCH=amd64 TOOLCHAIN=x86_64-linux-gnu

2
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/Makefile Executable file
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FILTER=src
include $(ONL)/make/subdirs.mk

45
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/lib/Makefile Executable file
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############################################################
# <bsn.cl fy=2014 v=onl>
#
# Copyright 2014 BigSwitch Networks, Inc.
#
# Licensed under the Eclipse Public License, Version 1.0 (the
# "License"); you may not use this file except in compliance
# with the License. You may obtain a copy of the License at
#
# http://www.eclipse.org/legal/epl-v10.html
#
# Unless required by applicable law or agreed to in writing,
# software distributed under the License is distributed on an
# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
# either express or implied. See the License for the specific
# language governing permissions and limitations under the
# License.
#
# </bsn.cl>
############################################################
#
#
############################################################
include $(ONL)/make/config.amd64.mk
MODULE := libonlp-x86-64-quanta-ix1-rangeley
include $(BUILDER)/standardinit.mk
DEPENDMODULES := AIM IOF x86_64_quanta_ix1_rangeley quanta_sys_eeprom onlplib
DEPENDMODULE_HEADERS := sff
include $(BUILDER)/dependmodules.mk
SHAREDLIB := libonlp-x86-64-quanta-ix1-rangeley.so
$(SHAREDLIB)_TARGETS := $(ALL_TARGETS)
include $(BUILDER)/so.mk
.DEFAULT_GOAL := $(SHAREDLIB)
GLOBAL_CFLAGS += -I$(onlp_BASEDIR)/module/inc
GLOBAL_CFLAGS += -DAIM_CONFIG_INCLUDE_MODULES_INIT=1
GLOBAL_CFLAGS += -fPIC
GLOBAL_LINK_LIBS += -lpthread
include $(BUILDER)/targets.mk

45
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/onlpdump/Makefile Executable file
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@@ -0,0 +1,45 @@
############################################################
# <bsn.cl fy=2014 v=onl>
#
# Copyright 2014 BigSwitch Networks, Inc.
#
# Licensed under the Eclipse Public License, Version 1.0 (the
# "License"); you may not use this file except in compliance
# with the License. You may obtain a copy of the License at
#
# http://www.eclipse.org/legal/epl-v10.html
#
# Unless required by applicable law or agreed to in writing,
# software distributed under the License is distributed on an
# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
# either express or implied. See the License for the specific
# language governing permissions and limitations under the
# License.
#
# </bsn.cl>
############################################################
#
#
#
############################################################
include $(ONL)/make/config.amd64.mk
.DEFAULT_GOAL := onlpdump
MODULE := onlpdump
include $(BUILDER)/standardinit.mk
DEPENDMODULES := AIM IOF onlp x86_64_quanta_ix1_rangeley quanta_sys_eeprom onlplib onlp_platform_defaults sff cjson cjson_util timer_wheel OS
include $(BUILDER)/dependmodules.mk
BINARY := onlpdump
$(BINARY)_LIBRARIES := $(LIBRARY_TARGETS)
include $(BUILDER)/bin.mk
GLOBAL_CFLAGS += -DAIM_CONFIG_AIM_MAIN_FUNCTION=onlpdump_main
GLOBAL_CFLAGS += -DAIM_CONFIG_INCLUDE_MODULES_INIT=1
GLOBAL_CFLAGS += -DAIM_CONFIG_INCLUDE_MAIN=1
GLOBAL_LINK_LIBS += -lpthread -lm
include $(BUILDER)/targets.mk

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name: x86_64_quanta_ix1_rangeley

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###############################################################################
#
#
#
###############################################################################
include $(ONL)/make/config.mk
MODULE := x86_64_quanta_ix1_rangeley
AUTOMODULE := x86_64_quanta_ix1_rangeley
include $(BUILDER)/definemodule.mk

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###############################################################################
#
# x86_64_quanta_ix1_rangeley Autogeneration
#
###############################################################################
x86_64_quanta_ix1_rangeley_AUTO_DEFS := module/auto/x86_64_quanta_ix1_rangeley.yml
x86_64_quanta_ix1_rangeley_AUTO_DIRS := module/inc/x86_64_quanta_ix1_rangeley module/src
include $(BUILDER)/auto.mk

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###############################################################################
#
# x86_64_quanta_ix1_rangeley Autogeneration Definitions.
#
###############################################################################
cdefs: &cdefs
- X86_64_QUANTA_IX1_RANGELEY_CONFIG_INCLUDE_LOGGING:
doc: "Include or exclude logging."
default: 1
- X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_OPTIONS_DEFAULT:
doc: "Default enabled log options."
default: AIM_LOG_OPTIONS_DEFAULT
- X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_BITS_DEFAULT:
doc: "Default enabled log bits."
default: AIM_LOG_BITS_DEFAULT
- X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_CUSTOM_BITS_DEFAULT:
doc: "Default enabled custom log bits."
default: 0
- X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_STDLIB:
doc: "Default all porting macros to use the C standard libraries."
default: 1
- X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS:
doc: "Include standard library headers for stdlib porting macros."
default: X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_STDLIB
- X86_64_QUANTA_IX1_RANGELEY_CONFIG_INCLUDE_UCLI:
doc: "Include generic uCli support."
default: 0
- X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_RPM_FAILURE_THRESHOLD:
doc: "RPM Threshold at which the fan is considered to have failed."
default: 3000
- X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_F2B_RPM_MAX:
doc: "Maximum system front-to-back fan speed."
default: 18000
- X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_B2F_RPM_MAX:
doc: "Maximum system back-to-front fan speed."
default: 18000
- X86_64_QUANTA_IX1_RANGELEY_CONFIG_PHY_RESET_DELAY_MS:
doc: "Time to hold Phy GPIO in reset, in ms"
default: 100
definitions:
cdefs:
X86_64_QUANTA_IX1_RANGELEY_CONFIG_HEADER:
defs: *cdefs
basename: x86_64_quanta_ix1_rangeley_config
enum: &enums
fan_id:
members:
- FAN1 : 1
- FAN2 : 2
- FAN3 : 3
- FAN4 : 4
- FAN5 : 5
- FAN6 : 6
- FAN7 : 7
- FAN8 : 8
- FAN9 : 9
- FAN10 : 10
fan_oid:
members:
- FAN1 : ONLP_FAN_ID_CREATE(1)
- FAN2 : ONLP_FAN_ID_CREATE(2)
- FAN3 : ONLP_FAN_ID_CREATE(3)
- FAN4 : ONLP_FAN_ID_CREATE(4)
- FAN5 : ONLP_FAN_ID_CREATE(5)
- FAN6 : ONLP_FAN_ID_CREATE(6)
- FAN7 : ONLP_FAN_ID_CREATE(7)
- FAN8 : ONLP_FAN_ID_CREATE(8)
- FAN9 : ONLP_FAN_ID_CREATE(9)
- FAN10 : ONLP_FAN_ID_CREATE(10)
psu_id:
members:
- PSU1 : 1
- PSU2 : 2
psu_oid:
members:
- PSU1 : ONLP_PSU_ID_CREATE(1)
- PSU2 : ONLP_PSU_ID_CREATE(2)
thermal_id:
members:
- THERMAL1 : 1
- THERMAL2 : 2
- THERMAL3 : 3
- THERMAL4 : 4
- THERMAL5 : 5
- THERMAL6 : 6
- THERMAL7 : 7
- THERMAL8 : 8
- THERMAL9 : 9
- THERMAL10 : 10
- THERMAL11 : 11
- THERMAL12 : 12
- THERMAL13 : 13
- THERMAL14 : 14
- THERMAL15 : 15
- THERMAL16 : 16
thermal_oid:
members:
- THERMAL1 : ONLP_THERMAL_ID_CREATE(1)
- THERMAL2 : ONLP_THERMAL_ID_CREATE(2)
- THERMAL3 : ONLP_THERMAL_ID_CREATE(3)
- THERMAL4 : ONLP_THERMAL_ID_CREATE(4)
- THERMAL5 : ONLP_THERMAL_ID_CREATE(5)
- THERMAL6 : ONLP_THERMAL_ID_CREATE(6)
- THERMAL7 : ONLP_THERMAL_ID_CREATE(7)
- THERMAL8 : ONLP_THERMAL_ID_CREATE(8)
- THERMAL9 : ONLP_THERMAL_ID_CREATE(9)
- THERMAL10 : ONLP_THERMAL_ID_CREATE(10)
- THERMAL11 : ONLP_THERMAL_ID_CREATE(11)
- THERMAL12 : ONLP_THERMAL_ID_CREATE(12)
- THERMAL13 : ONLP_THERMAL_ID_CREATE(13)
- THERMAL14 : ONLP_THERMAL_ID_CREATE(14)
- THERMAL15 : ONLP_THERMAL_ID_CREATE(15)
- THERMAL16 : ONLP_THERMAL_ID_CREATE(16)
portingmacro:
X86_64_QUANTA_IX1_RANGELEY:
macros:
- memset
- memcpy
- strncpy
- vsnprintf
- snprintf
- strlen

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/**************************************************************************//**
*
*
*
*****************************************************************************/
#include <x86_64_quanta_ix1_rangeley/x86_64_quanta_ix1_rangeley_config.h>
/* <--auto.start.xmacro(ALL).define> */
/* <auto.end.xmacro(ALL).define> */
/* <--auto.start.xenum(ALL).define> */
/* <auto.end.xenum(ALL).define> */

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/**************************************************************************//**
*
* @file
* @brief x86_64_quanta_ix1_rangeley Configuration Header
*
* @addtogroup x86_64_quanta_ix1_rangeley-config
* @{
*
*****************************************************************************/
#ifndef __X86_64_QUANTA_IX1_RANGELEY_CONFIG_H__
#define __X86_64_QUANTA_IX1_RANGELEY_CONFIG_H__
#ifdef GLOBAL_INCLUDE_CUSTOM_CONFIG
#include <global_custom_config.h>
#endif
#ifdef X86_64_QUANTA_IX1_RANGELEY_INCLUDE_CUSTOM_CONFIG
#include <x86_64_quanta_ix1_rangeley_custom_config.h>
#endif
/* <auto.start.cdefs(X86_64_QUANTA_IX1_RANGELEY_CONFIG_HEADER).header> */
#include <AIM/aim.h>
/**
* X86_64_QUANTA_IX1_RANGELEY_CONFIG_INCLUDE_LOGGING
*
* Include or exclude logging. */
#ifndef X86_64_QUANTA_IX1_RANGELEY_CONFIG_INCLUDE_LOGGING
#define X86_64_QUANTA_IX1_RANGELEY_CONFIG_INCLUDE_LOGGING 1
#endif
/**
* X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_OPTIONS_DEFAULT
*
* Default enabled log options. */
#ifndef X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_OPTIONS_DEFAULT
#define X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_OPTIONS_DEFAULT AIM_LOG_OPTIONS_DEFAULT
#endif
/**
* X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_BITS_DEFAULT
*
* Default enabled log bits. */
#ifndef X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_BITS_DEFAULT
#define X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_BITS_DEFAULT AIM_LOG_BITS_DEFAULT
#endif
/**
* X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_CUSTOM_BITS_DEFAULT
*
* Default enabled custom log bits. */
#ifndef X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_CUSTOM_BITS_DEFAULT
#define X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_CUSTOM_BITS_DEFAULT 0
#endif
/**
* X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_STDLIB
*
* Default all porting macros to use the C standard libraries. */
#ifndef X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_STDLIB
#define X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_STDLIB 1
#endif
/**
* X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS
*
* Include standard library headers for stdlib porting macros. */
#ifndef X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS
#define X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_STDLIB
#endif
/**
* X86_64_QUANTA_IX1_RANGELEY_CONFIG_INCLUDE_UCLI
*
* Include generic uCli support. */
#ifndef X86_64_QUANTA_IX1_RANGELEY_CONFIG_INCLUDE_UCLI
#define X86_64_QUANTA_IX1_RANGELEY_CONFIG_INCLUDE_UCLI 0
#endif
/**
* X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_RPM_FAILURE_THRESHOLD
*
* RPM Threshold at which the fan is considered to have failed. */
#ifndef X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_RPM_FAILURE_THRESHOLD
#define X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_RPM_FAILURE_THRESHOLD 3000
#endif
/**
* X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_F2B_RPM_MAX
*
* Maximum system front-to-back fan speed. */
#ifndef X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_F2B_RPM_MAX
#define X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_F2B_RPM_MAX 18000
#endif
/**
* X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_B2F_RPM_MAX
*
* Maximum system back-to-front fan speed. */
#ifndef X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_B2F_RPM_MAX
#define X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_B2F_RPM_MAX 18000
#endif
/**
* X86_64_QUANTA_IX1_RANGELEY_CONFIG_PHY_RESET_DELAY_MS
*
* Time to hold Phy GPIO in reset, in ms */
#ifndef X86_64_QUANTA_IX1_RANGELEY_CONFIG_PHY_RESET_DELAY_MS
#define X86_64_QUANTA_IX1_RANGELEY_CONFIG_PHY_RESET_DELAY_MS 100
#endif
/**
* All compile time options can be queried or displayed
*/
/** Configuration settings structure. */
typedef struct x86_64_quanta_ix1_rangeley_config_settings_s {
/** name */
const char* name;
/** value */
const char* value;
} x86_64_quanta_ix1_rangeley_config_settings_t;
/** Configuration settings table. */
/** x86_64_quanta_ix1_rangeley_config_settings table. */
extern x86_64_quanta_ix1_rangeley_config_settings_t x86_64_quanta_ix1_rangeley_config_settings[];
/**
* @brief Lookup a configuration setting.
* @param setting The name of the configuration option to lookup.
*/
const char* x86_64_quanta_ix1_rangeley_config_lookup(const char* setting);
/**
* @brief Show the compile-time configuration.
* @param pvs The output stream.
*/
int x86_64_quanta_ix1_rangeley_config_show(struct aim_pvs_s* pvs);
/* <auto.end.cdefs(X86_64_QUANTA_IX1_RANGELEY_CONFIG_HEADER).header> */
#include "x86_64_quanta_ix1_rangeley_porting.h"
#endif /* __X86_64_QUANTA_IX1_RANGELEY_CONFIG_H__ */
/* @} */

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/**************************************************************************//**
*
* x86_64_quanta_ix1_rangeley Doxygen Header
*
*****************************************************************************/
#ifndef __X86_64_QUANTA_IX1_RANGELEY_DOX_H__
#define __X86_64_QUANTA_IX1_RANGELEY_DOX_H__
/**
* @defgroup x86_64_quanta_ix1_rangeley x86_64_quanta_ix1_rangeley - x86_64_quanta_ix1_rangeley Description
*
The documentation overview for this module should go here.
*
* @{
*
* @defgroup x86_64_quanta_ix1_rangeley-x86_64_quanta_ix1_rangeley Public Interface
* @defgroup x86_64_quanta_ix1_rangeley-config Compile Time Configuration
* @defgroup x86_64_quanta_ix1_rangeley-porting Porting Macros
*
* @}
*
*/
#endif /* __X86_64_QUANTA_IX1_RANGELEY_DOX_H__ */

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#ifndef __X86_64_QUANTA_IX1_RANGELEY_GPIO_TABLE_H__
#define __X86_64_QUANTA_IX1_RANGELEY_GPIO_TABLE_H__
/*
* defined within platform/quanta_switch.c
* Quanta Switch Platform driver
*/
#define QUANTA_IX1_PCA953x_GPIO(P1, P2) (P1*8+P2)
#define QUANTA_IX1_PCA9555_GPIO_SIZE 0x10
#define QUANTA_IX1_I2C_GPIO_BASE 0x80
#define QUANTA_IX1_I2C_GPIO_CPU_BASE 0x40
#define QUANTA_IX1_CPU_BOARD_GPIO_BASE (QUANTA_IX1_I2C_GPIO_CPU_BASE)
#define QUANTA_IX1_CPU_BOARD_SYS_P1 (QUANTA_IX1_CPU_BOARD_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(1,2))
#define QUANTA_IX1_CPU_BOARD_SYS_P2 (QUANTA_IX1_CPU_BOARD_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(1,3))
#define QUANTA_IX1_PSU_GPIO_BASE 0x10
#define QUANTA_IX1_PSU_GPIO_SIZE QUANTA_IX1_PCA9555_GPIO_SIZE
#define QUANTA_IX1_PSU_GPIO_PSU1_PRSNT_N (QUANTA_IX1_PSU_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(0,0))
#define QUANTA_IX1_PSU_GPIO_PSU1_PWRGD (QUANTA_IX1_PSU_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(0,1))
#define QUANTA_IX1_PSU_GPIO_PSU2_PRSNT_N (QUANTA_IX1_PSU_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(0,3))
#define QUANTA_IX1_PSU_GPIO_PSU2_PWRGD (QUANTA_IX1_PSU_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(0,4))
#define QUANTA_IX1_PSU_GPIO_PSU1_AC_OK (QUANTA_IX1_PSU_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(0,6))
#define QUANTA_IX1_PSU_GPIO_PSU2_AC_OK (QUANTA_IX1_PSU_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(0,7))
#define QUANTA_IX1_PSU_GPIO_PSU1_GREEN_R (QUANTA_IX1_PSU_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(1,2))
#define QUANTA_IX1_PSU_GPIO_PSU1_RED_R (QUANTA_IX1_PSU_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(1,3))
#define QUANTA_IX1_PSU_GPIO_PSU2_GREEN_R (QUANTA_IX1_PSU_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(1,4))
#define QUANTA_IX1_PSU_GPIO_PSU2_RED_R (QUANTA_IX1_PSU_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(1,5))
#define QUANTA_IX1_PSU_GPIO_FAN_GREEN_R (QUANTA_IX1_PSU_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(1,6))
#define QUANTA_IX1_PSU_GPIO_FAN_RED_R (QUANTA_IX1_PSU_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(1,7))
#define QUANTA_IX1_ZQSFP_EN_GPIO_BASE QUANTA_IX1_I2C_GPIO_BASE
#define QUANTA_IX1_ZQSFP_EN_GPIO_SIZE QUANTA_IX1_PCA9555_GPIO_SIZE
#define QUANTA_IX1_ZQSFP_EN_GPIO_P3V3_PW_GD (QUANTA_IX1_ZQSFP_EN_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(0,4))
#define QUANTA_IX1_ZQSFP_EN_GPIO_P3V3_PW_EN (QUANTA_IX1_ZQSFP_EN_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(0,5))
#define QUANTA_IX1_FAN_GPIO_BASE (QUANTA_IX1_ZQSFP_EN_GPIO_BASE + QUANTA_IX1_ZQSFP_EN_GPIO_SIZE)
#define QUANTA_IX1_FAN_GPIO_SIZE QUANTA_IX1_PCA9555_GPIO_SIZE
#define QUANTA_IX1_FAN_PRSNT_N_1 (QUANTA_IX1_FAN_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(0,4))
#define QUANTA_IX1_FAN_PRSNT_N_2 (QUANTA_IX1_FAN_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(0,5))
#define QUANTA_IX1_FAN_PRSNT_N_3 (QUANTA_IX1_FAN_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(0,6))
#define QUANTA_IX1_FAN_PRSNT_N_4 (QUANTA_IX1_FAN_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(0,7))
#define QUANTA_IX1_FAN_BF_DET1 (QUANTA_IX1_FAN_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(1,0))
#define QUANTA_IX1_FAN_BF_DET2 (QUANTA_IX1_FAN_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(1,1))
#define QUANTA_IX1_FAN_BF_DET3 (QUANTA_IX1_FAN_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(1,2))
#define QUANTA_IX1_FAN_BF_DET4 (QUANTA_IX1_FAN_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(1,3))
#define QUANTA_IX1_FAN_FAIL_LED_1 (QUANTA_IX1_FAN_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(1,4))
#define QUANTA_IX1_FAN_FAIL_LED_2 (QUANTA_IX1_FAN_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(1,5))
#define QUANTA_IX1_FAN_FAIL_LED_3 (QUANTA_IX1_FAN_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(1,6))
#define QUANTA_IX1_FAN_FAIL_LED_4 (QUANTA_IX1_FAN_GPIO_BASE + QUANTA_IX1_PCA953x_GPIO(1,7))
#endif /* __X86_64_QUANTA_IX1_RANGELEY_GPIO_TABLE_H__ */

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/**************************************************************************//**
*
* @file
* @brief x86_64_quanta_ix1_rangeley Porting Macros.
*
* @addtogroup x86_64_quanta_ix1_rangeley-porting
* @{
*
*****************************************************************************/
#ifndef __X86_64_QUANTA_IX1_RANGELEY_PORTING_H__
#define __X86_64_QUANTA_IX1_RANGELEY_PORTING_H__
/* <auto.start.portingmacro(ALL).define> */
#if X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS == 1
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdarg.h>
#include <memory.h>
#endif
#ifndef X86_64_QUANTA_IX1_RANGELEY_MEMSET
#if defined(GLOBAL_MEMSET)
#define X86_64_QUANTA_IX1_RANGELEY_MEMSET GLOBAL_MEMSET
#elif X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_STDLIB == 1
#define X86_64_QUANTA_IX1_RANGELEY_MEMSET memset
#else
#error The macro X86_64_QUANTA_IX1_RANGELEY_MEMSET is required but cannot be defined.
#endif
#endif
#ifndef X86_64_QUANTA_IX1_RANGELEY_MEMCPY
#if defined(GLOBAL_MEMCPY)
#define X86_64_QUANTA_IX1_RANGELEY_MEMCPY GLOBAL_MEMCPY
#elif X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_STDLIB == 1
#define X86_64_QUANTA_IX1_RANGELEY_MEMCPY memcpy
#else
#error The macro X86_64_QUANTA_IX1_RANGELEY_MEMCPY is required but cannot be defined.
#endif
#endif
#ifndef X86_64_QUANTA_IX1_RANGELEY_STRNCPY
#if defined(GLOBAL_STRNCPY)
#define X86_64_QUANTA_IX1_RANGELEY_STRNCPY GLOBAL_STRNCPY
#elif X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_STDLIB == 1
#define X86_64_QUANTA_IX1_RANGELEY_STRNCPY strncpy
#else
#error The macro X86_64_QUANTA_IX1_RANGELEY_STRNCPY is required but cannot be defined.
#endif
#endif
#ifndef X86_64_QUANTA_IX1_RANGELEY_VSNPRINTF
#if defined(GLOBAL_VSNPRINTF)
#define X86_64_QUANTA_IX1_RANGELEY_VSNPRINTF GLOBAL_VSNPRINTF
#elif X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_STDLIB == 1
#define X86_64_QUANTA_IX1_RANGELEY_VSNPRINTF vsnprintf
#else
#error The macro X86_64_QUANTA_IX1_RANGELEY_VSNPRINTF is required but cannot be defined.
#endif
#endif
#ifndef X86_64_QUANTA_IX1_RANGELEY_SNPRINTF
#if defined(GLOBAL_SNPRINTF)
#define X86_64_QUANTA_IX1_RANGELEY_SNPRINTF GLOBAL_SNPRINTF
#elif X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_STDLIB == 1
#define X86_64_QUANTA_IX1_RANGELEY_SNPRINTF snprintf
#else
#error The macro X86_64_QUANTA_IX1_RANGELEY_SNPRINTF is required but cannot be defined.
#endif
#endif
#ifndef X86_64_QUANTA_IX1_RANGELEY_STRLEN
#if defined(GLOBAL_STRLEN)
#define X86_64_QUANTA_IX1_RANGELEY_STRLEN GLOBAL_STRLEN
#elif X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_STDLIB == 1
#define X86_64_QUANTA_IX1_RANGELEY_STRLEN strlen
#else
#error The macro X86_64_QUANTA_IX1_RANGELEY_STRLEN is required but cannot be defined.
#endif
#endif
/* <auto.end.portingmacro(ALL).define> */
#endif /* __X86_64_QUANTA_IX1_RANGELEY_PORTING_H__ */
/* @} */

10
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/make.mk Executable file
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###############################################################################
#
#
#
###############################################################################
THIS_DIR := $(dir $(lastword $(MAKEFILE_LIST)))
x86_64_quanta_ix1_rangeley_INCLUDES := -I $(THIS_DIR)inc
x86_64_quanta_ix1_rangeley_INTERNAL_INCLUDES := -I $(THIS_DIR)src
x86_64_quanta_ix1_rangeley_DEPENDMODULE_ENTRIES := init:x86_64_quanta_ix1_rangeley ucli:x86_64_quanta_ix1_rangeley

9
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/Makefile Executable file
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@@ -0,0 +1,9 @@
###############################################################################
#
# Local source generation targets.
#
###############################################################################
ucli:
@../../../../tools/uclihandlers.py x86_64_quanta_ix1_rangeley_ucli.c

172
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/fani.c Executable file
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/************************************************************
* <bsn.cl fy=2014 v=onl>
*
* Copyright 2014 Big Switch Networks, Inc.
*
* Licensed under the Eclipse Public License, Version 1.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.eclipse.org/legal/epl-v10.html
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the
* License.
*
* </bsn.cl>
************************************************************
*
*
*
***********************************************************/
#include <x86_64_quanta_ix1_rangeley/x86_64_quanta_ix1_rangeley_config.h>
#include <x86_64_quanta_ix1_rangeley/x86_64_quanta_ix1_rangeley_gpio_table.h>
#include <onlp/platformi/fani.h>
#include "x86_64_quanta_ix1_rangeley_int.h"
#include "x86_64_quanta_ix1_rangeley_log.h"
#include <onlplib/file.h>
#include <onlplib/gpio.h>
int
onlp_fani_init(void)
{
return ONLP_STATUS_OK;
}
struct fan_gpio_s {
int present;
int fan_dir_detect;
};
static struct fan_gpio_s fan_gpio[] = {
{}, /* Not used */
{ .present = QUANTA_IX1_FAN_PRSNT_N_1, .fan_dir_detect = QUANTA_IX1_FAN_BF_DET1 },
{ .present = QUANTA_IX1_FAN_PRSNT_N_2, .fan_dir_detect = QUANTA_IX1_FAN_BF_DET2 },
{ .present = QUANTA_IX1_FAN_PRSNT_N_3, .fan_dir_detect = QUANTA_IX1_FAN_BF_DET3 },
{ .present = QUANTA_IX1_FAN_PRSNT_N_4, .fan_dir_detect = QUANTA_IX1_FAN_BF_DET4 },
//{}, /* Not used */
{ .present = QUANTA_IX1_FAN_PRSNT_N_1, .fan_dir_detect = QUANTA_IX1_FAN_BF_DET1 },
{ .present = QUANTA_IX1_FAN_PRSNT_N_2, .fan_dir_detect = QUANTA_IX1_FAN_BF_DET2 },
{ .present = QUANTA_IX1_FAN_PRSNT_N_3, .fan_dir_detect = QUANTA_IX1_FAN_BF_DET3 },
{ .present = QUANTA_IX1_FAN_PRSNT_N_4, .fan_dir_detect = QUANTA_IX1_FAN_BF_DET4 },
//{}, /* Not used */
};
static int
sys_fan_info_get__(onlp_fan_info_t* info, int id)
{
int value = 0;
int rv;
if(onlp_gpio_get(fan_gpio[id].present, &value) == ONLP_STATUS_OK
&& value == 0) {
info->status = ONLP_FAN_STATUS_PRESENT;
if(onlp_gpio_get(fan_gpio[id].fan_dir_detect, &value) == ONLP_STATUS_OK
&& value == 0) {
info->status |= ONLP_FAN_STATUS_F2B;
info->caps |= ONLP_FAN_CAPS_F2B;
}
else {
info->status |= ONLP_FAN_STATUS_B2F;
info->caps |= ONLP_FAN_CAPS_B2F;
}
}
else {
info->status = ONLP_FAN_STATUS_FAILED;
}
rv = onlp_file_read_int(&info->rpm,
SYS_HWMON_PREFIX "/fan%d_input", id);
if(rv == ONLP_STATUS_E_INTERNAL) {
return rv;
}
if(rv == ONLP_STATUS_E_MISSING) {
info->status &= ~1;
return 0;
}
if(info->rpm <= X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_RPM_FAILURE_THRESHOLD) {
info->status |= ONLP_FAN_STATUS_FAILED;
}
/*
* Calculate percentage based on current speed and the maximum.
*/
info->caps |= ONLP_FAN_CAPS_GET_PERCENTAGE;
if(info->status & ONLP_FAN_STATUS_F2B) {
info->percentage = (int) ((double) info->rpm * (double)100 / (double)X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_F2B_RPM_MAX);
}
if(info->status & ONLP_FAN_STATUS_B2F) {
info->percentage = (int) ((double) info->rpm * (double)100 / (double)X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_B2F_RPM_MAX);
}
return 0;
}
static int
psu_fan_info_get__(onlp_fan_info_t* info, int id)
{
extern struct psu_info_s psu_info[];
char* dir = psu_info[id].path;
return onlp_file_read_int(&info->rpm, "%s*fan1_input", dir);
}
/* Onboard Fans */
static onlp_fan_info_t fans__[] = {
{ }, /* Not used */
{ { FAN_OID_FAN1, "Left (Module/Fan 1/1)", 0}, ONLP_FAN_STATUS_PRESENT },
{ { FAN_OID_FAN2, "Center-L(Module/Fan 2/1)", 0}, ONLP_FAN_STATUS_PRESENT },
{ { FAN_OID_FAN3, "Center-R(Module/Fan 3/1)", 0}, ONLP_FAN_STATUS_PRESENT },
{ { FAN_OID_FAN4, "Right (Module/Fan 4/1)", 0}, ONLP_FAN_STATUS_PRESENT },
{ { FAN_OID_FAN5, "Left (Module/Fan 1/2)", 0}, ONLP_FAN_STATUS_PRESENT },
{ { FAN_OID_FAN6, "Center-L(Module/Fan 2/2)", 0}, ONLP_FAN_STATUS_PRESENT },
{ { FAN_OID_FAN7, "Center-R(Module/Fan 3/2)", 0}, ONLP_FAN_STATUS_PRESENT },
{ { FAN_OID_FAN8, "Right (Module/Fan 4/2)", 0}, ONLP_FAN_STATUS_PRESENT },
{ { FAN_OID_FAN9, "PSU-1 Fan", 0 }, ONLP_FAN_STATUS_PRESENT },
{ { FAN_OID_FAN10, "PSU-2 Fan", 0 }, ONLP_FAN_STATUS_PRESENT },
};
int
onlp_fani_info_get(onlp_oid_t id, onlp_fan_info_t* rv)
{
int fid = ONLP_OID_ID_GET(id);
*rv = fans__[ONLP_OID_ID_GET(id)];
rv->caps |= ONLP_FAN_CAPS_GET_RPM;
switch(fid) {
case FAN_ID_FAN1:
case FAN_ID_FAN2:
case FAN_ID_FAN3:
case FAN_ID_FAN4:
case FAN_ID_FAN5:
case FAN_ID_FAN6:
case FAN_ID_FAN7:
case FAN_ID_FAN8:
return sys_fan_info_get__(rv, fid);
break;
case FAN_ID_FAN9:
case FAN_ID_FAN10:
return psu_fan_info_get__(rv, fid - FAN_ID_FAN9 + 1);
break;
default:
return ONLP_STATUS_E_INVALID;
break;
}
return ONLP_STATUS_E_INVALID;
}

229
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/ledi.c Executable file
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#include <onlp/platformi/ledi.h>
#include <sys/mman.h>
#include <stdio.h>
#include <string.h>
#include <fcntl.h>
#include "x86_64_quanta_ix1_rangeley_int.h"
#include <x86_64_quanta_ix1_rangeley/x86_64_quanta_ix1_rangeley_gpio_table.h>
#include <onlplib/gpio.h>
/*
* Get the information for the given LED OID.
*/
static onlp_led_info_t led_info[] =
{
{ }, /* Not used */
{
{ LED_OID_SYSTEM, "System LED", 0 },
ONLP_LED_STATUS_PRESENT,
ONLP_LED_CAPS_ON_OFF | ONLP_LED_CAPS_ORANGE | ONLP_LED_CAPS_GREEN,
},
{
{ LED_OID_FAN, "Front FAN LED", 0 },
ONLP_LED_STATUS_PRESENT,
ONLP_LED_CAPS_ON_OFF | ONLP_LED_CAPS_RED | ONLP_LED_CAPS_GREEN,
},
{
{ LED_OID_PSU_1, "Front PSU(1) LED", 0 },
ONLP_LED_STATUS_PRESENT,
ONLP_LED_CAPS_ON_OFF | ONLP_LED_CAPS_RED | ONLP_LED_CAPS_GREEN,
},
{
{ LED_OID_PSU_2, "Front PSU(2) LED", 0 },
ONLP_LED_STATUS_PRESENT,
ONLP_LED_CAPS_ON_OFF | ONLP_LED_CAPS_RED | ONLP_LED_CAPS_GREEN,
},
{
{ LED_OID_FAN_FAIL_1, "FAN(1) fail LED", 0 },
ONLP_LED_STATUS_PRESENT,
ONLP_LED_CAPS_ON_OFF | ONLP_LED_CAPS_RED,
},
{
{ LED_OID_FAN_FAIL_2, "FAN(2) fail LED", 0 },
ONLP_LED_STATUS_PRESENT,
ONLP_LED_CAPS_ON_OFF | ONLP_LED_CAPS_RED,
},
{
{ LED_OID_FAN_FAIL_3, "FAN(3) fail LED", 0 },
ONLP_LED_STATUS_PRESENT,
ONLP_LED_CAPS_ON_OFF | ONLP_LED_CAPS_RED,
},
{
{ LED_OID_FAN_FAIL_4, "FAN(4) fail LED", 0 },
ONLP_LED_STATUS_PRESENT,
ONLP_LED_CAPS_ON_OFF | ONLP_LED_CAPS_RED,
}
};
int
onlp_ledi_init(void)
{
return ONLP_STATUS_OK;
}
int
onlp_ledi_info_get(onlp_oid_t id, onlp_led_info_t* info)
{
int led_id;
led_id = ONLP_OID_ID_GET(id);
*info = led_info[led_id];
info->status |= ONLP_LED_STATUS_ON;
info->mode |= ONLP_LED_MODE_ON;
return ONLP_STATUS_OK;
}
void
Sysfs_Set_System_LED(onlp_led_mode_t mode)
{
if(mode == ONLP_LED_MODE_GREEN){
onlp_gpio_set(QUANTA_IX1_CPU_BOARD_SYS_P1, 0);
onlp_gpio_set(QUANTA_IX1_CPU_BOARD_SYS_P2, 1);
}
else if(mode == ONLP_LED_MODE_ORANGE){
onlp_gpio_set(QUANTA_IX1_CPU_BOARD_SYS_P1, 1);
onlp_gpio_set(QUANTA_IX1_CPU_BOARD_SYS_P2, 0);
}
else{
onlp_gpio_set(QUANTA_IX1_CPU_BOARD_SYS_P1, 1);
onlp_gpio_set(QUANTA_IX1_CPU_BOARD_SYS_P2, 1);
}
}
void
Sysfs_Set_Fan_LED(onlp_led_mode_t mode)
{
if(mode == ONLP_LED_MODE_GREEN){
onlp_gpio_set(QUANTA_IX1_PSU_GPIO_FAN_GREEN_R, 1);
onlp_gpio_set(QUANTA_IX1_PSU_GPIO_FAN_RED_R, 0);
}
else if(mode == ONLP_LED_MODE_RED){
onlp_gpio_set(QUANTA_IX1_PSU_GPIO_FAN_GREEN_R, 0);
onlp_gpio_set(QUANTA_IX1_PSU_GPIO_FAN_RED_R, 1);
}
else{
onlp_gpio_set(QUANTA_IX1_PSU_GPIO_FAN_GREEN_R, 0);
onlp_gpio_set(QUANTA_IX1_PSU_GPIO_FAN_RED_R, 0);
}
}
void
Sysfs_Set_Psu1_LED(onlp_led_mode_t mode)
{
if(mode == ONLP_LED_MODE_GREEN){
onlp_gpio_set(QUANTA_IX1_PSU_GPIO_PSU1_GREEN_R, 1);
onlp_gpio_set(QUANTA_IX1_PSU_GPIO_PSU1_RED_R, 0);
}
else if(mode == ONLP_LED_MODE_RED){
onlp_gpio_set(QUANTA_IX1_PSU_GPIO_PSU1_GREEN_R, 0);
onlp_gpio_set(QUANTA_IX1_PSU_GPIO_PSU1_RED_R, 1);
}
else{
onlp_gpio_set(QUANTA_IX1_PSU_GPIO_PSU1_GREEN_R, 0);
onlp_gpio_set(QUANTA_IX1_PSU_GPIO_PSU1_RED_R, 0);
}
}
void
Sysfs_Set_Psu2_LED(onlp_led_mode_t mode)
{
if(mode == ONLP_LED_MODE_GREEN){
onlp_gpio_set(QUANTA_IX1_PSU_GPIO_PSU2_GREEN_R, 1);
onlp_gpio_set(QUANTA_IX1_PSU_GPIO_PSU2_RED_R, 0);
}
else if(mode == ONLP_LED_MODE_RED){
onlp_gpio_set(QUANTA_IX1_PSU_GPIO_PSU2_GREEN_R, 0);
onlp_gpio_set(QUANTA_IX1_PSU_GPIO_PSU2_RED_R, 1);
}
else{
onlp_gpio_set(QUANTA_IX1_PSU_GPIO_PSU2_GREEN_R, 0);
onlp_gpio_set(QUANTA_IX1_PSU_GPIO_PSU2_RED_R, 0);
}
}
void
Sysfs_Set_Fan_Fail1_LED(onlp_led_mode_t mode)
{
if(mode == ONLP_LED_MODE_RED){
onlp_gpio_set(QUANTA_IX1_FAN_FAIL_LED_1, 1);
}
else{
onlp_gpio_set(QUANTA_IX1_FAN_FAIL_LED_1, 0);
}
}
void
Sysfs_Set_Fan_Fail2_LED(onlp_led_mode_t mode)
{
if(mode == ONLP_LED_MODE_RED){
onlp_gpio_set(QUANTA_IX1_FAN_FAIL_LED_2, 1);
}
else{
onlp_gpio_set(QUANTA_IX1_FAN_FAIL_LED_2, 0);
}
}
void
Sysfs_Set_Fan_Fail3_LED(onlp_led_mode_t mode)
{
if(mode == ONLP_LED_MODE_RED){
onlp_gpio_set(QUANTA_IX1_FAN_FAIL_LED_3, 1);
}
else{
onlp_gpio_set(QUANTA_IX1_FAN_FAIL_LED_3, 0);
}
}
void
Sysfs_Set_Fan_Fail4_LED(onlp_led_mode_t mode)
{
if(mode == ONLP_LED_MODE_RED){
onlp_gpio_set(QUANTA_IX1_FAN_FAIL_LED_4, 1);
}
else{
onlp_gpio_set(QUANTA_IX1_FAN_FAIL_LED_4, 0);
}
}
int
onlp_ledi_mode_set(onlp_oid_t id, onlp_led_mode_t mode)
{
int led_id;
led_id = ONLP_OID_ID_GET(id);
switch (led_id) {
case LED_ID_SYSTEM:
Sysfs_Set_System_LED(mode);
break;
case LED_ID_FAN:
Sysfs_Set_Fan_LED(mode);
break;
case LED_ID_PSU_1:
Sysfs_Set_Psu1_LED(mode);
break;
case LED_ID_PSU_2:
Sysfs_Set_Psu2_LED(mode);
break;
case LED_ID_FAN_FAIL_1:
Sysfs_Set_Fan_Fail1_LED(mode);
break;
case LED_ID_FAN_FAIL_2:
Sysfs_Set_Fan_Fail2_LED(mode);
break;
case LED_ID_FAN_FAIL_3:
Sysfs_Set_Fan_Fail3_LED(mode);
break;
case LED_ID_FAN_FAIL_4:
Sysfs_Set_Fan_Fail4_LED(mode);
break;
default:
return ONLP_STATUS_E_INTERNAL;
break;
}
return ONLP_STATUS_OK;
}

9
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/make.mk Executable file
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###############################################################################
#
#
#
###############################################################################
LIBRARY := x86_64_quanta_ix1_rangeley
$(LIBRARY)_SUBDIR := $(dir $(lastword $(MAKEFILE_LIST)))
include $(BUILDER)/lib.mk

119
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/psui.c Executable file
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/************************************************************
* <bsn.cl fy=2014 v=onl>
* </bsn.cl>
************************************************************
*
*
*
***********************************************************/
#include <x86_64_quanta_ix1_rangeley/x86_64_quanta_ix1_rangeley_config.h>
#include <x86_64_quanta_ix1_rangeley/x86_64_quanta_ix1_rangeley_gpio_table.h>
#include <onlp/platformi/psui.h>
#include <onlplib/file.h>
#include <onlplib/gpio.h>
#include "x86_64_quanta_ix1_rangeley_int.h"
#include "x86_64_quanta_ix1_rangeley_log.h"
#include <AIM/aim_string.h>
struct psu_info_s psu_info[] = {
{}, /* Not used */
{ .path = "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-24/24-005f", .present = QUANTA_IX1_PSU_GPIO_PSU1_PRSNT_N, .busno = 24, .addr = 0x5f},
{ .path = "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-25/25-0059", .present = QUANTA_IX1_PSU_GPIO_PSU2_PRSNT_N, .busno = 25, .addr = 0x59},
};
int
onlp_psui_init(void)
{
return 0;
}
static onlp_psu_info_t psus__[] = {
{ }, /* Not used */
{
{
PSU_OID_PSU1,
"Quanta IX1 RPSU-1",
0,
{
FAN_OID_FAN9,
},
}
},
{
{
PSU_OID_PSU2,
"Quanta IX1 RPSU-2",
0,
{
FAN_OID_FAN10,
},
}
},
};
#define PMBUS_MFR_MODEL 0x9A
#define PMBUS_MFR_SERIAL 0x9E
#define PMBUS_MFR_MODEL_LEN 20
#define PMBUS_MFR_SERIAL_LEN 19
int
onlp_psui_info_get(onlp_oid_t id, onlp_psu_info_t* info)
{
int rv;
int pid = ONLP_OID_ID_GET(id);
*info = psus__[pid];
const char* dir = psu_info[pid].path;
unsigned char buffer[ONLP_CONFIG_INFO_STR_MAX];
int value = -1, len;
rv = onlp_gpio_get(psu_info[pid].present, &value);
if(rv < 0) {
return rv;
}
else if(value == 1) {
info->status &= ~1;
return 0;
}
if(onlp_file_read_int(&info->mvin, "%s*in1_input", dir) == 0 && info->mvin >= 0) {
info->caps |= ONLP_PSU_CAPS_VIN;
}
/* PSU is present and powered. */
info->status |= 1;
len = PMBUS_MFR_MODEL_LEN;
if(onlp_file_read(buffer, sizeof(buffer), &len, "%s*mfr_model", dir) != 0){
AIM_LOG_ERROR("Read PMBUS_MFR_MODEL ###ERROR###");;
}
aim_strlcpy(info->model, (char *) buffer, 16);
len = PMBUS_MFR_SERIAL_LEN;
if(onlp_file_read(buffer, sizeof(buffer), &len, "%s*mfr_serial", dir) != 0){
AIM_LOG_ERROR("Read PMBUS_MFR_SERIAL ###ERROR###");;
}
aim_strlcpy(info->serial, (char *) buffer, 14);
info->caps |= ONLP_PSU_CAPS_AC;
if(onlp_file_read_int(&info->miin, "%s*curr1_input", dir) == 0 && info->miin >= 0) {
info->caps |= ONLP_PSU_CAPS_IIN;
}
if(onlp_file_read_int(&info->miout, "%s*curr2_input", dir) == 0 && info->miout >= 0) {
info->caps |= ONLP_PSU_CAPS_IOUT;
}
if(onlp_file_read_int(&info->mvout, "%s*in2_input", dir) == 0 && info->mvout >= 0) {
info->caps |= ONLP_PSU_CAPS_VOUT;
}
if(onlp_file_read_int(&info->mpin, "%s*power1_input", dir) == 0 && info->mpin >= 0) {
info->caps |= ONLP_PSU_CAPS_PIN;
/* The pmbus driver reports power in micro-units */
info->mpin /= 1000;
}
if(onlp_file_read_int(&info->mpout, "%s*power2_input", dir) == 0 && info->mpout >= 0) {
info->caps |= ONLP_PSU_CAPS_POUT;
/* the pmbus driver reports power in micro-units */
info->mpout /= 1000;
}
return ONLP_STATUS_OK;
}

134
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/sfpi.c Executable file
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/************************************************************
* <bsn.cl fy=2014 v=onl>
*
* Copyright 2014 Big Switch Networks, Inc.
*
* Licensed under the Eclipse Public License, Version 1.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.eclipse.org/legal/epl-v10.html
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the
* License.
*
* </bsn.cl>
************************************************************
*
* SFPI Interface for the Quanta IX1
*
***********************************************************/
#include <x86_64_quanta_ix1_rangeley/x86_64_quanta_ix1_rangeley_config.h>
#include <x86_64_quanta_ix1_rangeley/x86_64_quanta_ix1_rangeley_gpio_table.h>
#include <onlp/platformi/sfpi.h>
#include <onlplib/sfp.h>
#include <onlplib/gpio.h>
#include "x86_64_quanta_ix1_rangeley_log.h"
#include <unistd.h>
#include <fcntl.h>
/**
* This table maps the presence gpio, reset gpio, and eeprom file
* for each SFP port.
*/
typedef struct sfpmap_s {
int port;
const char* present_cpld;
const char* reset_gpio;
const char* eeprom;
const char* dom;
} sfpmap_t;
static sfpmap_t sfpmap__[] =
{
{ 1, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-1/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-32/32-0050/eeprom", NULL },
{ 2, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-2/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-33/33-0050/eeprom", NULL },
{ 3, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-3/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-34/34-0050/eeprom", NULL },
{ 4, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-4/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-35/35-0050/eeprom", NULL },
{ 5, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-5/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-36/36-0050/eeprom", NULL },
{ 6, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-6/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-37/37-0050/eeprom", NULL },
{ 7, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-7/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-38/38-0050/eeprom", NULL },
{ 8, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-8/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-39/39-0050/eeprom", NULL },
{ 9, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-9/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-40/40-0050/eeprom", NULL },
{ 10, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-10/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-41/41-0050/eeprom", NULL },
{ 11, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-11/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-42/42-0050/eeprom", NULL },
{ 12, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-12/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-43/43-0050/eeprom", NULL },
{ 13, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-13/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-44/44-0050/eeprom", NULL },
{ 14, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-14/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-45/45-0050/eeprom", NULL },
{ 15, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-15/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-46/46-0050/eeprom", NULL },
{ 16, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-16/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-47/47-0050/eeprom", NULL },
{ 17, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-17/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-48/48-0050/eeprom", NULL },
{ 18, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-18/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-49/49-0050/eeprom", NULL },
{ 19, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-19/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-50/50-0050/eeprom", NULL },
{ 20, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-20/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-51/51-0050/eeprom", NULL },
{ 21, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-21/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-52/52-0050/eeprom", NULL },
{ 22, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-22/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-53/53-0050/eeprom", NULL },
{ 23, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-23/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-54/54-0050/eeprom", NULL },
{ 24, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-24/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-55/55-0050/eeprom", NULL },
{ 25, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-25/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-56/56-0050/eeprom", NULL },
{ 26, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-26/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-57/57-0050/eeprom", NULL },
{ 27, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-27/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-58/58-0050/eeprom", NULL },
{ 28, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-28/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-59/59-0050/eeprom", NULL },
{ 29, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-29/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-60/60-0050/eeprom", NULL },
{ 30, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-30/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-61/61-0050/eeprom", NULL },
{ 31, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-31/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-62/62-0050/eeprom", NULL },
{ 32, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-32/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-63/63-0050/eeprom", NULL },
};
int
onlp_sfpi_init(void)
{
int value = -1, ret;
onlp_gpio_export(QUANTA_IX1_ZQSFP_EN_GPIO_P3V3_PW_EN, ONLP_GPIO_DIRECTION_IN);
ret = onlp_gpio_get(QUANTA_IX1_ZQSFP_EN_GPIO_P3V3_PW_EN, &value);
if(ret == ONLP_STATUS_OK && value != 1) {
onlp_gpio_export(QUANTA_IX1_ZQSFP_EN_GPIO_P3V3_PW_EN, ONLP_GPIO_DIRECTION_OUT);
ret = onlp_gpio_set(QUANTA_IX1_ZQSFP_EN_GPIO_P3V3_PW_EN, 1);
sleep(1);
}
return ret;
}
int
onlp_sfpi_bitmap_get(onlp_sfp_bitmap_t* bmap)
{
int p;
for(p = 1; p < 33; p++) {
AIM_BITMAP_SET(bmap, p);
}
return ONLP_STATUS_OK;
}
#define SFP_GET(_port) (sfpmap__ + _port - 1)
int
onlp_sfpi_is_present(int port)
{
sfpmap_t* sfp = SFP_GET(port);
return onlplib_sfp_is_present_file(sfp->present_cpld, /* Present */ "1\n", /* Absent */ "0\n");
}
int
onlp_sfpi_eeprom_read(int port, uint8_t data[256])
{
sfpmap_t* sfp = SFP_GET(port);
return onlplib_sfp_eeprom_read_file(sfp->eeprom, data);
}
int
onlp_sfpi_dom_read(int port, uint8_t data[256])
{
sfpmap_t* sfp = SFP_GET(port);
return onlplib_sfp_eeprom_read_file(sfp->dom, data);
}

287
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/sysi.c Executable file
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@@ -0,0 +1,287 @@
/************************************************************
* <bsn.cl fy=2014 v=onl>
* </bsn.cl>
************************************************************
*
*
*
***********************************************************/
#include <onlp/platformi/sysi.h>
#include "x86_64_quanta_ix1_rangeley_int.h"
#include "x86_64_quanta_ix1_rangeley_log.h"
#include <quanta_sys_eeprom/eeprom.h>
#include <x86_64_quanta_ix1_rangeley/x86_64_quanta_ix1_rangeley_gpio_table.h>
#include <onlplib/gpio.h>
#include <onlplib/i2c.h>
#include <onlp/platformi/ledi.h>
struct led_control_s led_control;
#define QUANTA_HWMON_REG_TEMP_ALERT_MASK 0x1E
#define QUANTA_HWMON_REG_TEMP_ALERT_CTRL 0x1D
#define QUANTA_HWMON_REG_FAN_ALERT_MASK 0x31
#define QUANTA_HWMON_REG_FAN_ALERT_CTRL 0x30
#define PSOC_REG_FAN_ALERT_STATUS 0x32
#define QUANTA_FAN_1_1 0x01
#define QUANTA_FAN_1_2 0x10
#define QUANTA_FAN_2_1 0x02
#define QUANTA_FAN_2_2 0x20
#define QUANTA_FAN_3_1 0x04
#define QUANTA_FAN_3_2 0x40
#define QUANTA_FAN_4_1 0x08
#define QUANTA_FAN_4_2 0x80
const char*
onlp_sysi_platform_get(void)
{
return "x86-64-quanta-ix1-rangeley-r0";
}
int
onlp_sysi_init(void)
{
/* Initial value */
led_control.PMCnt = 0;
led_control.fan_alert = 0xff;
led_control.psu1_present = 0;
led_control.psu2_present = 0;
led_control.psu1_power_good = 0;
led_control.psu2_power_good = 0;
/* Set PSoc Fan-Alert Enable */
onlp_i2c_writeb(0, 0x4e, QUANTA_HWMON_REG_TEMP_ALERT_MASK, 0x37, ONLP_I2C_F_FORCE);
onlp_i2c_writeb(0, 0x4e, QUANTA_HWMON_REG_TEMP_ALERT_CTRL, 0x3, ONLP_I2C_F_FORCE);
onlp_i2c_writeb(0, 0x4e, QUANTA_HWMON_REG_FAN_ALERT_MASK, 0xff, ONLP_I2C_F_FORCE);
onlp_i2c_writeb(0, 0x4e, QUANTA_HWMON_REG_FAN_ALERT_CTRL, 0x1, ONLP_I2C_F_FORCE);
/* Config GPIO */
/* LED Output */
onlp_gpio_export(QUANTA_IX1_CPU_BOARD_SYS_P1, ONLP_GPIO_DIRECTION_OUT);
onlp_gpio_export(QUANTA_IX1_CPU_BOARD_SYS_P2, ONLP_GPIO_DIRECTION_OUT);
onlp_gpio_export(QUANTA_IX1_PSU_GPIO_PSU1_GREEN_R, ONLP_GPIO_DIRECTION_OUT);
onlp_gpio_export(QUANTA_IX1_PSU_GPIO_PSU1_RED_R, ONLP_GPIO_DIRECTION_OUT);
onlp_gpio_export(QUANTA_IX1_PSU_GPIO_PSU2_GREEN_R, ONLP_GPIO_DIRECTION_OUT);
onlp_gpio_export(QUANTA_IX1_PSU_GPIO_PSU2_RED_R, ONLP_GPIO_DIRECTION_OUT);
onlp_gpio_export(QUANTA_IX1_FAN_FAIL_LED_1, ONLP_GPIO_DIRECTION_OUT);
onlp_gpio_export(QUANTA_IX1_FAN_FAIL_LED_2, ONLP_GPIO_DIRECTION_OUT);
onlp_gpio_export(QUANTA_IX1_FAN_FAIL_LED_3, ONLP_GPIO_DIRECTION_OUT);
onlp_gpio_export(QUANTA_IX1_FAN_FAIL_LED_4, ONLP_GPIO_DIRECTION_OUT);
onlp_gpio_export(QUANTA_IX1_PSU_GPIO_FAN_GREEN_R, ONLP_GPIO_DIRECTION_OUT);
onlp_gpio_export(QUANTA_IX1_PSU_GPIO_FAN_RED_R, ONLP_GPIO_DIRECTION_OUT);
/* PSU Input */
onlp_gpio_export(QUANTA_IX1_PSU_GPIO_PSU1_PRSNT_N, ONLP_GPIO_DIRECTION_IN);
onlp_gpio_export(QUANTA_IX1_PSU_GPIO_PSU1_PWRGD, ONLP_GPIO_DIRECTION_IN);
onlp_gpio_export(QUANTA_IX1_PSU_GPIO_PSU2_PRSNT_N, ONLP_GPIO_DIRECTION_IN);
onlp_gpio_export(QUANTA_IX1_PSU_GPIO_PSU2_PWRGD, ONLP_GPIO_DIRECTION_IN);
/* FAN Input */
onlp_gpio_export(QUANTA_IX1_FAN_PRSNT_N_1, ONLP_GPIO_DIRECTION_IN);
onlp_gpio_export(QUANTA_IX1_FAN_PRSNT_N_2, ONLP_GPIO_DIRECTION_IN);
onlp_gpio_export(QUANTA_IX1_FAN_PRSNT_N_3, ONLP_GPIO_DIRECTION_IN);
onlp_gpio_export(QUANTA_IX1_FAN_PRSNT_N_4, ONLP_GPIO_DIRECTION_IN);
/* Set LED to green */
onlp_ledi_mode_set(LED_OID_SYSTEM, ONLP_LED_MODE_GREEN);
led_control.psu_status_changed = 1;
led_control.fan_status_changed = 1;
onlp_sysi_platform_manage_leds();
return ONLP_STATUS_OK;
}
#define QUANTA_SYS_EEPROM_PATH \
"/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-26/26-0054/eeprom"
int
onlp_sysi_onie_info_get(onlp_onie_info_t* onie)
{
int rv;
rv = onlp_onie_decode_file(onie, QUANTA_SYS_EEPROM_PATH);
if(rv >= 0) {
onie->platform_name = aim_strdup("x86-64-quanta-ix1-rangeley-r0");
rv = quanta_onie_sys_eeprom_custom_format(onie);
}
return rv;
}
int
onlp_sysi_oids_get(onlp_oid_t* table, int max)
{
onlp_oid_t* e = table;
memset(table, 0, max*sizeof(onlp_oid_t));
/*
* 5 Chassis Thermal Sensors
*/
*e++ = THERMAL_OID_THERMAL1;
*e++ = THERMAL_OID_THERMAL2;
*e++ = THERMAL_OID_THERMAL3;
*e++ = THERMAL_OID_THERMAL5;
*e++ = THERMAL_OID_THERMAL6;
/*
* 8 Fans
*/
*e++ = FAN_OID_FAN1;
*e++ = FAN_OID_FAN2;
*e++ = FAN_OID_FAN3;
*e++ = FAN_OID_FAN4;
*e++ = FAN_OID_FAN5;
*e++ = FAN_OID_FAN6;
*e++ = FAN_OID_FAN7;
*e++ = FAN_OID_FAN8;
/*
* 2 PSUs
*/
*e++ = PSU_OID_PSU1;
*e++ = PSU_OID_PSU2;
/*
* 8 LEDs
*/
*e++ = LED_OID_SYSTEM;
*e++ = LED_OID_FAN;
*e++ = LED_OID_PSU_1;
*e++ = LED_OID_PSU_2;
*e++ = LED_OID_FAN_FAIL_1;
*e++ = LED_OID_FAN_FAIL_2;
*e++ = LED_OID_FAN_FAIL_3;
*e++ = LED_OID_FAN_FAIL_4;
return 0;
}
int
update_rpsu_fan_status(void){
int last_status, rv, value = -1, tmp;
last_status = led_control.psu1_present;
rv = onlp_gpio_get(QUANTA_IX1_PSU_GPIO_PSU1_PRSNT_N, &value);
if(rv < 0) {
AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_IX1_PSU_GPIO_PSU1_PRSNT_N);
return rv;
}
led_control.psu1_present = (value ? 0 : 1);
if(last_status != led_control.psu1_present)
led_control.psu_status_changed = 1;
last_status = led_control.psu1_power_good;
rv = onlp_gpio_get(QUANTA_IX1_PSU_GPIO_PSU1_PWRGD, &value);
if(rv < 0) {
AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_IX1_PSU_GPIO_PSU1_PWRGD);
return rv;
}
led_control.psu1_power_good = (value ? 1 : 0);
if(last_status != led_control.psu1_power_good)
led_control.psu_status_changed = 1;
last_status = led_control.psu2_present;
rv = onlp_gpio_get(QUANTA_IX1_PSU_GPIO_PSU2_PRSNT_N, &value);
if(rv < 0) {
AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_IX1_PSU_GPIO_PSU2_PRSNT_N);
return rv;
}
led_control.psu2_present = (value ? 0 : 1);
if(last_status != led_control.psu2_present)
led_control.psu_status_changed = 1;
last_status = led_control.psu2_power_good;
rv = onlp_gpio_get(QUANTA_IX1_PSU_GPIO_PSU2_PWRGD, &value);
if(rv < 0) {
AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_IX1_PSU_GPIO_PSU2_PWRGD);
return rv;
}
led_control.psu2_power_good = (value ? 1 : 0);
if(last_status != led_control.psu2_power_good)
led_control.psu_status_changed = 1;
tmp = led_control.fan_alert;
led_control.fan_alert = onlp_i2c_readb(0, 0x4e, PSOC_REG_FAN_ALERT_STATUS, ONLP_I2C_F_FORCE);
if(tmp != led_control.fan_alert)
led_control.fan_status_changed = 1;
return ONLP_STATUS_OK;
}
int
onlp_sysi_platform_manage_leds(void)
{
int rv;
led_control.PMCnt++;
if(led_control.PMCnt>300)
led_control.PMCnt = 0;
if(led_control.PMCnt % 5 == 1){/* Each 10 seconds detect one time */
rv = update_rpsu_fan_status();
if(rv < 0){
printf("onlp_sysi_platform_manage_leds error\n");
return ONLP_STATUS_E_INVALID;
}
if(led_control.psu_status_changed){
if(led_control.psu1_present && led_control.psu1_power_good) {
onlp_ledi_mode_set(LED_ID_PSU_1, ONLP_LED_MODE_GREEN);
}
else if(!led_control.psu1_present){
onlp_ledi_mode_set(LED_ID_PSU_1, ONLP_LED_MODE_OFF);
}
else{
onlp_ledi_mode_set(LED_ID_PSU_1, ONLP_LED_MODE_RED);
}
if(led_control.psu2_present && led_control.psu2_power_good) {
onlp_ledi_mode_set(LED_ID_PSU_2, ONLP_LED_MODE_GREEN);
}
else if(!led_control.psu2_present){
onlp_ledi_mode_set(LED_ID_PSU_2, ONLP_LED_MODE_OFF);
}
else{
onlp_ledi_mode_set(LED_ID_PSU_2, ONLP_LED_MODE_RED);
}
led_control.psu_status_changed = 0;
}
if(led_control.fan_status_changed){
if(!(led_control.fan_alert & QUANTA_FAN_1_1) && !(led_control.fan_alert & QUANTA_FAN_1_2)) {
onlp_ledi_mode_set(LED_ID_FAN_FAIL_1, ONLP_LED_MODE_OFF);
}
else{
onlp_ledi_mode_set(LED_ID_FAN_FAIL_1, ONLP_LED_MODE_RED);
}
if(!(led_control.fan_alert & QUANTA_FAN_2_1) && !(led_control.fan_alert & QUANTA_FAN_2_2)) {
onlp_ledi_mode_set(LED_ID_FAN_FAIL_2, ONLP_LED_MODE_OFF);
}
else{
onlp_ledi_mode_set(LED_ID_FAN_FAIL_2, ONLP_LED_MODE_RED);
}
if(!(led_control.fan_alert & QUANTA_FAN_3_1) && !(led_control.fan_alert & QUANTA_FAN_3_2)) {
onlp_ledi_mode_set(LED_ID_FAN_FAIL_3, ONLP_LED_MODE_OFF);
}
else{
onlp_ledi_mode_set(LED_ID_FAN_FAIL_3, ONLP_LED_MODE_RED);
}
if(!(led_control.fan_alert & QUANTA_FAN_4_1) && !(led_control.fan_alert & QUANTA_FAN_4_2)) {
onlp_ledi_mode_set(LED_ID_FAN_FAIL_4, ONLP_LED_MODE_OFF);
}
else{
onlp_ledi_mode_set(LED_ID_FAN_FAIL_4, ONLP_LED_MODE_RED);
}
if(!led_control.fan_alert){
onlp_ledi_mode_set(LED_ID_FAN, ONLP_LED_MODE_GREEN);
}
else{
onlp_ledi_mode_set(LED_ID_FAN, ONLP_LED_MODE_RED);
}
led_control.fan_status_changed = 0;
}
}
return ONLP_STATUS_OK;
}

146
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/thermali.c Executable file
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/************************************************************
* <bsn.cl fy=2014 v=onl>
*
* Copyright 2014 Big Switch Networks, Inc.
*
* Licensed under the Eclipse Public License, Version 1.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.eclipse.org/legal/epl-v10.html
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the
* License.
*
* </bsn.cl>
************************************************************
*
*
*
***********************************************************/
#include <onlp/platformi/thermali.h>
#include <onlplib/file.h>
#include "x86_64_quanta_ix1_rangeley_int.h"
#include "x86_64_quanta_ix1_rangeley_log.h"
int
onlp_thermali_init(void)
{
return ONLP_STATUS_OK;
}
static int
sys_thermal_info_get__(onlp_thermal_info_t* info, int id)
{
int rv;
rv = onlp_file_read_int(&info->mcelsius,
SYS_HWMON_PREFIX "/temp%d_input", id);
if(rv == ONLP_STATUS_E_INTERNAL) {
return rv;
}
if(rv == ONLP_STATUS_E_MISSING) {
info->status &= ~1;
return 0;
}
return ONLP_STATUS_OK;
}
static int
psu_thermal_info_get__(onlp_thermal_info_t* info, int pid, int id)
{
/* THERMAL6 -> PSU1 */
/* THERMAL7 -> PSU2 */
extern struct psu_info_s psu_info[];
char* dir = psu_info[pid].path;
info->status |= 1;
return onlp_file_read_int(&info->mcelsius, "%s/temp%d_input", dir, id);
}
int
onlp_thermali_info_get(onlp_oid_t id, onlp_thermal_info_t* rv)
{
int tid = ONLP_OID_ID_GET(id);
static onlp_thermal_info_t info[] = {
{ }, /* Not used */
{ { ONLP_THERMAL_ID_CREATE(1), "Chassis Thermal 1", 0}, ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
},
{ { ONLP_THERMAL_ID_CREATE(2), "Chassis Thermal 2", 0}, ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
},
{ { ONLP_THERMAL_ID_CREATE(3), "Chassis Thermal 3", 0}, ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
},
{ { ONLP_THERMAL_ID_CREATE(4), "Chassis Thermal 4", 0}, ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
},
{ { ONLP_THERMAL_ID_CREATE(5), "Chassis Thermal 5", 0}, ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
},
{ { ONLP_THERMAL_ID_CREATE(6), "Chassis Thermal 6", 0}, ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
},
{ { ONLP_THERMAL_ID_CREATE(7), "Chassis Thermal 7", 0}, ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
},
{ { ONLP_THERMAL_ID_CREATE(8), "Chassis Thermal 8", 0}, ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
},
{ { ONLP_THERMAL_ID_CREATE(9), "Chassis Thermal 9", 0}, ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
},
{ { ONLP_THERMAL_ID_CREATE(10), "Chassis Thermal 10", 0}, ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
},
{ { ONLP_THERMAL_ID_CREATE(11), "PSU-1 Thermal 1", 0 } },
{ { ONLP_THERMAL_ID_CREATE(12), "PSU-1 Thermal 2", 0 } },
{ { ONLP_THERMAL_ID_CREATE(13), "PSU-1 Thermal 3", 0 } },
{ { ONLP_THERMAL_ID_CREATE(14), "PSU-2 Thermal 1", 0 } },
{ { ONLP_THERMAL_ID_CREATE(15), "PSU-2 Thermal 2", 0 } },
{ { ONLP_THERMAL_ID_CREATE(16), "PSU-2 Thermal 3", 0 } },
};
*rv = info[tid];
rv->caps |= ONLP_THERMAL_CAPS_GET_TEMPERATURE;
switch(tid)
{
case THERMAL_ID_THERMAL1:
case THERMAL_ID_THERMAL2:
case THERMAL_ID_THERMAL3:
case THERMAL_ID_THERMAL4:
case THERMAL_ID_THERMAL5:
case THERMAL_ID_THERMAL6:
case THERMAL_ID_THERMAL7:
case THERMAL_ID_THERMAL8:
case THERMAL_ID_THERMAL9:
case THERMAL_ID_THERMAL10:
return sys_thermal_info_get__(rv, tid);
case THERMAL_ID_THERMAL11:
case THERMAL_ID_THERMAL12:
case THERMAL_ID_THERMAL13:
return psu_thermal_info_get__(rv, 1, tid - THERMAL_ID_THERMAL11 + 1);
case THERMAL_ID_THERMAL14:
case THERMAL_ID_THERMAL15:
case THERMAL_ID_THERMAL16:
return psu_thermal_info_get__(rv, 2, tid - THERMAL_ID_THERMAL14 + 1);
}
return ONLP_STATUS_E_INVALID;
}

95
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/x86_64_quanta_ix1_rangeley_config.c Executable file
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/**************************************************************************//**
*
*
*
*****************************************************************************/
#include <x86_64_quanta_ix1_rangeley/x86_64_quanta_ix1_rangeley_config.h>
/* <auto.start.cdefs(X86_64_QUANTA_IX1_RANGELEY_CONFIG_HEADER).source> */
#define __x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME(_x) #_x
#define __x86_64_quanta_ix1_rangeley_config_STRINGIFY_VALUE(_x) __x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME(_x)
x86_64_quanta_ix1_rangeley_config_settings_t x86_64_quanta_ix1_rangeley_config_settings[] =
{
#ifdef X86_64_QUANTA_IX1_RANGELEY_CONFIG_INCLUDE_LOGGING
{ __x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX1_RANGELEY_CONFIG_INCLUDE_LOGGING), __x86_64_quanta_ix1_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX1_RANGELEY_CONFIG_INCLUDE_LOGGING) },
#else
{ X86_64_QUANTA_IX1_RANGELEY_CONFIG_INCLUDE_LOGGING(__x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME), "__undefined__" },
#endif
#ifdef X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_OPTIONS_DEFAULT
{ __x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_OPTIONS_DEFAULT), __x86_64_quanta_ix1_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_OPTIONS_DEFAULT) },
#else
{ X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_OPTIONS_DEFAULT(__x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME), "__undefined__" },
#endif
#ifdef X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_BITS_DEFAULT
{ __x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_BITS_DEFAULT), __x86_64_quanta_ix1_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_BITS_DEFAULT) },
#else
{ X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_BITS_DEFAULT(__x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME), "__undefined__" },
#endif
#ifdef X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_CUSTOM_BITS_DEFAULT
{ __x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_CUSTOM_BITS_DEFAULT), __x86_64_quanta_ix1_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_CUSTOM_BITS_DEFAULT) },
#else
{ X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_CUSTOM_BITS_DEFAULT(__x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME), "__undefined__" },
#endif
#ifdef X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_STDLIB
{ __x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_STDLIB), __x86_64_quanta_ix1_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_STDLIB) },
#else
{ X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_STDLIB(__x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME), "__undefined__" },
#endif
#ifdef X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS
{ __x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS), __x86_64_quanta_ix1_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS) },
#else
{ X86_64_QUANTA_IX1_RANGELEY_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS(__x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME), "__undefined__" },
#endif
#ifdef X86_64_QUANTA_IX1_RANGELEY_CONFIG_INCLUDE_UCLI
{ __x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX1_RANGELEY_CONFIG_INCLUDE_UCLI), __x86_64_quanta_ix1_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX1_RANGELEY_CONFIG_INCLUDE_UCLI) },
#else
{ X86_64_QUANTA_IX1_RANGELEY_CONFIG_INCLUDE_UCLI(__x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME), "__undefined__" },
#endif
#ifdef X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_RPM_FAILURE_THRESHOLD
{ __x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_RPM_FAILURE_THRESHOLD), __x86_64_quanta_ix1_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_RPM_FAILURE_THRESHOLD) },
#else
{ X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_RPM_FAILURE_THRESHOLD(__x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME), "__undefined__" },
#endif
#ifdef X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_F2B_RPM_MAX
{ __x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_F2B_RPM_MAX), __x86_64_quanta_ix1_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_F2B_RPM_MAX) },
#else
{ X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_F2B_RPM_MAX(__x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME), "__undefined__" },
#endif
#ifdef X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_B2F_RPM_MAX
{ __x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_B2F_RPM_MAX), __x86_64_quanta_ix1_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_B2F_RPM_MAX) },
#else
{ X86_64_QUANTA_IX1_RANGELEY_CONFIG_SYSFAN_B2F_RPM_MAX(__x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME), "__undefined__" },
#endif
#ifdef X86_64_QUANTA_IX1_RANGELEY_CONFIG_PHY_RESET_DELAY_MS
{ __x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX1_RANGELEY_CONFIG_PHY_RESET_DELAY_MS), __x86_64_quanta_ix1_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX1_RANGELEY_CONFIG_PHY_RESET_DELAY_MS) },
#else
{ X86_64_QUANTA_IX1_RANGELEY_CONFIG_PHY_RESET_DELAY_MS(__x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME), "__undefined__" },
#endif
{ NULL, NULL }
};
#undef __x86_64_quanta_ix1_rangeley_config_STRINGIFY_VALUE
#undef __x86_64_quanta_ix1_rangeley_config_STRINGIFY_NAME
const char*
x86_64_quanta_ix1_rangeley_config_lookup(const char* setting)
{
int i;
for(i = 0; x86_64_quanta_ix1_rangeley_config_settings[i].name; i++) {
if(strcmp(x86_64_quanta_ix1_rangeley_config_settings[i].name, setting)) {
return x86_64_quanta_ix1_rangeley_config_settings[i].value;
}
}
return NULL;
}
int
x86_64_quanta_ix1_rangeley_config_show(struct aim_pvs_s* pvs)
{
int i;
for(i = 0; x86_64_quanta_ix1_rangeley_config_settings[i].name; i++) {
aim_printf(pvs, "%s = %s\n", x86_64_quanta_ix1_rangeley_config_settings[i].name, x86_64_quanta_ix1_rangeley_config_settings[i].value);
}
return i;
}
/* <auto.end.cdefs(X86_64_QUANTA_IX1_RANGELEY_CONFIG_HEADER).source> */

10
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/x86_64_quanta_ix1_rangeley_enums.c Executable file
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@@ -0,0 +1,10 @@
/**************************************************************************//**
*
*
*
*****************************************************************************/
#include <x86_64_quanta_ix1_rangeley/x86_64_quanta_ix1_rangeley_config.h>
/* <--auto.start.enum(ALL).source> */
/* <auto.end.enum(ALL).source> */

308
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/x86_64_quanta_ix1_rangeley_int.h Executable file
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@@ -0,0 +1,308 @@
/**************************************************************************//**
*
* x86_64_quanta_ix1_rangeley Internal Header
*
*****************************************************************************/
#ifndef __X86_64_QUANTA_IX1_RANGELEY_INT_H__
#define __X86_64_QUANTA_IX1_RANGELEY_INT_H__
#include <x86_64_quanta_ix1_rangeley/x86_64_quanta_ix1_rangeley_config.h>
#include <limits.h>
/* <auto.start.enum(ALL).header> */
/** thermal_oid */
typedef enum thermal_oid_e {
THERMAL_OID_THERMAL1 = ONLP_THERMAL_ID_CREATE(1),
THERMAL_OID_THERMAL2 = ONLP_THERMAL_ID_CREATE(2),
THERMAL_OID_THERMAL3 = ONLP_THERMAL_ID_CREATE(3),
THERMAL_OID_THERMAL4 = ONLP_THERMAL_ID_CREATE(4),
THERMAL_OID_THERMAL5 = ONLP_THERMAL_ID_CREATE(5),
THERMAL_OID_THERMAL6 = ONLP_THERMAL_ID_CREATE(6),
THERMAL_OID_THERMAL7 = ONLP_THERMAL_ID_CREATE(7),
THERMAL_OID_THERMAL8 = ONLP_THERMAL_ID_CREATE(8),
THERMAL_OID_THERMAL9 = ONLP_THERMAL_ID_CREATE(9),
THERMAL_OID_THERMAL10 = ONLP_THERMAL_ID_CREATE(10),
THERMAL_OID_THERMAL11 = ONLP_THERMAL_ID_CREATE(11),
THERMAL_OID_THERMAL12 = ONLP_THERMAL_ID_CREATE(12),
THERMAL_OID_THERMAL13 = ONLP_THERMAL_ID_CREATE(13),
THERMAL_OID_THERMAL14 = ONLP_THERMAL_ID_CREATE(14),
THERMAL_OID_THERMAL15 = ONLP_THERMAL_ID_CREATE(15),
THERMAL_OID_THERMAL16 = ONLP_THERMAL_ID_CREATE(16),
} thermal_oid_t;
/** Enum names. */
const char* thermal_oid_name(thermal_oid_t e);
/** Enum values. */
int thermal_oid_value(const char* str, thermal_oid_t* e, int substr);
/** Enum descriptions. */
const char* thermal_oid_desc(thermal_oid_t e);
/** Enum validator. */
int thermal_oid_valid(thermal_oid_t e);
/** validator */
#define THERMAL_OID_VALID(_e) \
(thermal_oid_valid((_e)))
/** thermal_oid_map table. */
extern aim_map_si_t thermal_oid_map[];
/** thermal_oid_desc_map table. */
extern aim_map_si_t thermal_oid_desc_map[];
/** psu_oid */
typedef enum psu_oid_e {
PSU_OID_PSU1 = ONLP_PSU_ID_CREATE(1),
PSU_OID_PSU2 = ONLP_PSU_ID_CREATE(2),
} psu_oid_t;
/** Enum names. */
const char* psu_oid_name(psu_oid_t e);
/** Enum values. */
int psu_oid_value(const char* str, psu_oid_t* e, int substr);
/** Enum descriptions. */
const char* psu_oid_desc(psu_oid_t e);
/** Enum validator. */
int psu_oid_valid(psu_oid_t e);
/** validator */
#define PSU_OID_VALID(_e) \
(psu_oid_valid((_e)))
/** psu_oid_map table. */
extern aim_map_si_t psu_oid_map[];
/** psu_oid_desc_map table. */
extern aim_map_si_t psu_oid_desc_map[];
/** thermal_id */
typedef enum thermal_id_e {
THERMAL_ID_THERMAL1 = 1,
THERMAL_ID_THERMAL2 = 2,
THERMAL_ID_THERMAL3 = 3,
THERMAL_ID_THERMAL4 = 4,
THERMAL_ID_THERMAL5 = 5,
THERMAL_ID_THERMAL6 = 6,
THERMAL_ID_THERMAL7 = 7,
THERMAL_ID_THERMAL8 = 8,
THERMAL_ID_THERMAL9 = 9,
THERMAL_ID_THERMAL10 = 10,
THERMAL_ID_THERMAL11 = 11,
THERMAL_ID_THERMAL12 = 12,
THERMAL_ID_THERMAL13 = 13,
THERMAL_ID_THERMAL14 = 14,
THERMAL_ID_THERMAL15 = 15,
THERMAL_ID_THERMAL16 = 16,
} thermal_id_t;
/** Enum names. */
const char* thermal_id_name(thermal_id_t e);
/** Enum values. */
int thermal_id_value(const char* str, thermal_id_t* e, int substr);
/** Enum descriptions. */
const char* thermal_id_desc(thermal_id_t e);
/** Enum validator. */
int thermal_id_valid(thermal_id_t e);
/** validator */
#define THERMAL_ID_VALID(_e) \
(thermal_id_valid((_e)))
/** thermal_id_map table. */
extern aim_map_si_t thermal_id_map[];
/** thermal_id_desc_map table. */
extern aim_map_si_t thermal_id_desc_map[];
/** fan_id */
typedef enum fan_id_e {
FAN_ID_FAN1 = 1,
FAN_ID_FAN2 = 2,
FAN_ID_FAN3 = 3,
FAN_ID_FAN4 = 4,
FAN_ID_FAN5 = 5,
FAN_ID_FAN6 = 6,
FAN_ID_FAN7 = 7,
FAN_ID_FAN8 = 8,
FAN_ID_FAN9 = 9,
FAN_ID_FAN10 = 10,
} fan_id_t;
/** Enum names. */
const char* fan_id_name(fan_id_t e);
/** Enum values. */
int fan_id_value(const char* str, fan_id_t* e, int substr);
/** Enum descriptions. */
const char* fan_id_desc(fan_id_t e);
/** Enum validator. */
int fan_id_valid(fan_id_t e);
/** validator */
#define FAN_ID_VALID(_e) \
(fan_id_valid((_e)))
/** fan_id_map table. */
extern aim_map_si_t fan_id_map[];
/** fan_id_desc_map table. */
extern aim_map_si_t fan_id_desc_map[];
/** psu_id */
typedef enum psu_id_e {
PSU_ID_PSU1 = 1,
PSU_ID_PSU2 = 2,
} psu_id_t;
/** Enum names. */
const char* psu_id_name(psu_id_t e);
/** Enum values. */
int psu_id_value(const char* str, psu_id_t* e, int substr);
/** Enum descriptions. */
const char* psu_id_desc(psu_id_t e);
/** Enum validator. */
int psu_id_valid(psu_id_t e);
/** validator */
#define PSU_ID_VALID(_e) \
(psu_id_valid((_e)))
/** psu_id_map table. */
extern aim_map_si_t psu_id_map[];
/** psu_id_desc_map table. */
extern aim_map_si_t psu_id_desc_map[];
/** fan_oid */
typedef enum fan_oid_e {
FAN_OID_FAN1 = ONLP_FAN_ID_CREATE(1),
FAN_OID_FAN2 = ONLP_FAN_ID_CREATE(2),
FAN_OID_FAN3 = ONLP_FAN_ID_CREATE(3),
FAN_OID_FAN4 = ONLP_FAN_ID_CREATE(4),
FAN_OID_FAN5 = ONLP_FAN_ID_CREATE(5),
FAN_OID_FAN6 = ONLP_FAN_ID_CREATE(6),
FAN_OID_FAN7 = ONLP_FAN_ID_CREATE(7),
FAN_OID_FAN8 = ONLP_FAN_ID_CREATE(8),
FAN_OID_FAN9 = ONLP_FAN_ID_CREATE(9),
FAN_OID_FAN10 = ONLP_FAN_ID_CREATE(10),
} fan_oid_t;
/** Enum names. */
const char* fan_oid_name(fan_oid_t e);
/** Enum values. */
int fan_oid_value(const char* str, fan_oid_t* e, int substr);
/** Enum descriptions. */
const char* fan_oid_desc(fan_oid_t e);
/** Enum validator. */
int fan_oid_valid(fan_oid_t e);
/** validator */
#define FAN_OID_VALID(_e) \
(fan_oid_valid((_e)))
/** fan_oid_map table. */
extern aim_map_si_t fan_oid_map[];
/** fan_oid_desc_map table. */
extern aim_map_si_t fan_oid_desc_map[];
/* <auto.end.enum(ALL).header> */
/* psu info table */
struct psu_info_s {
char path[PATH_MAX];
int present;
int busno;
int addr;
};
/** led_id */
typedef enum led_id_e {
LED_ID_SYSTEM = 1,
LED_ID_FAN = 2,
LED_ID_PSU_1 = 3,
LED_ID_PSU_2 = 4,
LED_ID_FAN_FAIL_1 = 5,
LED_ID_FAN_FAIL_2 = 6,
LED_ID_FAN_FAIL_3 = 7,
LED_ID_FAN_FAIL_4 = 8,
} led_id_t;
/** Enum names. */
const char* led_id_name(led_id_t e);
/** Enum values. */
int led_id_value(const char* str, led_id_t* e, int substr);
/** Enum descriptions. */
const char* led_id_desc(led_id_t e);
/** Enum validator. */
int led_id_valid(led_id_t e);
/** validator */
#define LED_ID_VALID(_e) \
(led_id_valid((_e)))
/** led_id_map table. */
extern aim_map_si_t led_id_map[];
/** led_id_desc_map table. */
extern aim_map_si_t led_id_desc_map[];
/** led_oid */
typedef enum led_oid_e {
LED_OID_SYSTEM = ONLP_LED_ID_CREATE(LED_ID_SYSTEM),
LED_OID_FAN = ONLP_LED_ID_CREATE(LED_ID_FAN),
LED_OID_PSU_1 = ONLP_LED_ID_CREATE(LED_ID_PSU_1),
LED_OID_PSU_2 = ONLP_LED_ID_CREATE(LED_ID_PSU_2),
LED_OID_FAN_FAIL_1 = ONLP_LED_ID_CREATE(LED_ID_FAN_FAIL_1),
LED_OID_FAN_FAIL_2 = ONLP_LED_ID_CREATE(LED_ID_FAN_FAIL_2),
LED_OID_FAN_FAIL_3 = ONLP_LED_ID_CREATE(LED_ID_FAN_FAIL_3),
LED_OID_FAN_FAIL_4 = ONLP_LED_ID_CREATE(LED_ID_FAN_FAIL_4),
} led_oid_t;
/** Enum names. */
const char* led_oid_name(led_oid_t e);
/** Enum values. */
int led_oid_value(const char* str, led_oid_t* e, int substr);
/** Enum descriptions. */
const char* led_oid_desc(led_oid_t e);
/** Enum validator. */
int led_oid_valid(led_oid_t e);
/** validator */
#define LED_OID_VALID(_e) \
(led_oid_valid((_e)))
/** led_oid_map table. */
extern aim_map_si_t led_oid_map[];
/** led_oid_desc_map table. */
extern aim_map_si_t led_oid_desc_map[];
/* <auto.end.enum(ALL).header> */
struct led_control_s{
int PMCnt;
int psu_status_changed;
int fan_status_changed;
int fan_alert;
int psu1_present;
int psu2_present;
int psu1_power_good;
int psu2_power_good;
};
#define SYS_HWMON_PREFIX "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/0-004e"
#endif /* __X86_64_QUANTA_IX1_RANGELEY_INT_H__ */

18
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/x86_64_quanta_ix1_rangeley_log.c Executable file
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@@ -0,0 +1,18 @@
/**************************************************************************//**
*
*
*
*****************************************************************************/
#include <x86_64_quanta_ix1_rangeley/x86_64_quanta_ix1_rangeley_config.h>
#include "x86_64_quanta_ix1_rangeley_log.h"
/*
* x86_64_quanta_ix1_rangeley log struct.
*/
AIM_LOG_STRUCT_DEFINE(
X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_OPTIONS_DEFAULT,
X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_BITS_DEFAULT,
NULL, /* Custom log map */
X86_64_QUANTA_IX1_RANGELEY_CONFIG_LOG_CUSTOM_BITS_DEFAULT
);

12
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/x86_64_quanta_ix1_rangeley_log.h Executable file
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@@ -0,0 +1,12 @@
/**************************************************************************//**
*
*
*
*****************************************************************************/
#ifndef __X86_64_QUANTA_IX1_RANGELEY_LOG_H__
#define __X86_64_QUANTA_IX1_RANGELEY_LOG_H__
#define AIM_LOG_MODULE_NAME x86_64_quanta_ix1_rangeley
#include <AIM/aim_log.h>
#endif /* __X86_64_QUANTA_IX1_RANGELEY_LOG_H__ */

24
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/x86_64_quanta_ix1_rangeley_module.c Executable file
View File

@@ -0,0 +1,24 @@
/**************************************************************************//**
*
*
*
*****************************************************************************/
#include <x86_64_quanta_ix1_rangeley/x86_64_quanta_ix1_rangeley_config.h>
#include "x86_64_quanta_ix1_rangeley_log.h"
static int
datatypes_init__(void)
{
#define X86_64_QUANTA_IX1_RANGELEY_ENUMERATION_ENTRY(_enum_name, _desc) AIM_DATATYPE_MAP_REGISTER(_enum_name, _enum_name##_map, _desc, AIM_LOG_INTERNAL);
#include <x86_64_quanta_ix1_rangeley/x86_64_quanta_ix1_rangeley.x>
return 0;
}
void __x86_64_quanta_ix1_rangeley_module_init__(void)
{
AIM_LOG_STRUCT_REGISTER();
datatypes_init__();
}
int __onlp_platform_version__ = 1;

50
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/x86_64_quanta_ix1_rangeley_ucli.c Executable file
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@@ -0,0 +1,50 @@
/**************************************************************************//**
*
*
*
*****************************************************************************/
#include <x86_64_quanta_ix1_rangeley/x86_64_quanta_ix1_rangeley_config.h>
#if X86_64_QUANTA_IX1_RANGELEY_CONFIG_INCLUDE_UCLI == 1
#include <uCli/ucli.h>
#include <uCli/ucli_argparse.h>
#include <uCli/ucli_handler_macros.h>
static ucli_status_t
x86_64_quanta_ix1_rangeley_ucli_ucli__config__(ucli_context_t* uc)
{
UCLI_HANDLER_MACRO_MODULE_CONFIG(x86_64_quanta_ix1_rangeley)
}
/* <auto.ucli.handlers.start> */
/* <auto.ucli.handlers.end> */
static ucli_module_t
x86_64_quanta_ix1_rangeley_ucli_module__ =
{
"x86_64_quanta_ix1_rangeley_ucli",
NULL,
x86_64_quanta_ix1_rangeley_ucli_ucli_handlers__,
NULL,
NULL,
};
ucli_node_t*
x86_64_quanta_ix1_rangeley_ucli_node_create(void)
{
ucli_node_t* n;
ucli_module_init(&x86_64_quanta_ix1_rangeley_ucli_module__);
n = ucli_node_create("x86_64_quanta_ix1_rangeley", NULL, &x86_64_quanta_ix1_rangeley_ucli_module__);
ucli_node_subnode_add(n, ucli_module_log_node_create("x86_64_quanta_ix1_rangeley"));
return n;
}
#else
void*
x86_64_quanta_ix1_rangeley_ucli_node_create(void)
{
return NULL;
}
#endif

1
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/platform-config/Makefile Executable file
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@@ -0,0 +1 @@
include $(ONL)/make/pkg.mk

1
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/platform-config/r0/Makefile Executable file
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@@ -0,0 +1 @@
include $(ONL)/make/pkg.mk

1
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/platform-config/r0/PKG.yml Executable file
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@@ -0,0 +1 @@
!include $ONL_TEMPLATES/platform-config-platform.yml ARCH=amd64 VENDOR=quanta BASENAME=x86-64-quanta-ix1-rangeley REVISION=r0

31
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/platform-config/r0/src/lib/x86-64-quanta-ix1-rangeley-r0.yml Executable file
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@@ -0,0 +1,31 @@
---
######################################################################
#
# platform-config for IX1
#
######################################################################
x86-64-quanta-ix1-rangeley-r0:
grub:
serial: >-
--port=0x2f8
--speed=115200
--word=8
--parity=no
--stop=1
kernel:
<<: *kernel-3-16
args: >-
console=ttyS1,115200n8
reboot=c,p
##network:
## interfaces:
## ma1:
## name: ~
## syspath: pci0000:00/0000:00:14.0

16
packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/platform-config/r0/src/python/x86_64_quanta_ix1_rangeley_r0/__init__.py Executable file
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@@ -0,0 +1,16 @@
from onl.platform.base import *
from onl.platform.quanta import *
class OnlPlatform_x86_64_quanta_ix1_rangeley_r0(OnlPlatformQuanta,
OnlPlatformPortConfig_32x100):
PLATFORM='x86-64-quanta-ix1-rangeley-r0'
MODEL="IX1"
SYS_OBJECT_ID=".8.1"
def baseconfig(self):
self.insmod("qci_pmbus")
self.insmod("qci_cpld")
self.insmod("quanta_hwmon_ix_series")
self.insmod("quanta_platform_ix1")
return True

8
packages/platforms/quanta/x86-64/x86-64-quanta-ly6-rangeley/onlp/builds/src/x86_64_quanta_ly6_rangeley/module/src/sysi.c
View File

@@ -153,7 +153,7 @@ update_rpsu_fan_status(void){
last_status = led_control.psu1_present;
rv = onlp_gpio_get(QUANTA_LY6_PSU_GPIO_PSU1_PRSNT_N, &value);
if(rv < 0) {
printf("GPIO %d read Error!\n", QUANTA_LY6_PSU_GPIO_PSU1_PRSNT_N);
AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_LY6_PSU_GPIO_PSU1_PRSNT_N);
return rv;
}
led_control.psu1_present = (value ? 0 : 1);
@@ -163,7 +163,7 @@ update_rpsu_fan_status(void){
last_status = led_control.psu1_power_good;
rv = onlp_gpio_get(QUANTA_LY6_PSU_GPIO_PSU1_PWRGD, &value);
if(rv < 0) {
printf("GPIO %d read Error!\n", QUANTA_LY6_PSU_GPIO_PSU1_PWRGD);
AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_LY6_PSU_GPIO_PSU1_PWRGD);
return rv;
}
led_control.psu1_power_good = (value ? 1 : 0);
@@ -173,7 +173,7 @@ update_rpsu_fan_status(void){
last_status = led_control.psu2_present;
rv = onlp_gpio_get(QUANTA_LY6_PSU_GPIO_PSU2_PRSNT_N, &value);
if(rv < 0) {
printf("GPIO %d read Error!\n", QUANTA_LY6_PSU_GPIO_PSU2_PRSNT_N);
AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_LY6_PSU_GPIO_PSU2_PRSNT_N);
return rv;
}
led_control.psu2_present = (value ? 0 : 1);
@@ -183,7 +183,7 @@ update_rpsu_fan_status(void){
last_status = led_control.psu2_power_good;
rv = onlp_gpio_get(QUANTA_LY6_PSU_GPIO_PSU2_PWRGD, &value);
if(rv < 0) {
printf("GPIO %d read Error!\n", QUANTA_LY6_PSU_GPIO_PSU2_PWRGD);
AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_LY6_PSU_GPIO_PSU2_PWRGD);
return rv;
}
led_control.psu2_power_good = (value ? 1 : 0);

8
packages/platforms/quanta/x86-64/x86-64-quanta-ly8-rangeley/onlp/builds/src/x86_64_quanta_ly8_rangeley/module/src/sysi.c
View File

@@ -153,7 +153,7 @@ update_rpsu_fan_status(void){
last_status = led_control.psu1_present;
rv = onlp_gpio_get(QUANTA_LY8_PSU_GPIO_PSU1_PRSNT_N, &value);
if(rv < 0) {
printf("GPIO %d read Error!\n", QUANTA_LY8_PSU_GPIO_PSU1_PRSNT_N);
AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_LY8_PSU_GPIO_PSU1_PRSNT_N);
return rv;
}
led_control.psu1_present = (value ? 0 : 1);
@@ -163,7 +163,7 @@ update_rpsu_fan_status(void){
last_status = led_control.psu1_power_good;
rv = onlp_gpio_get(QUANTA_LY8_PSU_GPIO_PSU1_PWRGD, &value);
if(rv < 0) {
printf("GPIO %d read Error!\n", QUANTA_LY8_PSU_GPIO_PSU1_PWRGD);
AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_LY8_PSU_GPIO_PSU1_PWRGD);
return rv;
}
led_control.psu1_power_good = (value ? 1 : 0);
@@ -173,7 +173,7 @@ update_rpsu_fan_status(void){
last_status = led_control.psu2_present;
rv = onlp_gpio_get(QUANTA_LY8_PSU_GPIO_PSU2_PRSNT_N, &value);
if(rv < 0) {
printf("GPIO %d read Error!\n", QUANTA_LY8_PSU_GPIO_PSU2_PRSNT_N);
AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_LY8_PSU_GPIO_PSU2_PRSNT_N);
return rv;
}
led_control.psu2_present = (value ? 0 : 1);
@@ -183,7 +183,7 @@ update_rpsu_fan_status(void){
last_status = led_control.psu2_power_good;
rv = onlp_gpio_get(QUANTA_LY8_PSU_GPIO_PSU2_PWRGD, &value);
if(rv < 0) {
printf("GPIO %d read Error!\n", QUANTA_LY8_PSU_GPIO_PSU2_PWRGD);
AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_LY8_PSU_GPIO_PSU2_PWRGD);
return rv;
}
led_control.psu2_power_good = (value ? 1 : 0);

8
packages/platforms/quanta/x86-64/x86-64-quanta-ly9-rangeley/onlp/builds/src/x86_64_quanta_ly9_rangeley/module/src/sysi.c
View File

@@ -154,7 +154,7 @@ update_rpsu_fan_status(void){
last_status = led_control.psu1_present;
rv = onlp_gpio_get(QUANTA_LY9_PSU_GPIO_PSU1_PRSNT_N, &value);
if(rv < 0) {
printf("GPIO %d read Error!\n", QUANTA_LY9_PSU_GPIO_PSU1_PRSNT_N);
AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_LY9_PSU_GPIO_PSU1_PRSNT_N);
return rv;
}
led_control.psu1_present = (value ? 0 : 1);
@@ -164,7 +164,7 @@ update_rpsu_fan_status(void){
last_status = led_control.psu1_power_good;
rv = onlp_gpio_get(QUANTA_LY9_PSU_GPIO_PSU1_PWRGD, &value);
if(rv < 0) {
printf("GPIO %d read Error!\n", QUANTA_LY9_PSU_GPIO_PSU1_PWRGD);
AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_LY9_PSU_GPIO_PSU1_PWRGD);
return rv;
}
led_control.psu1_power_good = (value ? 1 : 0);
@@ -174,7 +174,7 @@ update_rpsu_fan_status(void){
last_status = led_control.psu2_present;
rv = onlp_gpio_get(QUANTA_LY9_PSU_GPIO_PSU2_PRSNT_N, &value);
if(rv < 0) {
printf("GPIO %d read Error!\n", QUANTA_LY9_PSU_GPIO_PSU2_PRSNT_N);
AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_LY9_PSU_GPIO_PSU2_PRSNT_N);
return rv;
}
led_control.psu2_present = (value ? 0 : 1);
@@ -184,7 +184,7 @@ update_rpsu_fan_status(void){
last_status = led_control.psu2_power_good;
rv = onlp_gpio_get(QUANTA_LY9_PSU_GPIO_PSU2_PWRGD, &value);
if(rv < 0) {
printf("GPIO %d read Error!\n", QUANTA_LY9_PSU_GPIO_PSU2_PWRGD);
AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_LY9_PSU_GPIO_PSU2_PWRGD);
return rv;
}
led_control.psu2_power_good = (value ? 1 : 0);