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- Add the AS4600 DTB build to the platform build package.

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- The AS4600 DTB now comes from the platform build package rather than the kernel package.
This commit is contained in:
Jeffrey Townsend
2017-02-15 17:33:59 +00:00
parent 532a4d5b53
commit e404ad877a
5 changed files with 484 additions and 2 deletions
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1
packages/platforms/accton/powerpc/powerpc-accton-as4600-54t/platform-config/r0/builds/Makefile Normal file
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@@ -0,0 +1 @@
include $(ONL)/make/subdirs.mk

1
packages/platforms/accton/powerpc/powerpc-accton-as4600-54t/platform-config/r0/builds/dtb/.gitignore vendored Normal file
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@@ -0,0 +1 @@
*.dtb

1
packages/platforms/accton/powerpc/powerpc-accton-as4600-54t/platform-config/r0/builds/dtb/Makefile Normal file
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@@ -0,0 +1 @@
include $(ONL)/make/dtbs.mk

479
packages/platforms/accton/powerpc/powerpc-accton-as4600-54t/platform-config/r0/builds/dtb/powerpc-accton-as4600-54t-r0.dts Normal file
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@@ -0,0 +1,479 @@
/*
* P2020 RDB Device Tree Source
*
* Copyright 2009-2010 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "powerpc-as4600-54t";
compatible = "fsl,P2020RDB";
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &enet1;
serial0 = &serial0;
pci1 = &pci1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,P2020@0 {
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
};
PowerPC,P2020@1 {
device_type = "cpu";
reg = <0x1>;
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
};
localbus@ff705000 {
ranges = <0x0 0x0 0x0 0xef800000 0x800000 0x1 0x0 0x0 0xea000000 0x100>;
interrupts = <0x13 0x2>;
reg = <0x0 0xff705000 0x0 0x1000>;
compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
#size-cells = <0x1>;
#address-cells = <0x2>;
bus-frequency = <0x1dcd650>;
cpld@1,0 {
reg = <0x1 0x0 0x100>;
compatible = "accton,4654-cpld";
};
flash@0,0 {
device-width = <0x1>;
bank-width = <0x1>;
reg = <0x0 0x0 0x800000>;
compatible = "cfi-flash";
#size-cells = <0x1>;
#address-cells = <0x1>;
partition@0 {
label = "open";
reg = <0x0 0x360000>;
};
partition@1 {
label = "onie";
reg = <0x360000 0x400000>;
};
partition@2 {
env_size = <0x10000>;
label = "uboot-env";
reg = <0x760000 0x10000>;
};
partition@3 {
label = "board_eeprom";
reg = <0x770000 0x10000>;
};
partition@4 {
label = "uboot";
reg = <0x780000 0x80000>;
};
};
};
soc@ff700000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,p2020-immr", "simple-bus";
ranges = <0x0 0x0 0xff700000 0x100000>;
bus-frequency = <0>; // Filled out by uboot.
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,p2020-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,p2020-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
spi@7000 {
cell-index = <0>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,espi";
reg = <0x7000 0x1000>;
interrupts = <59 0x2>;
interrupt-parent = <&mpic>;
mode = "cpu";
fsl_m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,espi-flash";
reg = <0>;
linux,modalias = "fsl_m25p80";
modal = "s25sl128b";
spi-max-frequency = <32000000>;
mode = <0>;
partition@0 {
/* 512KB for u-boot Bootloader Image */
reg = <0x0 0x00080000>;
label = "SPI (RO) U-Boot Image";
read-only;
};
partition@80000 {
/* 512KB for DTB Image */
reg = <0x00080000 0x00080000>;
label = "SPI (RO) DTB Image";
read-only;
};
partition@100000 {
/* 4MB for Linux Kernel Image */
reg = <0x00100000 0x00400000>;
label = "SPI (RO) Linux Kernel Image";
read-only;
};
partition@500000 {
/* 4MB for Compressed RFS Image */
reg = <0x00500000 0x00400000>;
label = "SPI (RO) Compressed RFS Image";
read-only;
};
partition@900000 {
/* 7MB for JFFS2 based RFS */
reg = <0x00900000 0x00700000>;
label = "SPI (RW) JFFS2 RFS";
};
};
};
dma@c300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,eloplus-dma";
reg = <0xc300 0x4>;
ranges = <0x0 0xc100 0x200>;
cell-index = <1>;
dma-channel@0 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <76 2>;
};
dma-channel@80 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <77 2>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <78 2>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <79 2>;
};
};
gpio: gpio-controller@f000 {
#gpio-cells = <2>;
compatible = "fsl,mpc8572-gpio";
reg = <0xf000 0x100>;
interrupts = <47 0x2>;
interrupt-parent = <&mpic>;
gpio-controller;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,p2020-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x80000>; // L2,512K
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
usb@22000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-usb2-dr";
reg = <0x22000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <28 0x2>;
phy_type = "ulpi";
};
mdio0: mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x24520 0x20>;
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <3 1>;
reg = <0x1>;
device_type = "ethernet-phy";
};
};
enet1: ethernet@25000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
cell-index = <0x1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
interrupts = <
0x23 0x2
0x24 0x2
0x28 0x2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi1>;
phy-handle = <&phy1>;
phy-connection-type = "sgmii";
};
mdio1: mdio@25520 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
sdhci@2e000 {
compatible = "fsl,p2020-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <72 0x2>;
interrupt-parent = <&mpic>;
fsl,sdhci-adjust-timeout;
/* Filled in by U-Boot */
clock-frequency = <0>;
};
crypto@30000 {
compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
"fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <45 2 58 2>;
interrupt-parent = <&mpic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0xbfe>;
fsl,descriptor-types-mask = <0x3ab0ebf>;
fsl,multi-host-mode = "dual";
fsl,channel-remap = <0x3>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
message@41400 {
compatible = "fsl,p2020-msg", "fsl,mpic-msg";
reg = <0x41400 0x200>;
interrupts = <
0xb0 2
0xb1 2
0xb2 2
0xb3 2>;
interrupt-parent = <&mpic>;
};
message@42400 {
compatible = "fsl,p2020-msg", "fsl,mpic-msg";
reg = <0x42400 0x200>;
interrupts = <
0xb4 2
0xb5 2
0xb6 2
0xb7 2>;
interrupt-parent = <&mpic>;
};
msi@41600 {
compatible = "fsl,p2020-msi", "fsl,mpic-msi";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,p2020-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
};
pci1: pcie@ff70a000 {
cell-index = <2>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xff70a000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <26 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0x0 0x0 0x1 &mpic 0x0 0x1
0000 0x0 0x0 0x2 &mpic 0x1 0x1
0000 0x0 0x0 0x3 &mpic 0x2 0x1
0000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0xc0000000
0x2000000 0x0 0xc0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};

4
packages/platforms/accton/powerpc/powerpc-accton-as4600-54t/platform-config/r0/src/lib/powerpc-accton-as4600-54t-r0.yml
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@@ -11,8 +11,8 @@ powerpc-accton-as4600-54t-r0:
kernel:
<<: *e500v-kernel
dtb:
=: powerpc-as4600-54t.dtb
<<: *e500v-kernel-package
=: powerpc-accton-as4600-54t-r0.dtb
package: onl-platform-build-powerpc-accton-as4600-54t-r0:powerpc
loader:
device: /dev/sda