mirror of
https://github.com/Telecominfraproject/OpenNetworkLinux.git
synced 2025-12-27 10:14:47 +00:00
Update the patch file "driver-igb-netberg-aurora.patch"
- Remove unused and re-define definitions in bcm_phy.c - Change the name of function "bcm54616_config_init" to "bcm54616s_config_init"
This commit is contained in:
raymondhuey
@@ -1,354 +1,204 @@
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diff -Nu a/drivers/net/ethernet/intel/igb/bcm_phy.c b/drivers/net/ethernet/intel/igb/bcm_phy.c
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--- a/drivers/net/ethernet/intel/igb/bcm_phy.c 1969-12-31 16:00:00.000000000 -0800
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+++ b/drivers/net/ethernet/intel/igb/bcm_phy.c 2016-12-26 21:40:26.000000000 -0800
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@@ -0,0 +1,357 @@
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+
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+
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+
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--- a/drivers/net/ethernet/intel/igb/bcm_phy.c 1970-01-01 08:00:00.000000000 +0800
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+++ b/drivers/net/ethernet/intel/igb/bcm_phy.c 2017-06-20 17:00:46.000000000 +0800
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@@ -0,0 +1,206 @@
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+#include "e1000_hw.h"
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+#include "linux/brcmphy.h"
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+
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+/*
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+ * 1000Base-T Control Register
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+ */
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+#define MII_GB_CTRL_MS_MAN (1 << 12) /* Manual Master/Slave mode */
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+#define MII_GB_CTRL_MS (1 << 11) /* Master/Slave negotiation mode */
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+#define MII_GB_CTRL_PT (1 << 10) /* Port type */
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+#define MII_GB_CTRL_ADV_1000FD (1 << 9) /* Advertise 1000Base-T FD */
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+#define MII_GB_CTRL_ADV_1000HD (1 << 8) /* Advertise 1000Base-T HD */
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+
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+
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+#define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */
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+#define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */
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+#define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */
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+#define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */
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+#define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */
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+#define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
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+#define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
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+#define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
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+#define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
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+#define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */
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+#define MII_BCM54XX_AUX_CTL_ENCODE(val) (((val & 0x7) << 12)|(val & 0x7))
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+#define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */
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+#define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */
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+#define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */
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+#define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */
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+#define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */
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+#define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */
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+#define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */
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+#define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */
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+#define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */
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+#define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */
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+#define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */
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+#define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */
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+#define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */
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+#define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */
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+#define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */
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+#define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */
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+#define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */
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+
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+/*
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+ * MII Link Advertisment
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+ */
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+#define MII_ANA_ASF (1 << 0)/* Advertise Selector Field */
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+#define MII_ANA_HD_10 (1 << 5)/* Half duplex 10Mb/s supported */
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+#define MII_ANA_FD_10 (1 << 6)/* Full duplex 10Mb/s supported */
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+#define MII_ANA_HD_100 (1 << 7)/* Half duplex 100Mb/s supported */
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+#define MII_ANA_FD_100 (1 << 8)/* Full duplex 100Mb/s supported */
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+#define MII_ANA_T4 (1 << 9)/* T4 */
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+#define MII_ANA_ASF (1 << 0) /* Advertise Selector Field */
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+#define MII_ANA_HD_10 (1 << 5) /* Half duplex 10Mb/s supported */
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+#define MII_ANA_FD_10 (1 << 6) /* Full duplex 10Mb/s supported */
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+#define MII_ANA_HD_100 (1 << 7) /* Half duplex 100Mb/s supported */
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+#define MII_ANA_FD_100 (1 << 8) /* Full duplex 100Mb/s supported */
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+#define MII_ANA_T4 (1 << 9) /* T4 */
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+#define MII_ANA_PAUSE (1 << 10)/* Pause supported */
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+#define MII_ANA_ASYM_PAUSE (1 << 11)/* Asymmetric pause supported */
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+#define MII_ANA_RF (1 << 13)/* Remote fault */
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+#define MII_ANA_NP (1 << 15)/* Next Page */
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+
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+#define MII_ANA_ASF_802_3 (1) /* 802.3 PHY */
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+
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+
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+#define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */
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+#define MII_BCM54XX_SHD_WRITE 0x8000
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+#define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
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+#define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
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+
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+#define MII_BCM54XX_AUX_STATUS 0x19 /* Auxiliary status */
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+#define MII_BCM54XX_AUX_STATUS_LINKMODE_MASK 0x0700
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+#define MII_BCM54XX_AUX_STATUS_LINKMODE_SHIFT 8
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+#define MII_BCM54XX_SHD_WR_ENCODE(val, data) \
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+ (MII_BCM54XX_SHD_WRITE | MII_BCM54XX_SHD_VAL(val) | \
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+ MII_BCM54XX_SHD_DATA(data))
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+#define MII_ANA_ASF_802_3 (1) /* 802.3 PHY */
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+
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+/*
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+ * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18)
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+ */
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+#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
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+#define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400
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+#define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
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+
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+#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
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+#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
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+#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
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+#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
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+
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+#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
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+
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+/*
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+ * Broadcom LED source encodings. These are used in BCM5461, BCM5481,
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+ * BCM5482, and possibly some others.
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+ */
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+#define BCM_LED_SRC_LINKSPD1 0x0
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+#define BCM_LED_SRC_LINKSPD2 0x1
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+#define BCM_LED_SRC_XMITLED 0x2
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+#define BCM_LED_SRC_ACTIVITYLED 0x3
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+#define BCM_LED_SRC_FDXLED 0x4
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+#define BCM_LED_SRC_SLAVE 0x5
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+#define BCM_LED_SRC_INTR 0x6
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+#define BCM_LED_SRC_QUALITY 0x7
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+#define BCM_LED_SRC_RCVLED 0x8
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+#define BCM_LED_SRC_MULTICOLOR1 0xa
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+#define BCM_LED_SRC_OPENSHORT 0xb
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+#define BCM_LED_SRC_OFF 0xe /* Tied high */
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+#define BCM_LED_SRC_ON 0xf /* Tied low */
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+
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+ /*
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+ * BCM54XX: Shadow registers
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+ * Shadow values go into bits [14:10] of register 0x1c to select a shadow
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+ * register to access.
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+ */
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+
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+#define BCM54XX_SHD_AUTODETECT 0x1e /* 11110: Auto detect Regisrer */
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+ * BCM54XX: Shadow registers
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+ * Shadow values go into bits [14:10] of register 0x1c to select a shadow
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+ * register to access.
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+ */
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+#define BCM54XX_SHD_AUTODETECT 0x1e /* 11110: Auto detect Regisrer */
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+#define BCM54XX_SHD_MODE 0x1f /* 11111: Mode Control Register */
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+#define BCM54XX_SHD_MODE_COPPER 1<<7
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+#define BCM54XX_SHD_MODE_SER 1<<6
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+ /*
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+ * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17)
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+ */
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+ #define MII_BCM54XX_EXP_AADJ1CH0 0x001f
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+ #define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200
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+ #define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100
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+ #define MII_BCM54XX_EXP_AADJ1CH3 0x601f
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+ #define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002
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+ #define MII_BCM54XX_EXP_EXP08 0x0F08
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+ #define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001
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+ #define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200
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+ #define MII_BCM54XX_EXP_EXP75 0x0f75
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+ #define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c
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+ #define MII_BCM54XX_EXP_EXP96 0x0f96
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+ #define MII_BCM54XX_EXP_EXP96_MYST 0x0010
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+ #define MII_BCM54XX_EXP_EXP97 0x0f97
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+ #define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c
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+
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+
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+#define BCM54XX_SHD_MODE_SER 1<<6
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+
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+
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+ /*
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+ * Indirect register access functions for the 1000BASE-T/100BASE-TX/10BASE-T
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+ * 0x1c shadow registers.
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+ */
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+/*
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+ * Indirect register access functions for the 1000BASE-T/100BASE-TX/10BASE-T
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+ * 0x1c shadow registers.
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+ */
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+
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+int bcmphy_write(struct e1000_hw *hw,u32 reg,u16 regval){
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+int bcmphy_write(struct e1000_hw *hw,u32 reg, u16 regval)
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+{
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+ u32 ret;
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+ struct e1000_phy_info *phy = &hw->phy;
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+
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+ u32 ret;
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+ struct e1000_phy_info *phy = &hw->phy;
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+ ret=phy->ops.write_reg(hw,reg,regval);
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+ return ret;
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+ ret = phy->ops.write_reg(hw,reg, regval);
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+ return ret;
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+}
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+
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+u16 bcmphy_read(struct e1000_hw *hw,u32 reg){
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+u16 bcmphy_read(struct e1000_hw *hw, u32 reg)
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+{
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+ u16 val;
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+ struct e1000_phy_info *phy = &hw->phy;
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+
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+ u16 val;
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+ struct e1000_phy_info *phy = &hw->phy;
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+ phy->ops.read_reg(hw,reg,&val);
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+ return val;
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+ phy->ops.read_reg(hw,reg, &val);
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+ return val;
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+}
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+
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+
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+static int bcm54xx_shadow_read(struct e1000_hw *hw, u16 shadow)
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+{
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+ bcmphy_write(hw, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
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+ return MII_BCM54XX_SHD_DATA(bcmphy_read(hw, MII_BCM54XX_SHD));
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+ bcmphy_write(hw, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
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+ return MII_BCM54XX_SHD_DATA(bcmphy_read(hw, MII_BCM54XX_SHD));
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+}
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+
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+
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+static int bcm54xx_shadow_write(struct e1000_hw *hw, u16 shadow, u16 val)
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+ {
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+ return bcmphy_write(hw, MII_BCM54XX_SHD,
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+ MII_BCM54XX_SHD_WRITE |
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+ MII_BCM54XX_SHD_VAL(shadow) |
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+ MII_BCM54XX_SHD_DATA(val));
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+ }
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+
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+ /* Indirect register access functions for the Expansion Registers */
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+ static int bcm54xx_exp_read(struct e1000_hw *hw, u8 regnum)
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+ {
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+ int val;
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+
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+ val = bcmphy_write(hw, MII_BCM54XX_EXP_SEL, regnum);
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+ if (val < 0)
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+ return val;
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+
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+ val = bcmphy_read(hw, MII_BCM54XX_EXP_DATA);
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+
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+ /* Restore default value. It's O.K. if this write fails. */
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+ bcmphy_write(hw, MII_BCM54XX_EXP_SEL, 0);
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+
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+ return val;
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+ }
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+
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+ static int bcm54xx_exp_write(struct e1000_hw *hw, u16 regnum, u16 val)
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+ {
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+ int ret;
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+{
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+ return bcmphy_write(hw, MII_BCM54XX_SHD,
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+ MII_BCM54XX_SHD_WRITE |
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+ MII_BCM54XX_SHD_VAL(shadow) |
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+ MII_BCM54XX_SHD_DATA(val));
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+}
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+
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+static int bcm54xx_auxctl_write(struct e1000_hw *hw, u16 regnum, u16 val)
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+{
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+ return bcmphy_write(hw, MII_BCM54XX_AUX_CTL, (regnum | val));
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+}
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+
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+ ret = bcmphy_write(hw, MII_BCM54XX_EXP_SEL, regnum);
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+ if (ret < 0)
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+ return ret;
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+
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+ ret = bcmphy_write(hw, MII_BCM54XX_EXP_DATA, val);
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+
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+ /* Restore default value. It's O.K. if this write fails. */
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+ bcmphy_write(hw, MII_BCM54XX_EXP_SEL, 0);
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+
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+ return ret;
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+ }
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+
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+ static int bcm54xx_auxctl_write(struct e1000_hw *hw, u16 regnum, u16 val)
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+ {
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+ return bcmphy_write(hw, MII_BCM54XX_AUX_CTL, regnum | val);
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+ }
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+
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+static int bcm54xx_config_init(struct e1000_hw *hw)
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+ {
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+ int reg, err;
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+
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+ reg = bcmphy_read(hw, MII_BCM54XX_ECR);
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+ if (reg < 0)
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+ return reg;
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+
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+ /* Mask interrupts globally. */
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+ reg |= MII_BCM54XX_ECR_IM;
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+ err = bcmphy_write(hw, MII_BCM54XX_ECR, reg);
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+ if (err < 0)
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+ return err;
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+
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+ /* Unmask events we are interested in. */
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+ reg = ~(MII_BCM54XX_INT_DUPLEX |
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+ MII_BCM54XX_INT_SPEED |
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+ MII_BCM54XX_INT_LINK);
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+ err = bcmphy_write(hw, MII_BCM54XX_IMR, reg);
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+ if (err < 0)
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+ return err;
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+
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+ return 0;
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+ }
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+{
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+ int reg, err;
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+
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+void bcm54616s_linkup(struct e1000_hw *hw,int speed , int duplex)
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+ reg = bcmphy_read(hw, MII_BCM54XX_ECR);
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+ if (reg < 0)
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+ return reg;
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+
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+ /* Mask interrupts globally. */
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+ reg |= MII_BCM54XX_ECR_IM;
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+ err = bcmphy_write(hw, MII_BCM54XX_ECR, reg);
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+ if (err < 0)
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+ return err;
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+
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+ /* Unmask events we are interested in. */
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+ reg = ~(MII_BCM54XX_INT_DUPLEX |
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+ MII_BCM54XX_INT_SPEED |
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+ MII_BCM54XX_INT_LINK);
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+ err = bcmphy_write(hw, MII_BCM54XX_IMR, reg);
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+ if (err < 0)
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+ return err;
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+
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+ return 0;
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+}
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+
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+void bcm54616s_linkup(struct e1000_hw *hw, int speed, int duplex)
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+{
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+ u16 regval;
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+
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+ /* set speed and full duplex*/
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+ regval=bcmphy_read(hw,PHY_CONTROL);
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+ regval = bcmphy_read(hw,PHY_CONTROL);
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+ regval &= ~(MII_CR_SPEED_SELECT_MSB |
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+ MII_CR_SPEED_SELECT_LSB |
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+ MII_CR_FULL_DUPLEX);
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+
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+ regval &= ~(MII_CR_SPEED_SELECT_MSB | MII_CR_SPEED_SELECT_LSB |MII_CR_FULL_DUPLEX);
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+ switch(speed){
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+ case SPEED_10:
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+ regval |=MII_CR_SPEED_10;
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+ break;
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+ case SPEED_100:
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+ regval |=MII_CR_SPEED_100;
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+ break;
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+ case SPEED_1000:
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+ default:
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+ regval |=MII_CR_SPEED_1000;
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+ break;
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+ }
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+ switch(duplex){
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+ case FULL_DUPLEX:
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+ regval |=MII_CR_FULL_DUPLEX;
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+ break;
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+ switch(speed) {
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+ case SPEED_10:
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+ regval |= MII_CR_SPEED_10;
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+ break;
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+ case SPEED_100:
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+ regval |= MII_CR_SPEED_100;
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+ break;
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+ case SPEED_1000:
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+ default:
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+ regval |= MII_CR_SPEED_1000;
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+ break;
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+ }
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+
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+ bcmphy_write(hw,PHY_CONTROL,regval);
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+ switch(duplex) {
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+ case FULL_DUPLEX:
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+ regval |= MII_CR_FULL_DUPLEX;
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+ break;
|
||||
+ }
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+
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+ #if 0
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+ /* set Master auto and cap*/
|
||||
+ regval=bcmphy_read(hw,PHY_1000T_CTRL);
|
||||
+ regval &= ~(MII_GB_CTRL_MS_MAN);
|
||||
+ regval |= MII_ANA_ASF_802_3;
|
||||
+ regval |= MII_ANA_HD_10;
|
||||
+ regval |= MII_ANA_HD_100;
|
||||
+ regval |= MII_ANA_FD_10;
|
||||
+ regval |= MII_ANA_FD_100;
|
||||
+ regval |= MII_ANA_ASYM_PAUSE;
|
||||
+ regval |= MII_ANA_PAUSE | MII_ANA_ASYM_PAUSE;
|
||||
+ regval |= MII_ANA_PAUSE;
|
||||
+ bcmphy_write(hw,PHY_1000T_CTRL,regval);
|
||||
+ bcmphy_write(hw,PHY_CONTROL, regval);
|
||||
+
|
||||
+ regval=bcmphy_read(hw,PHY_CONTROL);
|
||||
+ regval |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
|
||||
+ bcmphy_write(hw,PHY_CONTROL,regval);
|
||||
+ #endif
|
||||
+
|
||||
+ regval=bcmphy_read(hw,PHY_CONTROL);
|
||||
+ regval &=~(MII_CR_ISOLATE);
|
||||
+ bcmphy_write(hw,PHY_CONTROL,regval);
|
||||
+ regval = bcmphy_read(hw, PHY_CONTROL);
|
||||
+ regval &= ~(MII_CR_ISOLATE);
|
||||
+ bcmphy_write(hw, PHY_CONTROL, regval);
|
||||
+}
|
||||
+
|
||||
+int bcm54616_config_init(struct e1000_hw *hw)
|
||||
+ {
|
||||
+int bcm54616s_config_init(struct e1000_hw *hw)
|
||||
+{
|
||||
+ int err, reg;
|
||||
+ u16 regval;
|
||||
+ int i;
|
||||
+
|
||||
+ /* reset PHY */
|
||||
+ regval=1<<15;
|
||||
+ bcmphy_write(hw,PHY_CONTROL,regval);
|
||||
+ regval = (1<<15);
|
||||
+ bcmphy_write(hw, PHY_CONTROL, regval);
|
||||
+
|
||||
+ mdelay(10);
|
||||
+
|
||||
+ /* disable Power down and iso */
|
||||
+ regval=bcmphy_read(hw,PHY_CONTROL);
|
||||
+ regval &=~(MII_CR_POWER_DOWN|MII_CR_ISOLATE);
|
||||
+ bcmphy_write(hw,PHY_CONTROL,regval);
|
||||
+ regval = bcmphy_read(hw,PHY_CONTROL);
|
||||
+ regval &= ~(MII_CR_POWER_DOWN | MII_CR_ISOLATE);
|
||||
+ bcmphy_write(hw, PHY_CONTROL, regval);
|
||||
+
|
||||
+ /* disable suport I */
|
||||
+ /*0000 0100 1100 0010 */
|
||||
+ bcm54xx_auxctl_write(hw,0,0x04c2);
|
||||
+ bcm54xx_auxctl_write(hw, 0, 0x04c2);
|
||||
+
|
||||
+ regval=bcmphy_read(hw,MII_BCM54XX_AUX_CTL);
|
||||
+ regval = bcmphy_read(hw, MII_BCM54XX_AUX_CTL);
|
||||
+
|
||||
+ /* set 1000base-T */
|
||||
+ regval=bcmphy_read(hw,PHY_1000T_CTRL);
|
||||
+ regval |=CR_1000T_FD_CAPS | CR_1000T_REPEATER_DTE;
|
||||
+ bcmphy_write(hw,PHY_1000T_CTRL,regval);
|
||||
+ regval = bcmphy_read(hw, PHY_1000T_CTRL);
|
||||
+ regval |= (CR_1000T_FD_CAPS | CR_1000T_REPEATER_DTE);
|
||||
+ bcmphy_write(hw, PHY_1000T_CTRL, regval);
|
||||
+
|
||||
+ /* set ctrl */
|
||||
+ regval= MII_CR_SPEED_1000|MII_CR_FULL_DUPLEX|MII_CR_SPEED_SELECT_MSB;
|
||||
+ bcmphy_write(hw,PHY_CONTROL,regval);
|
||||
+
|
||||
+ regval = (MII_CR_SPEED_1000 |
|
||||
+ MII_CR_FULL_DUPLEX |
|
||||
+ MII_CR_SPEED_SELECT_MSB);
|
||||
+ bcmphy_write(hw, PHY_CONTROL, regval);
|
||||
+
|
||||
+ /* Setup read from auxilary control shadow register 7 */
|
||||
+ bcmphy_write(hw, MII_BCM54XX_AUX_CTL,MII_BCM54XX_AUX_CTL_ENCODE(7));
|
||||
+
|
||||
+ bcmphy_write(hw, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUX_CTL_ENCODE(7));
|
||||
+
|
||||
+ /* Read Misc Control register */
|
||||
+ reg = (bcmphy_read(hw, MII_BCM54XX_AUX_CTL) & 0x8FFF) | 0x8010;
|
||||
+ reg = ((bcmphy_read(hw, MII_BCM54XX_AUX_CTL) & 0x8FFF) | 0x8010);
|
||||
+ bcmphy_write(hw, MII_BCM54XX_AUX_CTL, reg);
|
||||
+
|
||||
+
|
||||
+ /* Enable auto-detect and copper prefer */
|
||||
+ bcm54xx_shadow_write(hw,BCM54XX_SHD_AUTODETECT,0x31);
|
||||
+ bcm54xx_shadow_write(hw, BCM54XX_SHD_AUTODETECT, 0x31);
|
||||
+
|
||||
+ err = bcm54xx_config_init(hw);
|
||||
+
|
||||
+ /* set link parner */
|
||||
+ regval = MII_ANA_ASF_802_3;
|
||||
+ regval = MII_ANA_ASF_802_3;
|
||||
+ regval |= MII_ANA_HD_10;
|
||||
+ regval |= MII_ANA_HD_100;
|
||||
+ regval |= MII_ANA_FD_10;
|
||||
+ regval |= MII_ANA_FD_100;
|
||||
+ regval |= MII_ANA_ASYM_PAUSE;
|
||||
+ regval |= MII_ANA_PAUSE | MII_ANA_ASYM_PAUSE;
|
||||
+ regval |= (MII_ANA_PAUSE | MII_ANA_ASYM_PAUSE);
|
||||
+ regval |= MII_ANA_PAUSE;
|
||||
+ bcmphy_write(hw, PHY_AUTONEG_ADV, reg);
|
||||
+
|
||||
+
|
||||
+ i=0;
|
||||
+ while (1) {
|
||||
+ regval = bcm54xx_shadow_read(hw,BCM54XX_SHD_MODE);
|
||||
+ if(regval & BCM54XX_SHD_MODE_SER)
|
||||
+ if (regval & BCM54XX_SHD_MODE_SER)
|
||||
+ break;
|
||||
+ if (i++ > 500) {
|
||||
+ //printk("SERDES no link %x\n",regval);
|
||||
@@ -357,19 +207,18 @@ diff -Nu a/drivers/net/ethernet/intel/igb/bcm_phy.c b/drivers/net/ethernet/intel
|
||||
+ mdelay(1); /* 1 ms */
|
||||
+ }
|
||||
+ return err;
|
||||
+ }
|
||||
+
|
||||
+}
|
||||
diff -Nu a/drivers/net/ethernet/intel/igb/e1000_82575.c b/drivers/net/ethernet/intel/igb/e1000_82575.c
|
||||
--- a/drivers/net/ethernet/intel/igb/e1000_82575.c 2017-05-09 23:52:56.728565000 -0700
|
||||
+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c 2017-05-10 01:58:36.796075944 -0700
|
||||
--- a/drivers/net/ethernet/intel/igb/e1000_82575.c 2017-06-20 16:44:29.000000000 +0800
|
||||
+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c 2017-06-20 17:00:52.000000000 +0800
|
||||
@@ -317,6 +317,10 @@
|
||||
break;
|
||||
case BCM54616_E_PHY_ID:
|
||||
phy->type = e1000_phy_bcm54616;
|
||||
+ //phy->ops.check_polarity = e1000_check_polarity_bcm;
|
||||
+ phy->ops.get_info = igb_get_phy_info_bcm;
|
||||
+ phy->ops.check_polarity = NULL;
|
||||
+ phy->ops.get_info = igb_get_phy_info_bcm;
|
||||
+ phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_bcm;
|
||||
+ bcm54616_config_init(hw);
|
||||
+ bcm54616s_config_init(hw);
|
||||
break;
|
||||
case BCM50210S_E_PHY_ID:
|
||||
break;
|
||||
@@ -382,32 +231,20 @@ diff -Nu a/drivers/net/ethernet/intel/igb/e1000_82575.c b/drivers/net/ethernet/i
|
||||
case e1000_phy_bcm5461s:
|
||||
break;
|
||||
diff -Nu a/drivers/net/ethernet/intel/igb/e1000_82575.h b/drivers/net/ethernet/intel/igb/e1000_82575.h
|
||||
--- a/drivers/net/ethernet/intel/igb/e1000_82575.h 2017-05-09 23:52:56.608565000 -0700
|
||||
+++ b/drivers/net/ethernet/intel/igb/e1000_82575.h 2017-01-12 01:49:16.214072900 -0800
|
||||
--- a/drivers/net/ethernet/intel/igb/e1000_82575.h 2017-06-20 16:44:27.000000000 +0800
|
||||
+++ b/drivers/net/ethernet/intel/igb/e1000_82575.h 2017-06-20 17:00:57.000000000 +0800
|
||||
@@ -25,6 +25,8 @@
|
||||
#ifndef _E1000_82575_H_
|
||||
#define _E1000_82575_H_
|
||||
|
||||
+extern void bcm54616s_linkup(struct e1000_hw *hw,int speed , int duplex);
|
||||
+extern int bcm54616_config_init(struct e1000_hw *hw);
|
||||
+extern int bcm54616s_config_init(struct e1000_hw *hw);
|
||||
#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
|
||||
(ID_LED_DEF1_DEF2 << 8) | \
|
||||
(ID_LED_DEF1_DEF2 << 4) | \
|
||||
diff -Nu a/drivers/net/ethernet/intel/igb/e1000_defines.h b/drivers/net/ethernet/intel/igb/e1000_defines.h
|
||||
--- a/drivers/net/ethernet/intel/igb/e1000_defines.h 2017-05-09 23:52:56.732565000 -0700
|
||||
+++ b/drivers/net/ethernet/intel/igb/e1000_defines.h 2017-05-10 01:57:15.622221274 -0700
|
||||
@@ -1186,7 +1186,7 @@
|
||||
#define IGP04E1000_E_PHY_ID 0x02A80391
|
||||
#define BCM54616_E_PHY_ID 0x3625D10
|
||||
#define BCM5461S_PHY_ID 0x002060C0
|
||||
-#define M88_VENDOR 0x0141
|
||||
+#define M88_VENDOR 0x0141
|
||||
#define BCM50210S_E_PHY_ID 0x600d8590
|
||||
|
||||
/* M88E1000 Specific Registers */
|
||||
diff -Nu a/drivers/net/ethernet/intel/igb/e1000_phy.c b/drivers/net/ethernet/intel/igb/e1000_phy.c
|
||||
--- a/drivers/net/ethernet/intel/igb/e1000_phy.c 2017-05-09 23:52:56.672565000 -0700
|
||||
+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c 2017-01-12 01:57:04.376530600 -0800
|
||||
--- a/drivers/net/ethernet/intel/igb/e1000_phy.c 2017-06-20 16:44:27.000000000 +0800
|
||||
+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c 2017-06-20 17:01:05.000000000 +0800
|
||||
@@ -1187,6 +1187,19 @@
|
||||
return E1000_SUCCESS;
|
||||
}
|
||||
@@ -419,9 +256,9 @@ diff -Nu a/drivers/net/ethernet/intel/igb/e1000_phy.c b/drivers/net/ethernet/int
|
||||
+ u16 phy_data;
|
||||
+
|
||||
+ ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
|
||||
+ phy_data &=~(MII_CR_ISOLATE);
|
||||
+ phy_data &= ~(MII_CR_ISOLATE);
|
||||
+ ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
|
||||
+
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
@@ -445,15 +282,15 @@ diff -Nu a/drivers/net/ethernet/intel/igb/e1000_phy.c b/drivers/net/ethernet/int
|
||||
+
|
||||
+ e1000_phy_force_speed_duplex_setup(hw, &phy_data);
|
||||
+
|
||||
+ phy_data &=~(MII_CR_POWER_DOWN|MII_CR_ISOLATE);
|
||||
+ phy_data &= ~(MII_CR_POWER_DOWN | MII_CR_ISOLATE);
|
||||
+ ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
|
||||
+ if (ret_val)
|
||||
+ return ret_val;
|
||||
+
|
||||
+ /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
|
||||
+ * forced whenever speed and duplex are forced.
|
||||
+ */
|
||||
+ #if 0
|
||||
+ * forced whenever speed and duplex are forced.
|
||||
+ */
|
||||
+ #if 0
|
||||
+ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
|
||||
+ if (ret_val)
|
||||
+ return ret_val;
|
||||
@@ -466,7 +303,7 @@ diff -Nu a/drivers/net/ethernet/intel/igb/e1000_phy.c b/drivers/net/ethernet/int
|
||||
+ return ret_val;
|
||||
+
|
||||
+ hw_dbg("IGP PSCR: %X\n", phy_data);
|
||||
+ #endif
|
||||
+ #endif
|
||||
+ udelay(1);
|
||||
+
|
||||
+ if (phy->autoneg_wait_to_complete) {
|
||||
@@ -491,41 +328,16 @@ diff -Nu a/drivers/net/ethernet/intel/igb/e1000_phy.c b/drivers/net/ethernet/int
|
||||
/**
|
||||
* e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
|
||||
* @hw: pointer to the HW structure
|
||||
@@ -2146,6 +2215,25 @@
|
||||
return ret_val;
|
||||
}
|
||||
@@ -2614,6 +2683,29 @@
|
||||
}
|
||||
|
||||
+s32 e1000_check_polarity_bcm(struct e1000_hw *hw)
|
||||
+{
|
||||
+ struct e1000_phy_info *phy = &hw->phy;
|
||||
+ s32 ret_val;
|
||||
+ u16 data;
|
||||
+
|
||||
+ #if 0
|
||||
+ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
|
||||
+
|
||||
+ if (!ret_val)
|
||||
+ phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
|
||||
+ ? e1000_rev_polarity_reversed
|
||||
+ : e1000_rev_polarity_normal);
|
||||
+ #endif
|
||||
+ ret_val=0;
|
||||
+ phy->cable_polarity =e1000_rev_polarity_normal;
|
||||
+ return ret_val;
|
||||
return ret_val;
|
||||
+}
|
||||
+
|
||||
/**
|
||||
* igb_e1000_check_polarity_igp - Checks the polarity.
|
||||
* @hw: pointer to the HW structure
|
||||
@@ -2616,6 +2704,38 @@
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
+s32 igb_get_phy_info_bcm(struct e1000_hw *hw)
|
||||
+{
|
||||
+ struct e1000_phy_info *phy = &hw->phy;
|
||||
+ s32 ret_val;
|
||||
+ u16 phy_data;
|
||||
+ s32 ret_val;
|
||||
+ bool link;
|
||||
+
|
||||
+ if (phy->media_type != e1000_media_type_copper) {
|
||||
@@ -542,28 +354,17 @@ diff -Nu a/drivers/net/ethernet/intel/igb/e1000_phy.c b/drivers/net/ethernet/int
|
||||
+ return -E1000_ERR_CONFIG;
|
||||
+ }
|
||||
+
|
||||
+ #if 0
|
||||
+ phy->polarity_correction =true;
|
||||
+ phy->is_mdix = true;
|
||||
+ phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
|
||||
+ phy->local_rx = e1000_1000t_rx_status_undefined;
|
||||
+ phy->remote_rx = e1000_1000t_rx_status_undefined;
|
||||
+ ret_val=0;
|
||||
+ #endif
|
||||
+ return ret_val;
|
||||
+}
|
||||
+
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_get_phy_info_igp - Retrieve igp PHY information
|
||||
* @hw: pointer to the HW structure
|
||||
diff -Nu a/drivers/net/ethernet/intel/igb/e1000_phy.h b/drivers/net/ethernet/intel/igb/e1000_phy.h
|
||||
--- a/drivers/net/ethernet/intel/igb/e1000_phy.h 2017-05-09 23:52:56.672565000 -0700
|
||||
+++ b/drivers/net/ethernet/intel/igb/e1000_phy.h 2017-01-12 01:58:07.074761900 -0800
|
||||
@@ -99,6 +99,10 @@
|
||||
--- a/drivers/net/ethernet/intel/igb/e1000_phy.h 2017-06-20 16:44:27.000000000 +0800
|
||||
+++ b/drivers/net/ethernet/intel/igb/e1000_phy.h 2017-06-20 17:01:24.000000000 +0800
|
||||
@@ -99,6 +99,9 @@
|
||||
s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
|
||||
bool line_override);
|
||||
bool e1000_is_mphy_ready(struct e1000_hw *hw);
|
||||
+s32 igb_check_polarity_bcm(struct e1000_hw *hw);
|
||||
+s32 igb_copper_link_setup_bcm(struct e1000_hw *hw);
|
||||
+s32 igb_phy_force_speed_duplex_bcm(struct e1000_hw *hw);
|
||||
+s32 igb_get_phy_info_bcm(struct e1000_hw *hw);
|
||||
@@ -571,8 +372,8 @@ diff -Nu a/drivers/net/ethernet/intel/igb/e1000_phy.h b/drivers/net/ethernet/int
|
||||
#define E1000_MAX_PHY_ADDR 8
|
||||
|
||||
diff -Nu a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c
|
||||
--- a/drivers/net/ethernet/intel/igb/igb_main.c 2017-05-09 23:52:56.676565000 -0700
|
||||
+++ b/drivers/net/ethernet/intel/igb/igb_main.c 2017-01-12 02:04:11.728846300 -0800
|
||||
--- a/drivers/net/ethernet/intel/igb/igb_main.c 2017-06-20 16:44:27.000000000 +0800
|
||||
+++ b/drivers/net/ethernet/intel/igb/igb_main.c 2017-06-20 17:01:29.000000000 +0800
|
||||
@@ -4814,6 +4814,14 @@
|
||||
&adapter->link_speed,
|
||||
&adapter->link_duplex);
|
||||
@@ -589,8 +390,8 @@ diff -Nu a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/inte
|
||||
/* Links status message must follow this format */
|
||||
netdev_info(netdev,
|
||||
diff -Nu a/drivers/net/ethernet/intel/igb/Makefile b/drivers/net/ethernet/intel/igb/Makefile
|
||||
--- a/drivers/net/ethernet/intel/igb/Makefile 2017-05-09 23:52:56.600565000 -0700
|
||||
+++ b/drivers/net/ethernet/intel/igb/Makefile 2017-01-12 02:06:51.790832900 -0800
|
||||
--- a/drivers/net/ethernet/intel/igb/Makefile 2017-06-20 16:44:27.000000000 +0800
|
||||
+++ b/drivers/net/ethernet/intel/igb/Makefile 2017-06-20 17:01:34.000000000 +0800
|
||||
@@ -35,4 +35,4 @@
|
||||
e1000_mac.o e1000_nvm.o e1000_phy.o e1000_mbx.o \
|
||||
e1000_i210.o igb_ptp.o igb_hwmon.o \
|
||||
|
||||
Reference in New Issue
Block a user