WIFI-14603 Default TC fq_codel queue on GRE cause low GRE RX throughput

Signed-off-by: Ken <xshi@actiontec.com>

.github/workflows/build-dev.yml

@@ -21,7 +21,7 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        target: [ 'cig_wf186h', 'cig_wf186w', 'cig_wf188n', 'cig_wf189', 'cig_wf196', 'cig_wf196', 'cybertan_eww631-a1', 'cybertan_eww631-b1', 'sonicfi_rap630w-312g', 'sonicfi_rap63xc-211g', 'sonicfi_rap630c-311g', 'sonicfi_rap630w-311g', 'sonicfi_rap630w-211g', 'sonicfi_rap650c', 'sonicfi_rap7110c-341x', 'sonicfi_rap750e-h', 'sonicfi_rap750w-311a', 'edgecore_eap101', 'edgecore_eap102', 'edgecore_eap104', 'edgecore_eap105', 'edgecore_eap111', 'edgecore_eap112', 'edgecore_oap101', 'edgecore_oap101-6e', 'edgecore_oap101e', 'edgecore_oap101e-6e', 'edgecore_oap103', 'hfcl_ion4xe', 'hfcl_ion4xi', 'hfcl_ion4x', 'hfcl_ion4x_2', 'hfcl_ion4x_3', 'hfcl_ion4xi_w', 'hfcl_ion4x_w', 'indio_um-305ax', 'senao_iap4300m', 'senao_iap2300m', 'senao_jeap6500', 'udaya_a6-id2', 'udaya_a6-od2', 'yuncore_ax820', 'yuncore_ax840', 'yuncore_fap640', 'yuncore_fap650', 'yuncore_fap655', 'emplus_wap588m' ]
+        target: [ 'cig_wf186h', 'cig_wf186w', 'cig_wf188n', 'cig_wf189', 'cig_wf196', 'cig_wf196', 'cybertan_eww631-a1', 'cybertan_eww631-b1', 'sonicfi_rap630w-312g', 'sonicfi_rap63xc-211g', 'sonicfi_rap630c-311g', 'sonicfi_rap630w-311g', 'sonicfi_rap630w-211g', 'sonicfi_rap650c', 'sonicfi_rap7110c-341x', 'sonicfi_rap750e-h', 'sonicfi_rap750w-311a', 'edgecore_eap101', 'edgecore_eap102', 'edgecore_eap104', 'edgecore_eap105', 'edgecore_eap111', 'edgecore_eap112', 'edgecore_oap101', 'edgecore_oap101-6e', 'edgecore_oap101e', 'edgecore_oap101e-6e', 'edgecore_oap103', 'hfcl_ion4xe', 'hfcl_ion4xi', 'hfcl_ion4x', 'hfcl_ion4x_2', 'hfcl_ion4x_3', 'hfcl_ion4xi_w', 'hfcl_ion4x_w', 'indio_um-305ax', 'senao_iap4300m', 'senao_iap2300m', 'senao_jeap6500', 'udaya_a6-id2', 'udaya_a6-od2', 'yuncore_ax820', 'yuncore_ax840', 'yuncore_fap640', 'yuncore_fap650', 'yuncore_fap655', 'emplus_wap588m', 'zyxel_nwa130be' ]
     steps:
     - uses: actions/checkout@v3
 

feeds/mediatek-sdk/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-edgecore-eap111.dts

@@ -169,7 +169,8 @@
 		compatible = "mediatek,eth-mac";
 		reg = <0>;
 		phy-mode = "sgmii";
-		phy-handle = <&phy1>;      // add phy handler
+		phy-handle = <&phy30>;
+		phy-handle2 = <&phy1>;
 		mtd-mac-address = <&factory 0x24>;
 	};
 
@@ -181,9 +182,9 @@
 		mtd-mac-address = <&factory 0x2a>;
 	};
 
-        mdio: mdio-bus {
-                #address-cells = <1>;
-                #size-cells = <0>;
+	mdio: mdio-bus {
+		#address-cells = <1>;
+		#size-cells = <0>;
 
 		phy0: ethernet-phy@0 {
 			compatible = "ethernet-phy-id03a2.9461";
@@ -193,6 +194,16 @@
 			nvmem-cell-names = "phy-cal-data";
 		};
 
+		phy30: ethernet-phy@30 { // AN8801SB
+			compatible = "ethernet-phy-idc0ff.0421";
+			reg = <30>; //0x1e
+			phy-mode = "sgmii";
+			full-duplex;
+			pause;
+			airoha,surge = <1>;
+			airoha,polarity = <2>;
+		};
+
 		phy1: ethernet-phy@1 {
 			compatible = "ethernet-phy-id03a2.9471";
 			reg = <24>;            // set phy address to 0x18
@@ -200,9 +211,8 @@
 			reset-assert-us = <600>;
 			reset-deassert-us = <20000>;
 			phy-mode = "sgmii";
-    };
-
-        };
+		};
+	};
 };
 
 &hnat {

feeds/mediatek-sdk/mediatek/files-5.4/drivers/net/phy/an8801.c

@@ -113,7 +113,6 @@ static const struct AIR_LED_CFG_T led_cfg_dlt[MAX_LED_SIZE] = {
 	/* LED2 */
 	{LED_ENABLE, AIR_LED_GPIO9, AIR_ACTIVE_LOW,  AIR_LED2_ON, AIR_LED2_BLK},
 };
-
 static const u16 led_blink_cfg_dlt = AIR_LED_BLK_DUR_64M;
 /* RGMII delay */
 static const u8 rxdelay_force = FALSE;
@@ -140,7 +139,6 @@ static int __air_buckpbus_reg_write(struct phy_device *phydev, u32 addr,
 	err |= mbus->write(mbus, phy_addr, 0x13, (u16)(data >> 16));
 	err |= mbus->write(mbus, phy_addr, 0x14, (u16)(data & 0xffff));
 	err |= mbus->write(mbus, phy_addr, 0x1F, 0);
-
 	return err;
 }
 
@@ -167,6 +165,41 @@ static u32 __air_buckpbus_reg_read(struct phy_device *phydev, u32 addr)
 	return data;
 }
 
+static u32 __air_buckpbus_reg_modify(struct phy_device *phydev, u32 addr,
+					u32 mask, u32 set)
+{
+	int err = 0;
+	u32 data_h, data_l, data_old, data_new;
+	int phy_addr = phydev_phy_addr(phydev);
+	struct mii_bus *mbus = phydev_mdiobus(phydev);
+
+	err = mbus->write(mbus, phy_addr, 0x1F, 4);
+	err |= mbus->write(mbus, phy_addr, 0x10, 0);
+	err |= mbus->write(mbus, phy_addr, 0x15, (u16)(addr >> 16));
+	err |= mbus->write(mbus, phy_addr, 0x16, (u16)(addr & 0xffff));
+	data_h = mbus->read(mbus, phy_addr, 0x17);
+	data_l = mbus->read(mbus, phy_addr, 0x18);
+	if (err < 0) {
+		mbus->write(mbus, phy_addr, 0x1F, 0);
+		return INVALID_DATA;
+	}
+
+	data_old = ((data_h & 0xffff) << 16) | (data_l & 0xffff);
+	data_new = (data_old & ~mask) | set;
+	if (data_new == data_old) {
+		mbus->write(mbus, phy_addr, 0x1F, 0);
+		return 0;
+	}
+
+	err |= mbus->write(mbus, phy_addr, 0x11, (u16)(addr >> 16));
+	err |= mbus->write(mbus, phy_addr, 0x12, (u16)(addr & 0xffff));
+	err |= mbus->write(mbus, phy_addr, 0x13, (u16)(data_new >> 16));
+	err |= mbus->write(mbus, phy_addr, 0x14, (u16)(data_new & 0xffff));
+	err |= mbus->write(mbus, phy_addr, 0x1F, 0);
+
+	return err;
+}
+
 static int air_buckpbus_reg_write(struct phy_device *phydev, u32 addr, u32 data)
 {
 	int err = 0;
@@ -189,82 +222,18 @@ static u32 air_buckpbus_reg_read(struct phy_device *phydev, u32 addr)
 	return data;
 }
 
-static int __an8801_cl45_write(struct phy_device *phydev, int devad, u16 reg,
-				u16 val)
-{
-	u32 addr = (AN8801_EPHY_ADDR | AN8801_CL22 | (devad << 18) |
-				(reg << 2));
-
-	return __air_buckpbus_reg_write(phydev, addr, val);
-}
-
-static int __an8801_cl45_read(struct phy_device *phydev, int devad, u16 reg)
-{
-	u32 addr = (AN8801_EPHY_ADDR | AN8801_CL22 | (devad << 18) |
-				(reg << 2));
-
-	return __air_buckpbus_reg_read(phydev, addr);
-}
-
-int __an8801_modify_cl45_changed(struct phy_device *phydev, int devad, u32 regnum,
-				u16 mask, u16 set)
-{
-	int new, ret;
-
-	ret = __an8801_cl45_read(phydev, devad, regnum);
-	if (ret < 0)
-		return ret;
-
-	new = (ret & ~mask) | set;
-	if (new == ret)
-		return 0;
-
-	ret = __an8801_cl45_write(phydev, devad, regnum, new);
-
-	return ret < 0 ? ret : 1;
-}
-
-static int an8801_modify_cl45_changed(struct phy_device *phydev, int devad,
-				u32 regnum, u16 mask, u16 set)
+static int air_buckpbus_reg_modify(struct phy_device *phydev, u32 addr,
+					u32 mask, u32 set)
 {
 	int err = 0;
 
 	mdiobus_lock(phydev);
-	err = __an8801_modify_cl45_changed(phydev, devad, regnum, mask, set);
+	err = __air_buckpbus_reg_modify(phydev, addr, mask, set);
 	mdiobus_unlock(phydev);
 
 	return err;
 }
 
-static int an8801_cl45_write(struct phy_device *phydev, int devad, u16 reg,
-			      u16 val)
-{
-	int err = 0;
-
-	mdiobus_lock(phydev);
-	err = __an8801_cl45_write(phydev, devad, reg, val);
-	mdiobus_unlock(phydev);
-
-	return err;
-}
-
-static int an8801_cl45_read(struct phy_device *phydev, int devad, u16 reg,
-			     u16 *read_data)
-{
-	int data = 0;
-
-	mdiobus_lock(phydev);
-	data = __an8801_cl45_read(phydev, devad, reg);
-	mdiobus_unlock(phydev);
-
-	if (data == INVALID_DATA)
-		return -EINVAL;
-
-	*read_data = data;
-
-	return 0;
-}
-
 static int air_sw_reset(struct phy_device *phydev)
 {
 	u32 reg_value;
@@ -298,50 +267,36 @@ static int an8801_led_set_usr_def(struct phy_device *phydev, u8 entity,
 
 	on_evt |= LED_ON_EN;
 
-	err = an8801_cl45_write(phydev, 0x1f, LED_ON_CTRL(entity), on_evt);
+	err = phy_write_mmd(phydev, 0x1f, LED_ON_CTRL(entity), on_evt);
 	if (err)
 		return -1;
 
-	return an8801_cl45_write(phydev, 0x1f, LED_BLK_CTRL(entity), blk_evt);
+	return phy_write_mmd(phydev, 0x1f, LED_BLK_CTRL(entity), blk_evt);
 }
 
 static int an8801_led_set_mode(struct phy_device *phydev, u8 mode)
 {
-	int err;
-	u16 data;
-
-	err = an8801_cl45_read(phydev, 0x1f, LED_BCR, &data);
-	if (err)
-		return -1;
-
 	switch (mode) {
 	case AIR_LED_MODE_DISABLE:
-		data &= ~LED_BCR_EXT_CTRL;
-		data &= ~LED_BCR_MODE_MASK;
-		data |= LED_BCR_MODE_DISABLE;
-		break;
+		return phy_modify_mmd(phydev, 0x1f, LED_BCR,
+						(LED_BCR_EXT_CTRL | LED_BCR_CLK_EN),
+						0x0);
 	case AIR_LED_MODE_USER_DEFINE:
-		data |= (LED_BCR_EXT_CTRL | LED_BCR_CLK_EN);
+		return phy_modify_mmd(phydev, 0x1f, LED_BCR,
+						(LED_BCR_EXT_CTRL | LED_BCR_CLK_EN),
+						(LED_BCR_EXT_CTRL | LED_BCR_CLK_EN));
+	default:
 		break;
 	}
-	return an8801_cl45_write(phydev, 0x1f, LED_BCR, data);
+	dev_err(phydev_dev(phydev),
+				"LED mode %d is not supported\n", mode);
+	return -EINVAL;
 }
 
 static int an8801_led_set_state(struct phy_device *phydev, u8 entity, u8 state)
 {
-	u16 data;
-	int err;
-
-	err = an8801_cl45_read(phydev, 0x1f, LED_ON_CTRL(entity), &data);
-	if (err)
-		return err;
-
-	if (state)
-		data |= LED_ON_EN;
-	else
-		data &= ~LED_ON_EN;
-
-	return an8801_cl45_write(phydev, 0x1f, LED_ON_CTRL(entity), data);
+	return phy_modify_mmd(phydev, 0x1f, LED_ON_CTRL(entity), LED_ON_EN,
+					(state) ? LED_ON_EN : 0x0);
 }
 
 static int an8801_led_init(struct phy_device *phydev)
@@ -352,12 +307,12 @@ static int an8801_led_init(struct phy_device *phydev)
 	u32 data;
 	u16 led_blink_cfg = priv->led_blink_cfg;
 
-	ret = an8801_cl45_write(phydev, 0x1f, LED_BLK_DUR,
+	ret = phy_write_mmd(phydev, 0x1f, LED_BLK_DUR,
 				 LED_BLINK_DURATION(led_blink_cfg));
 	if (ret < 0)
 		return ret;
 
-	ret = an8801_cl45_write(phydev, 0x1f, LED_ON_DUR,
+	ret = phy_write_mmd(phydev, 0x1f, LED_ON_DUR,
 				 (LED_BLINK_DURATION(led_blink_cfg) >> 1));
 	if (ret < 0)
 		return ret;
@@ -406,6 +361,56 @@ static int an8801_led_init(struct phy_device *phydev)
 	return 0;
 }
 
+static int an8801_ack_interrupt(struct phy_device *phydev)
+{
+	u32 reg_val = 0;
+
+	air_buckpbus_reg_write(phydev, 0x10285404, 0x102);
+	reg_val = air_buckpbus_reg_read(phydev, 0x10285400);
+	air_buckpbus_reg_write(phydev, 0x10285400, 0x0);
+	air_buckpbus_reg_write(phydev, 0x10285400, reg_val | 0x10);
+	air_buckpbus_reg_write(phydev, 0x10285404, 0x12);
+	air_buckpbus_reg_write(phydev, 0x10285704, 0x1f);
+	return 0;
+}
+
+static int an8801_config_intr(struct phy_device *phydev)
+{
+	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+		air_buckpbus_reg_write(phydev, 0x1000007c, BIT(AIR_INTERRUPT_GPIO) << 16);
+		air_buckpbus_reg_modify(phydev, 0x10285700, 0x1, 0x1);
+	} else {
+		air_buckpbus_reg_write(phydev, 0x1000007c, 0x0);
+		air_buckpbus_reg_modify(phydev, 0x10285700, 0x1, 0x0);
+	}
+	an8801_ack_interrupt(phydev);
+	return 0;
+}
+
+static int an8801_did_interrupt(struct phy_device *phydev)
+{
+	u32 reg_val = 0;
+
+	reg_val = air_buckpbus_reg_read(phydev, 0x10285704);
+
+	if (reg_val & 0x11)
+		return 1;
+
+	return 0;
+}
+
+#if (KERNEL_VERSION(5, 11, 0) < LINUX_VERSION_CODE)
+static irqreturn_t an8801_handle_interrupt(struct phy_device *phydev)
+{
+	if (!an8801_did_interrupt(phydev))
+		return IRQ_NONE;
+
+	an8801_ack_interrupt(phydev);
+	phy_trigger_machine(phydev);
+	return IRQ_HANDLED;
+}
+#endif
+
 static int findClosestNumber(const u16 *arr, u16 size, u16 target)
 {
 	int left = 0, right = size - 1;
@@ -431,77 +436,77 @@ static int findClosestNumber(const u16 *arr, u16 size, u16 target)
 static int an8801sb_i2mpb_config(struct phy_device *phydev)
 {
 	int ret = 0;
-	u16 cl45_value = 0, temp_cl45 = 0, set = 0;
+	u16 cl45_value = 0, temp_cl45 = 0;
 	u16 mask = 0;
 
-	ret = an8801_cl45_read(phydev, MMD_DEV_VSPEC1, 0x12, &cl45_value);
+	cl45_value = phy_read_mmd(phydev, MMD_DEV_VSPEC1, 0x12);
 	dev_dbg(phydev_dev(phydev), "%s:%d cl45_value 0x%x!\n", __func__, __LINE__, cl45_value);
 	cl45_value = (cl45_value & GENMASK(15, 10)) + (6 << 10);
-	ret = an8801_modify_cl45_changed(phydev, MMD_DEV_VSPEC1, 0x12, GENMASK(15, 10), cl45_value);
+	ret = phy_modify_mmd(phydev, MMD_DEV_VSPEC1, 0x12, GENMASK(15, 10), cl45_value);
 	if (ret < 0)
 		return ret;
-	ret = an8801_cl45_read(phydev, MMD_DEV_VSPEC1, 0x16, &temp_cl45);
+	temp_cl45 = phy_read_mmd(phydev, MMD_DEV_VSPEC1, 0x16);
 	dev_dbg(phydev_dev(phydev), "%s:%d cl45_value 0x%x!\n", __func__, __LINE__, temp_cl45);
 	mask = GENMASK(15, 10) | GENMASK(5, 0);
 	cl45_value = (temp_cl45 & GENMASK(15, 10)) + (9 << 10);
 	cl45_value = ((temp_cl45 & GENMASK(5, 0)) + 6) | cl45_value;
-	ret = an8801_modify_cl45_changed(phydev, MMD_DEV_VSPEC1, 0x16, mask, cl45_value);
+	ret = phy_modify_mmd(phydev, MMD_DEV_VSPEC1, 0x16, mask, cl45_value);
 	if (ret < 0)
 		return ret;
-	ret = an8801_cl45_read(phydev, MMD_DEV_VSPEC1, 0x17, &cl45_value);
+	cl45_value = phy_read_mmd(phydev, MMD_DEV_VSPEC1, 0x17);
 	dev_dbg(phydev_dev(phydev), "%s:%d cl45_value 0x%x!\n", __func__, __LINE__, cl45_value);
 	cl45_value = (cl45_value & GENMASK(13, 8)) + (6 << 8);
-	ret = an8801_modify_cl45_changed(phydev, MMD_DEV_VSPEC1, 0x17, GENMASK(13, 8), cl45_value);
+	ret = phy_modify_mmd(phydev, MMD_DEV_VSPEC1, 0x17, GENMASK(13, 8), cl45_value);
 	if (ret < 0)
 		return ret;
-	ret = an8801_cl45_read(phydev, MMD_DEV_VSPEC1, 0x18, &temp_cl45);
+	temp_cl45 = phy_read_mmd(phydev, MMD_DEV_VSPEC1, 0x18);
 	dev_dbg(phydev_dev(phydev), "%s:%d cl45_value 0x%x!\n", __func__, __LINE__, temp_cl45);
 	mask = GENMASK(13, 8) | GENMASK(5, 0);
 	cl45_value = (temp_cl45 & GENMASK(13, 8)) + (9 << 8);
 	cl45_value = ((temp_cl45 & GENMASK(5, 0)) + 6) | cl45_value;
-	ret = an8801_modify_cl45_changed(phydev, MMD_DEV_VSPEC1, 0x18, mask, cl45_value);
+	ret = phy_modify_mmd(phydev, MMD_DEV_VSPEC1, 0x18, mask, cl45_value);
 	if (ret < 0)
 		return ret;
-	ret = an8801_cl45_read(phydev, MMD_DEV_VSPEC1, 0x19, &cl45_value);
+	cl45_value = phy_read_mmd(phydev, MMD_DEV_VSPEC1, 0x19);
 	dev_dbg(phydev_dev(phydev), "%s:%d cl45_value 0x%x!\n", __func__, __LINE__, cl45_value);
 	cl45_value = (cl45_value & GENMASK(13, 8)) + (6 << 8);
-	ret = an8801_modify_cl45_changed(phydev, MMD_DEV_VSPEC1, 0x19, GENMASK(13, 8), cl45_value);
+	ret = phy_modify_mmd(phydev, MMD_DEV_VSPEC1, 0x19, GENMASK(13, 8), cl45_value);
 	if (ret < 0)
 		return ret;
-	ret = an8801_cl45_read(phydev, MMD_DEV_VSPEC1, 0x20, &cl45_value);
+	cl45_value = phy_read_mmd(phydev, MMD_DEV_VSPEC1, 0x20);
 	dev_dbg(phydev_dev(phydev), "%s:%d cl45_value 0x%x!\n", __func__, __LINE__, cl45_value);
 	cl45_value = (cl45_value & GENMASK(5, 0)) + 6;
-	ret = an8801_modify_cl45_changed(phydev, MMD_DEV_VSPEC1, 0x20, GENMASK(5, 0), cl45_value);
+	ret = phy_modify_mmd(phydev, MMD_DEV_VSPEC1, 0x20, GENMASK(5, 0), cl45_value);
 	if (ret < 0)
 		return ret;
-	ret = an8801_cl45_read(phydev, MMD_DEV_VSPEC1, 0x21, &cl45_value);
+	cl45_value = phy_read_mmd(phydev, MMD_DEV_VSPEC1, 0x21);
 	dev_dbg(phydev_dev(phydev), "%s:%d cl45_value 0x%x!\n", __func__, __LINE__, cl45_value);
 	cl45_value = (cl45_value & GENMASK(13, 8)) + (6 << 8);
-	ret = an8801_modify_cl45_changed(phydev, MMD_DEV_VSPEC1, 0x21, GENMASK(13, 8), cl45_value);
+	ret = phy_modify_mmd(phydev, MMD_DEV_VSPEC1, 0x21, GENMASK(13, 8), cl45_value);
 	if (ret < 0)
 		return ret;
-	ret = an8801_cl45_read(phydev, MMD_DEV_VSPEC1, 0x22, &cl45_value);
+	cl45_value = phy_read_mmd(phydev, MMD_DEV_VSPEC1, 0x22);
 	dev_dbg(phydev_dev(phydev), "%s:%d cl45_value 0x%x!\n", __func__, __LINE__, cl45_value);
 	cl45_value = (cl45_value & GENMASK(5, 0)) + 6;
-	ret = an8801_modify_cl45_changed(phydev, MMD_DEV_VSPEC1, 0x22, GENMASK(5, 0), cl45_value);
+	ret = phy_modify_mmd(phydev, MMD_DEV_VSPEC1, 0x22, GENMASK(5, 0), cl45_value);
 	if (ret < 0)
 		return ret;
-	ret = an8801_cl45_write(phydev, MMD_DEV_VSPEC1, 0x23, 0x883);
-	ret |= an8801_cl45_write(phydev, MMD_DEV_VSPEC1, 0x24, 0x883);
-	ret |= an8801_cl45_write(phydev, MMD_DEV_VSPEC1, 0x25, 0x883);
-	ret |= an8801_cl45_write(phydev, MMD_DEV_VSPEC1, 0x26, 0x883);
-	ret |= an8801_cl45_write(phydev, MMD_DEV_VSPEC1, 0x0, 0x100);
-	ret |= an8801_cl45_write(phydev, MMD_DEV_VSPEC1, 0x1, 0x1bc);
-	ret |= an8801_cl45_write(phydev, MMD_DEV_VSPEC1, 0x2, 0x1d0);
-	ret |= an8801_cl45_write(phydev, MMD_DEV_VSPEC1, 0x3, 0x186);
-	ret |= an8801_cl45_write(phydev, MMD_DEV_VSPEC1, 0x4, 0x202);
-	ret |= an8801_cl45_write(phydev, MMD_DEV_VSPEC1, 0x5, 0x20e);
-	ret |= an8801_cl45_write(phydev, MMD_DEV_VSPEC1, 0x6, 0x300);
-	ret |= an8801_cl45_write(phydev, MMD_DEV_VSPEC1, 0x7, 0x3c0);
-	ret |= an8801_cl45_write(phydev, MMD_DEV_VSPEC1, 0x8, 0x3d0);
-	ret |= an8801_cl45_write(phydev, MMD_DEV_VSPEC1, 0x9, 0x317);
-	ret |= an8801_cl45_write(phydev, MMD_DEV_VSPEC1, 0xa, 0x206);
-	ret |= an8801_cl45_write(phydev, MMD_DEV_VSPEC1, 0xb, 0xe);
+	ret = phy_write_mmd(phydev, MMD_DEV_VSPEC1, 0x23, 0x883);
+	ret |= phy_write_mmd(phydev, MMD_DEV_VSPEC1, 0x24, 0x883);
+	ret |= phy_write_mmd(phydev, MMD_DEV_VSPEC1, 0x25, 0x883);
+	ret |= phy_write_mmd(phydev, MMD_DEV_VSPEC1, 0x26, 0x883);
+	ret |= phy_write_mmd(phydev, MMD_DEV_VSPEC1, 0x0, 0x100);
+	ret |= phy_write_mmd(phydev, MMD_DEV_VSPEC1, 0x1, 0x1bc);
+	ret |= phy_write_mmd(phydev, MMD_DEV_VSPEC1, 0x2, 0x1d0);
+	ret |= phy_write_mmd(phydev, MMD_DEV_VSPEC1, 0x3, 0x186);
+	ret |= phy_write_mmd(phydev, MMD_DEV_VSPEC1, 0x4, 0x202);
+	ret |= phy_write_mmd(phydev, MMD_DEV_VSPEC1, 0x5, 0x20e);
+	ret |= phy_write_mmd(phydev, MMD_DEV_VSPEC1, 0x6, 0x300);
+	ret |= phy_write_mmd(phydev, MMD_DEV_VSPEC1, 0x7, 0x3c0);
+	ret |= phy_write_mmd(phydev, MMD_DEV_VSPEC1, 0x8, 0x3d0);
+	ret |= phy_write_mmd(phydev, MMD_DEV_VSPEC1, 0x9, 0x317);
+	ret |= phy_write_mmd(phydev, MMD_DEV_VSPEC1, 0xa, 0x206);
+	ret |= phy_write_mmd(phydev, MMD_DEV_VSPEC1, 0xb, 0xe);
 	if (ret < 0)
 		return ret;
 
@@ -510,14 +515,14 @@ static int an8801sb_i2mpb_config(struct phy_device *phydev)
 }
 
 void update_r50_value(struct phy_device *phydev,
-			u16 *cl45_value, int pos1, int pos2)
+	u16 *cl45_value, int pos1, int pos2)
 {
 	*cl45_value &= ~(0x007f << 8);
 	*cl45_value |= ((r50ohm_table[pos1]) & 0x007f) << 8;
 	*cl45_value &= ~(0x007f);
 	*cl45_value |= (r50ohm_table[pos2]) & 0x007f;
 	dev_dbg(phydev_dev(phydev), "Read: r50ohm_tx_1=%d r50ohm_tx_2=%d\n",
-			r50ohm_table[pos1], r50ohm_table[pos2]);
+		r50ohm_table[pos1], r50ohm_table[pos2]);
 }
 
 int calculate_position(int pos, int shift, int table_size)
@@ -529,7 +534,7 @@ int calculate_position(int pos, int shift, int table_size)
 }
 
 int process_r50(struct phy_device *phydev, int reg,
-			u16 *cl45_value, u16 *r50ohm_tx_a, u16 *r50ohm_tx_b)
+	u16 *cl45_value, u16 *r50ohm_tx_a, u16 *r50ohm_tx_b)
 {
 	int pos1 = findClosestNumber(r50ohm_table, r50ohm_table_size, *r50ohm_tx_a);
 	int pos2 = findClosestNumber(r50ohm_table, r50ohm_table_size, *r50ohm_tx_b);
@@ -539,7 +544,7 @@ int process_r50(struct phy_device *phydev, int reg,
 		pos2 = calculate_position(pos2, R50_SHIFT, r50ohm_table_size);
 
 		update_r50_value(phydev, cl45_value, pos1, pos2);
-		return an8801_cl45_write(phydev, 0x1e, reg, *cl45_value);
+		return phy_write_mmd(phydev, 0x1e, reg, *cl45_value);
 	}
 	return 0;
 }
@@ -558,10 +563,10 @@ static int an8801r_of_init(struct phy_device *phydev)
 			return -1;
 		}
 		if (val < AIR_RGMII_DELAY_NOSTEP ||
-		    val > AIR_RGMII_DELAY_STEP_7) {
+			val > AIR_RGMII_DELAY_STEP_7) {
 			dev_err(phydev_dev(phydev),
-				   "airoha,rxclk-delay value %u out of range.",
-				   val);
+					"airoha,rxclk-delay value %u out of range.",
+					val);
 			return -1;
 		}
 		priv->rxdelay_force = TRUE;
@@ -574,14 +579,14 @@ static int an8801r_of_init(struct phy_device *phydev)
 		if (of_property_read_u32(of_node, "airoha,txclk-delay",
 					 &val) != 0) {
 			dev_err(phydev_dev(phydev),
-				   "airoha,txclk-delay value is invalid.");
+					"airoha,txclk-delay value is invalid.");
 			return -1;
 		}
 		if (val < AIR_RGMII_DELAY_NOSTEP ||
-		    val > AIR_RGMII_DELAY_STEP_7) {
+			val > AIR_RGMII_DELAY_STEP_7) {
 			dev_err(phydev_dev(phydev),
-				   "airoha,txclk-delay value %u out of range.",
-				   val);
+					"airoha,txclk-delay value %u out of range.",
+					val);
 			return -1;
 		}
 		priv->txdelay_force = TRUE;
@@ -603,10 +608,10 @@ static int an8801sb_of_init(struct phy_device *phydev)
 			return -1;
 		}
 		if (val < AIR_POL_TX_NOR_RX_REV ||
-		    val > AIR_POL_TX_REV_RX_NOR) {
+			val > AIR_POL_TX_REV_RX_NOR) {
 			dev_err(phydev_dev(phydev),
-				   "airoha,polarity value %u out of range.",
-				   val);
+					"airoha,polarity value %u out of range.",
+					val);
 			return -1;
 		}
 		priv->pol = val;
@@ -615,15 +620,15 @@ static int an8801sb_of_init(struct phy_device *phydev)
 
 	if (of_find_property(of_node, "airoha,surge", NULL)) {
 		if (of_property_read_u32(of_node, "airoha,surge",
-					&val) != 0) {
+					 &val) != 0) {
 			dev_err(phydev_dev(phydev), "airoha,surge value is invalid.");
 			return -1;
 		}
 		if (val < AIR_SURGE_0R ||
 			val > AIR_SURGE_5R) {
 			dev_err(phydev_dev(phydev),
-				"airoha,surge value %u out of range.",
-				val);
+					"airoha,surge value %u out of range.",
+					val);
 			return -1;
 		}
 		priv->surge = val;
@@ -693,23 +698,19 @@ int an8801sb_surge_protect_cfg(struct phy_device *phydev)
 	u16 cl45_value = 0;
 
 	if (priv->surge) {
-		ret = an8801_cl45_read(phydev, 0x1e, 0x174, &cl45_value);
-		if (ret < 0)
-			return ret;
+		cl45_value = phy_read_mmd(phydev, 0x1e, 0x174);
 		r50ohm_tx_a = (cl45_value >> 8) & 0x007f;
 		r50ohm_tx_b = cl45_value & 0x007f;
 		dev_dbg(phydev_dev(phydev), "Read: (0x174) value=0x%04x r50ohm_tx_a=%d r50ohm_tx_b=%d\n",
-		cl45_value, r50ohm_tx_a, r50ohm_tx_b);
+			cl45_value, r50ohm_tx_a, r50ohm_tx_b);
 		ret = process_r50(phydev, 0x174, &cl45_value, &r50ohm_tx_a, &r50ohm_tx_b);
 		if (ret < 0)
 			return ret;
-		ret = an8801_cl45_read(phydev, 0x1e, 0x175, &cl45_value);
-		if (ret < 0)
-			return ret;
+		cl45_value = phy_read_mmd(phydev, 0x1e, 0x175);
 		r50ohm_tx_c = (cl45_value >> 8) & 0x007f;
 		r50ohm_tx_d = cl45_value & 0x007f;
 		dev_dbg(phydev_dev(phydev), "Read: (0x175) value=0x%04x r50ohm_tx_c=%d r50ohm_tx_d=%d\n",
-		cl45_value, r50ohm_tx_c, r50ohm_tx_d);
+			cl45_value, r50ohm_tx_c, r50ohm_tx_d);
 		ret = process_r50(phydev, 0x175, &cl45_value, &r50ohm_tx_c, &r50ohm_tx_d);
 		if (ret < 0)
 			return ret;
@@ -764,10 +765,10 @@ static int an8801sb_config_init(struct phy_device *phydev)
 	dev_info(phydev_dev(phydev),
 		"Tx, Rx Polarity : %08x\n", pbus_value);
 
-	ret = an8801_cl45_write(phydev, MMD_DEV_VSPEC2, 0x600, 0x1e);
-	ret |= an8801_cl45_write(phydev, MMD_DEV_VSPEC2, 0x601, 0x02);
+	ret = phy_write_mmd(phydev, MMD_DEV_VSPEC2, 0x600, 0x1e);
+	ret |= phy_write_mmd(phydev, MMD_DEV_VSPEC2, 0x601, 0x02);
 
-	ret |= an8801_cl45_write(phydev, 7, 60, 0x0);
+	ret |= phy_write_mmd(phydev, 7, 60, 0x0);
 	if (ret != 0) {
 		dev_err(phydev_dev(phydev),
 			"AN8801SB initialize fail, ret %d !\n", ret);
@@ -940,7 +941,7 @@ static ssize_t an8801_polarity_write(struct file *file, const char __user *ptr,
 }
 
 static ssize_t an8801_mdio_write(struct file *file, const char __user *ptr,
-				size_t len, loff_t *off)
+					size_t len, loff_t *off)
 {
 	struct phy_device *phydev = file->private_data;
 	char buf[64], param1[32], param2[32];
@@ -955,7 +956,7 @@ static ssize_t an8801_mdio_write(struct file *file, const char __user *ptr,
 	if (count > sizeof(buf) - 1)
 		return -EINVAL;
 	if (copy_from_user(buf, ptr, len))
-	return -EFAULT;
+		return -EFAULT;
 
 	ret = sscanf(buf, "%s %s", param1, param2);
 	if (ret < 0)
@@ -991,16 +992,16 @@ static ssize_t an8801_mdio_write(struct file *file, const char __user *ptr,
 			pr_notice("\nphy=0x%x, devad=0x%x, reg=0x%x, val=0x%x\n",
 				phydev_phy_addr(phydev), devad, reg, val);
 
-			ret = an8801_cl45_write(phydev, devad, reg, val);
+			ret = phy_write_mmd(phydev, devad, reg, val);
 			if (ret < 0)
 				return ret;
-			an8801_cl45_read(phydev, devad, reg, &reg_val);
+			reg_val = phy_read_mmd(phydev, devad, reg);
 			pr_notice("\nphy=0x%x, devad=0x%x, reg=0x%x, val=0x%x confirm..\n",
 				phydev_phy_addr(phydev), devad, reg, reg_val);
 		} else if (!strncmp("r", param2, strlen("r"))) {
 			if (sscanf(buf, "cl45 r %x %x", &devad, &reg) == -1)
 				return -EFAULT;
-			an8801_cl45_read(phydev, devad, reg, &reg_val);
+			reg_val = phy_read_mmd(phydev, devad, reg);
 			pr_notice("\nphy=0x%x, devad=0x%x, reg=0x%x, val=0x%x\n",
 				phydev_phy_addr(phydev), devad, reg, reg_val);
 		} else {
@@ -1020,7 +1021,6 @@ static int an8801_counter_show(struct seq_file *seq, void *v)
 	struct phy_device *phydev = seq->private;
 	int ret = 0;
 	u32 pkt_cnt = 0;
-	struct mii_bus *mbus = phydev_mdiobus(phydev);
 
 	seq_puts(seq, "==========AIR PHY COUNTER==========\n");
 	seq_puts(seq, "|\t<<SERDES COUNTER>>\n");
@@ -1143,8 +1143,9 @@ static ssize_t an8801_debugfs_pbus(struct file *file,
 	if (buf[0] == 'w') {
 		if (sscanf(buf, "w %x %x", &reg, &val) == -1)
 			return -EFAULT;
+
 		pr_notice("\nphy=0x%x, reg=0x%x, val=0x%x\n",
-			phydev_phy_addr(phydev), reg, val);
+				phydev_phy_addr(phydev), reg, val);
 
 		ret = air_buckpbus_reg_write(phydev, reg, val);
 		if (ret < 0)
@@ -1188,10 +1189,9 @@ int an8801_info_show(struct seq_file *seq, void *v)
 	for (reg = MII_BMCR; reg <= MII_STAT1000; reg++) {
 		if ((reg <= MII_LPA) || (reg >= MII_CTRL1000))
 			seq_printf(seq, "| RG_MII 0x%02x     : 0x%08x\n",
-			reg, phy_read(phydev, reg));
+				reg, phy_read(phydev, reg));
 	}
 	seq_puts(seq, "\n");
-
 	return 0;
 }
 
@@ -1231,10 +1231,10 @@ static const struct file_operations an8801_polarity_fops = {
 };
 
 static const struct file_operations an8801_mdio_fops = {
-   .owner = THIS_MODULE,
-   .open = simple_open,
-   .write = an8801_mdio_write,
-   .llseek = noop_llseek,
+	.owner = THIS_MODULE,
+	.open = simple_open,
+	.write = an8801_mdio_write,
+	.llseek = noop_llseek,
 };
 
 int an8801_debugfs_init(struct phy_device *phydev)
@@ -1354,13 +1354,22 @@ static int an8801sb_read_status(struct phy_device *phydev)
 	if (phydev->link == LINK_DOWN) {
 		prespeed = 0;
 		phydev->speed = 0;
-		ret |= an8801_cl45_write(
+		ret |= phy_write_mmd(
 			phydev, MMD_DEV_VSPEC2, PHY_PRE_SPEED_REG, prespeed);
+
+		mdelay(10);        /* delay 10 ms */
+		reg_value = air_buckpbus_reg_read(phydev, 0x10220010);
+		reg_value &= 0x7fff;
+		air_buckpbus_reg_write(phydev, 0x10220010, reg_value);
+
+		reg_value = air_buckpbus_reg_read(phydev, 0x10220000);
+		reg_value |= AN8801SB_SGMII_AN0_ANRESTART;
+		air_buckpbus_reg_write(phydev, 0x10220000, reg_value);
 	}
 
 	if (prespeed != phydev->speed && phydev->link == LINK_UP) {
 		prespeed = phydev->speed;
-		ret |= an8801_cl45_write(
+		ret |= phy_write_mmd(
 			phydev, MMD_DEV_VSPEC2, PHY_PRE_SPEED_REG, prespeed);
 		dev_info(phydev_dev(phydev), "AN8801SB SPEED %d\n", prespeed);
 		while (an_retry > 0) {
@@ -1374,28 +1383,19 @@ static int an8801sb_read_status(struct phy_device *phydev)
 		mdelay(10);        /* delay 10 ms */
 
 
-		if (phydev->autoneg == AUTONEG_DISABLE) {
-			dev_info(phydev_dev(phydev),
-				"AN8801SB force speed = %d\n", prespeed);
-			if (prespeed == SPEED_1000) {
-				air_buckpbus_reg_write(
-					phydev, 0x10220010, 0xd801);
-			} else if (prespeed == SPEED_100) {
-				air_buckpbus_reg_write(
-					phydev, 0x10220010, 0xd401);
-			} else {
-				air_buckpbus_reg_write(
-					phydev, 0x10220010, 0xd001);
-			}
-
-			reg_value = air_buckpbus_reg_read(
-				phydev, 0x10220000);
-			reg_value |= AN8801SB_SGMII_AN0_ANRESTART;
+		if (prespeed == SPEED_1000) {
 			air_buckpbus_reg_write(
-				phydev, 0x10220000, reg_value);
+				phydev, 0x10220010, 0xd801);
+		} else if (prespeed == SPEED_100) {
+			air_buckpbus_reg_write(
+				phydev, 0x10220010, 0xd401);
+		} else {
+			air_buckpbus_reg_write(
+				phydev, 0x10220010, 0xd001);
 		}
+
 		reg_value = air_buckpbus_reg_read(phydev, 0x10220000);
-		reg_value |= AN8801SB_SGMII_AN0_RESET;
+		reg_value |= (AN8801SB_SGMII_AN0_RESET | AN8801SB_SGMII_AN0_ANRESTART);
 		air_buckpbus_reg_write(phydev, 0x10220000, reg_value);
 	}
 	return ret;
@@ -1451,9 +1451,12 @@ static struct phy_driver airoha_driver[] = {
 		.probe          = an8801_phy_probe,
 		.remove         = an8801_phy_remove,
 		.read_status    = an8801_read_status,
-#if (KERNEL_VERSION(4, 5, 0) < LINUX_VERSION_CODE)
-		.read_mmd       = __an8801_cl45_read,
-		.write_mmd      = __an8801_cl45_write,
+		.config_intr	= an8801_config_intr,
+#if (KERNEL_VERSION(5, 11, 0) < LINUX_VERSION_CODE)
+		.handle_interrupt = an8801_handle_interrupt,
+#else
+		.did_interrupt	= an8801_did_interrupt,
+		.ack_interrupt	= an8801_ack_interrupt,
 #endif
 	}
 };

feeds/mediatek-sdk/mediatek/files-5.4/drivers/net/phy/an8801.h

@@ -12,10 +12,10 @@
 
 /* NAMING DECLARATIONS
  */
-#define AN8801_DRIVER_VERSION  "1.1.4"
+#define AN8801_DRIVER_VERSION  "1.1.6"
 
 #define DEBUGFS_COUNTER         "counter"
-#define DEBUGFS_INFO     "driver_info"
+#define DEBUGFS_INFO            "driver_info"
 #define DEBUGFS_PBUS_OP         "pbus_op"
 #define DEBUGFS_POLARITY        "polarity"
 #define DEBUGFS_MDIO            "mdio"
@@ -88,7 +88,7 @@
 #define LED_BLK_EVT_1000M_RX        BIT(1)
 #define LED_BLK_EVT_1000M_TX        BIT(0)
 
-#define UNIT_LED_BLINK_DURATION     1024
+#define UNIT_LED_BLINK_DURATION     780
 
 /* Serdes auto negotation restart */
 #define AN8801SB_SGMII_AN0_ANRESTART    (0x0200)
@@ -135,6 +135,9 @@ For reference only
 #define LED_BLINK_DURATION(f)       (UNIT_LED_BLINK_DURATION << (f))
 #define LED_GPIO_SEL(led, gpio)     ((led) << ((gpio) * 3))
 
+/* Interrupt GPIO number, should not conflict with LED */
+#define AIR_INTERRUPT_GPIO	3
+
 /* DATA TYPE DECLARATIONS
  */
 enum AIR_LED_GPIO_PIN_T {

feeds/mediatek-sdk/mediatek/files-5.4/drivers/net/phy/en8801sc.c

@@ -587,7 +587,7 @@ static int en8801s_phase1_init(struct phy_device *phydev)
 
 	phydev->dev_flags = PHY_STATE_INIT;
 
-	dev_info(dev, "Phase1 initialize OK ! (%s)\n", EN8801S_DRIVER_VERSION);
+	dev_info(dev, "Phase1 initialize OK ! (%s) 10Te TP_IDL fixed.\n", EN8801S_DRIVER_VERSION);
 	if (priv->pro_version == 4) {
 		ret = en8801s_phase2_init(phydev);
 		if (ret != 0) {
@@ -811,14 +811,7 @@ static int en8801s_phase2_init(struct phy_device *phydev)
 		retry--;
 	}
 	pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C38); /* RAW#2 */
-	ret = airoha_cl45_read(mbus, phy_addr, 0x1E, 0x12, &cl45_value);
-	if (ret < 0)
-		return ret;
-	GPHY_RG_1E_012.DATA = cl45_value;
-	GPHY_RG_1E_012.DataBitField.da_tx_i2mpb_a_tbt =
-				(u16)(pbus_data & 0x03f);
-	ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x12,
-				GPHY_RG_1E_012.DATA);
+	ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x12, 0xA018);
 	if (ret < 0)
 		return ret;
 	ret = airoha_cl45_read(mbus, phy_addr, 0x1E, 0x17, &cl45_value);
@@ -893,6 +886,17 @@ static int en8801s_phase2_init(struct phy_device *phydev)
 		}
 	}
 
+	//Fix 10Te TP_IDL
+	ret = airoha_cl45_read(mbus, phy_addr, 0x1E,
+				0x1A3, &cl45_value);
+	if (ret < 0)
+		return ret;
+	cl45_value &= ~0xf0;
+	ret = airoha_cl45_write(mbus, phy_addr, 0x1E,
+				0x1A3, cl45_value);
+	if (ret < 0)
+		return ret;
+
 	priv->first_init = false;
 	dev_info(phydev_dev(phydev), "Phase2 initialize OK !\n");
 	return 0;

feeds/mediatek-sdk/mediatek/mt7981/base-files/etc/board.d/02_network

@@ -31,7 +31,10 @@ mediatek_setup_interfaces()
 		;;
 	sonicfi,rap630w-211g)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" eth1
-		;;		
+		;;
+    emplus,wap588m)
+        ucidef_set_interfaces_lan_wan "eth0" "eth1"
+        ;;
 	*)	
 		ucidef_set_interfaces_lan_wan "eth1" "eth0"
 		;;

feeds/mediatek-sdk/mediatek/mt7981/config-5.4

@@ -2,7 +2,6 @@ CONFIG_64BIT=y
 CONFIG_AHCI_MTK=y
 CONFIG_AIROHA_EN8801SC_PHY=y
 # CONFIG_AIROHA_EN8811H_PHY is not set
-# CONFIG_AIROHA_AN8801_PHY is not set
 CONFIG_AN8855_GSW=y
 CONFIG_ARCH_CLOCKSOURCE_DATA=y
 CONFIG_ARCH_DMA_ADDR_T_64BIT=y

feeds/mediatek-sdk/mediatek/patches-5.4/999-2738-an8801sb-gphy-support.patch

@@ -1,15 +1,3 @@
-From 535fdc6dfce7def996a5188819ffc96231c36f98 Mon Sep 17 00:00:00 2001
-From: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
-Date: Tue, 2 Jan 2024 18:13:43 +0800
-Subject: [PATCH] [networking][999-2738-an8801sb-gphy-support.patch]
-
----
- drivers/net/phy/Kconfig  |   5 +
- drivers/net/phy/Makefile |   1 +
- 2 files changed, 6 insertions(+)
-
-diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
-index ccd3f3f..5dbfb17 100644
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
 @@ -345,6 +345,11 @@ config SFP
@@ -24,8 +12,6 @@ index ccd3f3f..5dbfb17 100644
  config AIROHA_EN8801SC_PHY
  	tristate "Drivers for Airoha EN8801S Gigabit PHYs for MediaTek SoC."
  	---help---
-diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
-index 1e8d67b..d39e54b 100644
 --- a/drivers/net/phy/Makefile
 +++ b/drivers/net/phy/Makefile
 @@ -74,6 +74,7 @@ endif
@@ -36,6 +22,64 @@ index 1e8d67b..d39e54b 100644
  obj-$(CONFIG_AIROHA_EN8801SC_PHY)	+= en8801sc.o
  air_en8811h-y := air_en8811h_main.o air_en8811h_api.o
  obj-$(CONFIG_AIROHA_EN8811H_PHY)	+= air_en8811h.o
--- 
-2.18.0
-
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -870,12 +870,17 @@
+ 	of_node_put(phy_node);
+ 
+ 	if (!phy_dev)
+-		return -ENODEV;
+-
++	{
++		phylink_info(pl, "[phylink] reload phy-handle2. %s %d\n",__func__, __LINE__);
++		phy_node = of_parse_phandle(dn, "phy-handle2", 0);
++		phy_dev = of_phy_attach(pl->netdev, phy_node, flags, pl->link_interface);
++		if (!phy_dev)
++			return -ENODEV;
++	}
++	
+ 	ret = phylink_bringup_phy(pl, phy_dev, pl->link_config.interface);
+ 	if (ret)
+ 		phy_detach(phy_dev);
+-
+ 	return ret;
+ }
+ EXPORT_SYMBOL_GPL(phylink_of_phy_connect);
+--- a/drivers/of/of_mdio.c
++++ b/drivers/of/of_mdio.c
+@@ -226,7 +226,9 @@
+ 		return rc;
+ 
+ 	/* Loop over the child nodes and register a phy_device for each phy */
++	int an8801=0;
+ 	for_each_available_child_of_node(np, child) {
++		if(an8801==1)break;
+ 		addr = of_mdio_parse_addr(&mdio->dev, child);
+ 		if (addr < 0) {
+ 			scanphys = true;
+@@ -234,7 +236,25 @@
+ 		}
+ 
+ 		if (of_mdiobus_child_is_phy(child))
++		{
++			if(addr==30)
++			{
++				int phy_id ;
++
++				phy_id = mdiobus_read(mdio, addr, MII_PHYSID1) << 16 ;
++				phy_id = phy_id + mdiobus_read(mdio, addr, MII_PHYSID2);
++				dev_info(&mdio->dev, "[of_mdio] %s %d  addr:%d phy_id:0x%x  \n",__func__, __LINE__, addr, phy_id);
++
++				if (phy_id==0 || phy_id==0x1a750000)
++				{
++					dev_info(&mdio->dev, "[of_mdio] %s %d  continue  \n",__func__, __LINE__);
++					continue;
++				}
++				else
++					an8801=1;
++			}
+ 			rc = of_mdiobus_register_phy(mdio, child, addr);
++		}
+ 		else
+ 			rc = of_mdiobus_register_device(mdio, child, addr);
+ 

feeds/qca-wifi-7/ath12k-wifi/Makefile

@@ -78,6 +78,10 @@ $(call Package/ath12k-wifi-default)
     TITLE:=board-2.bin for AP72TIP-v4
 endef
 
+define Package/ath12k-wifi-zyxel-nwa130be
+$(call Package/ath12k-wifi-default)
+    TITLE:=board-2.bin for NWA130BE
+endef
 
 define Package/ath12k-wifi-cig-wf189/install
 	$(INSTALL_DIR) $(1)/lib/firmware/ath12k/QCN92XX/hw1.0/
@@ -149,6 +153,13 @@ define Package/ath12k-wifi-sercomm-ap72tip-v4/install
 	$(INSTALL_DATA) ./board-2.bin.ap72tip-v4.IPQ5332 $(1)/lib/firmware/ath12k/IPQ5332/hw1.0/board-2.bin
 endef
 
+define Package/ath12k-wifi-zyxel-nwa130be/install
+	$(INSTALL_DIR) $(1)/lib/firmware/ath12k/QCN92XX/hw1.0/
+	$(INSTALL_DIR) $(1)/lib/firmware/ath12k/IPQ5332/hw1.0/
+	$(INSTALL_DATA) ./board-2.bin.nwa130be.QCN92XX $(1)/lib/firmware/ath12k/QCN92XX/hw1.0/board-2.bin
+	$(INSTALL_DATA) ./board-2.bin.nwa130be.IPQ5332 $(1)/lib/firmware/ath12k/IPQ5332/hw1.0/board-2.bin
+endef
+
 $(eval $(call BuildPackage,ath12k-wifi-cig-wf189))
 $(eval $(call BuildPackage,ath12k-wifi-edgecore-eap105))
 $(eval $(call BuildPackage,ath12k-wifi-sonicfi-rap7110c-341x))
@@ -158,3 +169,4 @@ $(eval $(call BuildPackage,ath12k-wifi-cig-wf189w))
 $(eval $(call BuildPackage,ath12k-wifi-cig-wf189h))
 $(eval $(call BuildPackage,ath12k-wifi-sercomm-ap72tip))
 $(eval $(call BuildPackage,ath12k-wifi-sercomm-ap72tip-v4))
+$(eval $(call BuildPackage,ath12k-wifi-zyxel-nwa130be))

feeds/qca-wifi-7/ipq53xx/base-files/etc/board.d/01_leds

@@ -18,6 +18,15 @@ sonicfi,rap750e-h|\
 sonicfi,rap750w-311a)
 	ucidef_set_led_default "power" "POWER" "pwm:blue" "on"
 	;;
+zyxel,nwa130be)
+	#eth0: APPE: phyaddr 4  green:2.5G  orange:others
+	ssdk_sh debug phy set 4 0x40078074 0x670
+	ssdk_sh debug phy set 4 0x40078078 0x8600
+
+	#eth1:  MHT: phyaddr 3  green:2.5G orange:others
+	ssdk_sh debug phy set 3 0x40078074 0x670
+	ssdk_sh debug phy set 3 0x40078078 0x8600
+	;;
 esac
 
 board_config_flush

feeds/qca-wifi-7/ipq53xx/base-files/etc/board.d/02_network

@@ -33,6 +33,9 @@ ipq53xx_setup_interfaces()
 	sercomm,ap72tip-v4)
 		ucidef_set_interface_wan "eth0"
 		;;	
+	zyxel,nwa130be)
+		ucidef_set_interfaces_lan_wan "eth1" "eth0"
+		;;
 	esac
 }
 
@@ -87,6 +90,19 @@ qcom_setup_macs()
                 ucidef_set_wireless_macaddr_base 5g $(macaddr_add "$wan_mac" 2)
                 ucidef_set_wireless_macaddr_base 6g $(macaddr_add "$wan_mac" 3)
                 ;;
+	zyxel,nwa130be)
+		wan_mac=$(cat /proc/cmdline)
+		wan_mac="${wan_mac##*hwaddr=}"
+		wan_mac="${wan_mac%% *}"
+		wan_mac="$(echo ${wan_mac} | sed 's/\(..\)/\1:/g;s/:$//')"
+		lan_mac=$(macaddr_add "$wan_mac" 1)
+		ucidef_set_network_device_mac eth0 $wan_mac
+		ucidef_set_network_device_mac eth1 $lan_mac
+		ucidef_set_label_macaddr $wan_mac
+		ucidef_set_wireless_macaddr_base 2g $(macaddr_add "$wan_mac" 2)
+		ucidef_set_wireless_macaddr_base 5g $(macaddr_add "$wan_mac" 3)
+		ucidef_set_wireless_macaddr_base 6g $(macaddr_add "$wan_mac" 4)
+		;;
         *)
                 wan_mac=$(cat /sys/class/net/eth1/address)
                 lan_mac=$(macaddr_add "$wan_mac" 1)

feeds/qca-wifi-7/ipq53xx/base-files/etc/hotplug.d/firmware/10-ath12k-caldata

@@ -32,7 +32,8 @@ ath12k/IPQ5332/hw1.0/caldata.bin)
 	cig,wf189|\
 	edgecore,eap105|\
 	sercomm,ap72tip-v4|\
-	sercomm,ap72tip)
+	sercomm,ap72tip|\
+	zyxel,nwa130be)
 		caldata_extract "0:ART" 0x1000 0x20000 
 		;;
 	sonicfi,rap7110c-341x)
@@ -49,7 +50,8 @@ ath12k/QCN92XX/hw1.0/cal-pci-0001:01:00.0.bin)
 	cig,wf189|\
 	edgecore,eap105|\
 	sercomm,ap72tip-v4|\
-	sercomm,ap72tip)
+	sercomm,ap72tip|\
+	zyxel,nwa130be)
 		caldata_extract "0:ART" 0x58800 0x2d000
 		;;
 	sonicfi,rap7110c-341x)

feeds/qca-wifi-7/ipq53xx/base-files/etc/hotplug.d/iface/85-greqos

@@ -0,0 +1,20 @@
+# /etc/hotplug.d/iface/85-greqos
+[ "$ACTION" == "ifup" ] || exit 0
+
+. /lib/functions.sh
+
+case "$(board_name)" in
+cig,wf189|\
+cig,wf189w|\
+cig,wf189h|\
+cig,wf672)
+    case "$INTERFACE" in
+      gre*)
+        dev=$(ubus call network.interface.$INTERFACE status | jsonfilter -e '@.l3_device')
+        [ -n "$dev" ] && {
+          tc qdisc del dev $dev root 2>/dev/null
+          tc qdisc add dev $dev root noqueue
+        }
+        ;;
+    esac
+esac

feeds/qca-wifi-7/ipq53xx/base-files/lib/upgrade/platform.sh

@@ -125,5 +125,8 @@ platform_do_upgrade() {
 	sercomm,ap72tip)
 		nand_upgrade_tar "$1"
 		;;
+	zyxel,nwa130be)
+		nand_upgrade_tar "$1"
+		;;
 	esac
 }

feeds/qca-wifi-7/ipq53xx/dts/ipq5332-zyxel-nwa130be.dts

@@ -0,0 +1,592 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * IPQ5332 RDP468 board device tree source
+ *
+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include "ipq5332.dtsi"
+#include "ipq5332-default-memory.dtsi"
+
+/ {
+	model = "Zyxel NWA130BE";
+	compatible = "zyxel,nwa130be", "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332-rdp468", "qcom,ipq5332";
+
+	aliases {
+		serial0 = &blsp1_uart0;
+		serial1 = &blsp1_uart1;
+		ethernet0 = "/soc/dp1";
+		ethernet1 = "/soc/dp2";
+	};
+
+	chosen {
+		stdout-path = "serial0";
+	};
+
+	soc@0 {
+		mdio:mdio@90000 {
+			pinctrl-0 = <&mdio1_pins &mdio0_pins>;
+			pinctrl-names = "default";
+			/*gpio51 for manhattan reset*/
+			phy-reset-gpio = <&tlmm 51 GPIO_ACTIVE_LOW>;
+			phyaddr_fixup = <0xC90F018>;
+			uniphyaddr_fixup = <0xC90F014>;
+			mdio_clk_fixup; /* MDIO clock sequence fix up flag */
+			status = "okay";
+
+			phy0: ethernet-phy@0 {
+				reg = <1>;
+				fixup;
+			};
+			phy1: ethernet-phy@1 {
+				reg = <2>;
+				fixup;
+			};
+			phy2: ethernet-phy@2 {
+				reg = <3>;
+				fixup;
+			};
+			phy3: ethernet-phy@3 {
+				reg = <4>;
+				fixup;
+			};
+
+			switch0@10 {
+				compatible = "qca,qca8386";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x10>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						label = "cpu";
+						ethernet = <&gmac2>;
+						dsa-tag-protocol = "qca_4b";
+					};
+
+					port@1 {
+						reg = <1>;
+						label = "lan1";
+						phy-handle = <&phy0>;
+						phy-mode = "usxgmii";
+					};
+
+					port@2 {
+						reg = <2>;
+						label = "lan2";
+						phy-handle = <&phy1>;
+						phy-mode = "usxgmii";
+					};
+
+					port@3 {
+						reg = <3>;
+						label = "lan3";
+						phy-handle = <&phy2>;
+						phy-mode = "usxgmii";
+					};
+				};
+			};
+		};
+
+		ess-instance {
+			num_devices = <0x2>;
+
+			ess-switch@3a000000 {
+				switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
+				switch_lan_bmp = <0x2>; /* lan port bitmap */
+				switch_wan_bmp = <0x4>; /* wan port bitmap */
+				switch_mac_mode = <0xc>; /* mac mode for uniphy instance0*/
+				switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/
+				switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
+
+				qcom,port_phyinfo {
+					port@0 {
+						port_id = <1>;
+						forced-speed = <2500>;
+						forced-duplex = <1>;
+					};
+					port@1 {
+						port_id = <2>;
+						phy_address = <4>;
+					};
+				};
+
+				led_source@5 {
+					source = <5>;
+					mode = "normal";
+					speed = "all";
+					blink_en = "enable";
+					active = "high";
+				};
+			};
+
+			ess-switch1@1 {
+				compatible = "qcom,ess-switch-qca8386";
+				device_id = <1>;
+				switch_access_mode = "mdio";
+				mdio-bus = <&mdio>;
+				switch_mac_mode = <0xc>; /* mac mode for uniphy instance0 */
+				switch_mac_mode1 = <0xff>; /* mac mode1 for uniphy instance1 */
+				switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
+				switch_lan_bmp = <0xe>; /* lan port bitmap */
+				switch_wan_bmp = <0x0>;  /* wan port bitmap */
+				link-polling-required = <0>;
+				fdb_sync = "interrupt";
+				link-intr-gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>;
+
+				qcom,port_phyinfo {
+					port@0 {
+						port_id = <0>;
+						forced-speed = <2500>;
+						forced-duplex = <1>;
+					};
+					port@1 {
+						port_id = <1>;
+						phy_address = <1>;
+					};
+					port@2 {
+						port_id = <2>;
+						phy_address = <2>;
+					};
+					port@3 {
+						port_id = <3>;
+						phy_address = <3>;
+					};
+				};
+
+				led_source@2 {
+					source = <2>;
+					mode = "normal";
+					speed = "all";
+					blink_en = "enable";
+					active = "high";
+				};
+				led_source@5 {
+					source = <5>;
+					mode = "normal";
+					speed = "all";
+					blink_en = "enable";
+					active = "high";
+				};
+				led_source@8 {
+					source = <8>;
+					mode = "normal";
+					speed = "all";
+					blink_en = "enable";
+					active = "high";
+				};
+			};
+		};
+
+		dp1 {
+			device_type = "network";
+			compatible = "qcom,nss-dp";
+			qcom,id = <2>;
+			reg = <0x3a504000 0x4000>;
+			qcom,mactype = <1>;
+			local-mac-address = [000000000000];
+			mdio-bus = <&mdio>;
+			qcom,phy-mdio-addr = <4>;
+			qcom,link-poll = <1>;
+			phy-mode = "sgmii";
+		};
+
+		gmac2:dp2 {
+			device_type = "network";
+			compatible = "qcom,nss-dp";
+			qcom,id = <1>;
+			reg = <0x3a500000 0x4000>;
+			qcom,mactype = <1>;
+			local-mac-address = [000000000000];
+			phy-mode = "sgmii";
+			qcom,mht-dev = <1>;
+			qcom,is_switch_connected = <1>;
+			qcom,ppe-offload-disabled = <1>;
+		};
+
+		/* EDMA host driver configuration for the board */
+		edma@3ab00000 {
+			qcom,txdesc-ring-start = <4>;		/* Tx desc ring start ID */
+			qcom,txdesc-rings = <12>;		/* Total number of Tx desc rings to be provisioned */
+			qcom,mht-txdesc-rings = <8>;            /* Extra Tx desc rings to be provisioned for MHT SW ports */
+			qcom,txcmpl-ring-start = <4>;		/* Tx complete ring start ID */
+			qcom,txcmpl-rings = <12>;		/* Total number of Tx complete rings to be provisioned */
+			qcom,mht-txcmpl-rings = <8>;            /* Extra Tx complete rings to be provisioned for mht sw ports. */
+			qcom,rxfill-ring-start = <4>;		/* Rx fill ring start ID */
+			qcom,rxfill-rings = <4>;		/* Total number of Rx fill rings to be provisioned */
+			qcom,rxdesc-ring-start = <12>;		/* Rx desc ring start ID */
+			qcom,rxdesc-rings = <4>;		/* Total number of Rx desc rings to be provisioned */
+			qcom,rx-page-mode = <0>;		/* Rx fill ring page mode */
+			qcom,tx-map-priority-level = <1>;	/* Tx priority level per port */
+			qcom,rx-map-priority-level = <1>;	/* Rx priority level per core */
+			qcom,ppeds-num = <2>;			/* Number of PPEDS nodes */
+			/* PPE-DS node format: <Rx-fill Tx-cmpl Rx Tx Queue-base Queue-count> */
+			qcom,ppeds-map = <1 1 1 1 32 8>,	/* PPEDS Node#0 ring and queue map */
+					<2 2 2 2 40 8>;		/* PPEDS Node#1 ring and queue map */
+			qcom,txdesc-map = <8 9 10 11>,		/* Port0 per-core Tx ring map */
+					<12 13 14 15>,        /* MHT-Port1 per-core Tx ring map */
+					<4 5 6 7>,            /* MHT-Port2 per-core Tx ring map/packets from  vp*/
+					<16 17 18 19>,        /* MHT-Port3 per-core Tx ring map */
+					<20 21 22 23>;        /* MHT-Port4 per-core Tx ring map */
+			qcom,txdesc-fc-grp-map = <1 2 3 4 5>;   /* Per GMAC flow control group map */
+			qcom,rxfill-map = <4 5 6 7>;		/* Per-core Rx fill ring map */
+			qcom,rxdesc-map = <12 13 14 15>;	/* Per-core Rx desc ring map */
+			qcom,rx-queue-start = <0>;		/* Rx queue start */
+			qcom,rx-ring-queue-map = <0 8 16 24>,	/* Priority 0 queues per-core Rx ring map */
+						<1 9 17 25>,	/* Priority 1 queues per-core Rx ring map */
+						<2 10 18 26>,	/* Priority 2 queues per-core Rx ring map */
+						<3 11 19 27>,	/* Priority 3 queues per-core Rx ring map */
+						<4 12 20 28>,	/* Priority 4 queues per-core Rx ring map */
+						<5 13 21 29>,	/* Priority 5 queues per-core Rx ring map */
+						<6 14 22 30>,	/* Priority 6 queues per-core Rx ring map */
+						<7 15 23 31>;	/* Priority 7 queues per-core Rx ring map */
+			interrupts = <0 163 4>,			/* Tx complete ring id #4 IRQ info */
+				   <0 164 4>,			/* Tx complete ring id #5 IRQ info */
+				   <0 165 4>,			/* Tx complete ring id #6 IRQ info */
+				   <0 166 4>,			/* Tx complete ring id #7 IRQ info */
+				   <0 167 4>,			/* Tx complete ring id #8 IRQ info */
+				   <0 168 4>,			/* Tx complete ring id #9 IRQ info */
+				   <0 169 4>,			/* Tx complete ring id #10 IRQ info */
+				   <0 170 4>,			/* Tx complete ring id #11 IRQ info */
+				   <0 171 4>,			/* Tx complete ring id #12 IRQ info */
+				   <0 172 4>,			/* Tx complete ring id #13 IRQ info */
+				   <0 173 4>,			/* Tx complete ring id #14 IRQ info */
+				   <0 174 4>,			/* Tx complete ring id #15 IRQ info */
+				   <0 139 4>,			/* Rx desc ring id #12 IRQ info */
+				   <0 140 4>,			/* Rx desc ring id #13 IRQ info */
+				   <0 141 4>,			/* Rx desc ring id #14 IRQ info */
+				   <0 142 4>,			/* Rx desc ring id #15 IRQ info */
+				   <0 191 4>,			/* Misc error IRQ info */
+				<0 160 4>,			/* PPEDS Node #1(TxComp ring id #1) TxComplete IRQ info */
+				<0 128 4>,			/* PPEDS Node #1(Rx Desc ring id #1) Rx Desc IRQ info */
+				<0 152 4>,			/* PPEDS Node #1(RxFill Desc ring id #1) Rx Fill IRQ info */
+				<0 161 4>,			/* PPEDS Node #2(TxComp ring id #2) TxComplete IRQ info */
+				<0 129 4>,			/* PPEDS Node #2(Rx Desc ring id #2) Rx Desc IRQ info */
+				<0 153 4>,                      /* PPEDS Node #2(RxFill Desc ring id #2) Rx Fill IRQ info */
+				<0 175 4>,                   /* MHT port Tx complete ring id #16 IRQ info */
+				<0 176 4>,                   /* MHT port Tx complete ring id #17 IRQ info */
+				<0 177 4>,                   /* MHT port Tx complete ring id #18 IRQ info */
+				<0 178 4>,                   /* MHT port Tx complete ring id #19 IRQ info */
+				<0 179 4>,                   /* MHT port Tx complete ring id #20 IRQ info */
+				<0 180 4>,                   /* MHT port Tx complete ring id #21 IRQ info */
+				<0 181 4>,                   /* MHT port Tx complete ring id #22 IRQ info */
+				<0 182 4>;                   /* MHT port Tx complete ring id #23 IRQ info */
+		};
+
+		leds {
+			compatible = "gpio-leds";
+			pinctrl-0 = <&led_pins>;
+			pinctrl-names = "default";
+			led_blue{
+				label = "led_blue";
+				gpio = <&tlmm 22 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "led_blue";
+				default-state = "off";
+			};
+			led_green {
+				label = "led_green";
+				gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "led_green";
+				default-state = "on";
+			};
+			led_white {
+				label = "led_white";
+				gpio = <&tlmm 32 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "led_white";
+				default-state = "off";
+			};
+			led_red {
+				label = "led_red";
+				gpio = <&tlmm 44 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "led_red";
+				default-state = "off";
+			};
+		};
+
+		gpio_keys {
+			compatible = "gpio-keys";
+			pinctrl-0 = <&button_pins>;
+			pinctrl-names = "default";
+			button@1 {
+				label = "reset";
+				linux,code = <KEY_RESTART>;
+				gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
+				linux,input-type = <1>;
+				debounce-interval = <60>;
+			};
+		};
+
+		wsi: wsi {
+			id = <0>;
+			num_chip = <2>;
+			status = "okay";
+			chip_info = <0 1 1>,
+				    <1 1 0>;
+		};
+	};
+};
+
+&wifi0 {
+	led-gpio = <&tlmm 36 GPIO_ACTIVE_HIGH>;
+	qcom,rproc = <&q6_wcss_pd1>;
+	qcom,rproc_rpd = <&q6v5_wcss>;
+	qcom,multipd_arch;
+	qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
+	memory-region = <&q6_region>;
+	qcom,wsi = <&wsi>;
+	qcom,wsi_index = <0>;
+	qcom,board_id = <0x12>;
+	status = "okay";
+};
+
+&qcn9224_pcie1 {
+	status = "okay";
+};
+
+&blsp1_uart0 {
+	pinctrl-0 = <&serial_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&blsp1_uart1 {
+	pinctrl-0 = <&serial_1_pins>;
+	pinctrl-names = "default";
+	status = "disabled";
+};
+
+&blsp1_spi0 {
+	pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	flash@0 {
+		compatible = "n25q128a11", "micron,n25q128a11", "jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&sdhc {
+	bus-width = <4>;
+	max-frequency = <192000000>;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	non-removable;
+	pinctrl-0 = <&sdc_default_state>;
+	pinctrl-names = "default";
+	status = "disabled";
+};
+
+&sleep_clk {
+	clock-frequency = <32000>;
+};
+
+&xo {
+	clock-frequency = <24000000>;
+};
+
+&qpic_bam {
+	status = "okay";
+};
+
+&qpic_nand {
+	pinctrl-0 = <&qspi_default_state>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	nandcs@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		nand-ecc-strength = <8>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+	};
+};
+
+&pcie1_phy_x2 {
+	status = "okay";
+};
+
+&pcie1 {
+	pinctrl-0 = <&pcie1_default_state>;
+	pinctrl-names = "default";
+	perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+	pcie1_rp {
+		reg = <0 0 0 0 0>;
+
+		qcom,mhi@1 {
+			reg = <0 0 0 0 0>;
+			boot-args = <0x2 0x4 0x34 0x3 0x0 0x0     /* MX Rail, GPIO52, Drive strength 0x3 */
+					0x4 0x4 0x18 0x3 0x0 0x0  /* RFA1p2 Rail, GPIO24, Drive strength 0x3 */
+					0x0 0x4 0x0 0x0 0x0 0x0>; /* End of arguments */
+			memory-region = <&qcn9224_pcie1>;
+			qcom,wsi = <&wsi>;
+			qcom,wsi_index = <1>;
+			qcom,board_id = <0x1019>;
+		};
+	};
+};
+
+/* PINCTRL */
+
+&tlmm {
+
+	led_pins: led_pins {
+		led_blue {
+			pins = "gpio22";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		led_green {
+			pins = "gpio31";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		led_white {
+			pins = "gpio32";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		led_red {
+			pins = "gpio44";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
+
+	sdc_default_state: sdc-default-state {
+		clk-pins {
+			pins = "gpio13";
+			function = "sdc_clk";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		cmd-pins {
+			pins = "gpio12";
+			function = "sdc_cmd";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		data-pins {
+			pins = "gpio8", "gpio9", "gpio10", "gpio11";
+			function = "sdc_data";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	spi_0_data_clk_pins: spi-0-data-clk-state {
+		pins = "gpio14", "gpio15", "gpio16";
+		function = "blsp0_spi";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	spi_0_cs_pins: spi-0-cs-state {
+		pins = "gpio17";
+		function = "blsp0_spi";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
+	qspi_default_state: qspi-default-state {
+		qspi_clock {
+			pins = "gpio13";
+			function = "qspi_clk";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		qspi_cs {
+			pins = "gpio12";
+			function = "qspi_cs";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		qspi_data {
+			pins = "gpio8", "gpio9", "gpio10", "gpio11";
+			function = "qspi_data";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
+	serial_1_pins: serial1-pinmux {
+		pins = "gpio33", "gpio34", "gpio35", "gpio36";
+		function = "blsp1_uart2";
+		drive-strength = <8>;
+		bias-pull-up;
+	};
+
+	button_pins: button-state {
+		pins = "gpio30";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-up;
+	};
+
+	pwm_pins: pwm-state {
+		pins = "gpio46";
+		function = "pwm0";
+		drive-strength = <8>;
+	};
+
+	pcie1_default_state: pcie1-default-state {
+		pins = "gpio47";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-up;
+		output-low;
+	};
+};
+
+&license_manager {
+	status = "okay";
+};
+
+&usb3 {
+	qcom,multiplexed-phy;
+	status = "okay";
+};
+
+&pwm {
+	pinctrl-0 = <&pwm_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&hs_m31phy_0 {
+	status = "okay";
+};
+
+&ssuniphy_0 {
+	status = "okay";
+};

feeds/qca-wifi-7/ipq53xx/image/ipq53xx.mk

@@ -119,3 +119,18 @@ define Device/cig_wf189h
   DEVICE_PACKAGES := ath12k-wifi-cig-wf189h ath12k-firmware-ipq5332-peb-peb
 endef
 TARGET_DEVICES += cig_wf189h
+
+define Device/zyxel_nwa130be
+  DEVICE_TITLE := Zyxel NWA130BE
+  DEVICE_DTS := ipq5332-zyxel-nwa130be
+  DEVICE_DTS_DIR := ../dts
+  DEVICE_DTS_CONFIG := config@mi01.6
+  IMAGES := sysupgrade.tar nand-factory.bin nand-factory.ubi
+  BLOCKSIZE := 256k
+  PAGESIZE := 4096
+  IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata
+  IMAGE/nand-factory.bin := append-ubi | qsdk-ipq-factory-nand
+  IMAGE/nand-factory.ubi := append-ubi
+  DEVICE_PACKAGES := ath12k-wifi-zyxel-nwa130be ath12k-firmware-qcn92xx ath12k-firmware-ipq5332
+endef
+TARGET_DEVICES += zyxel_nwa130be

feeds/qca-wifi-7/mac80211/Makefile

@@ -262,6 +262,11 @@ define KernelPackage/mt7601u
   AUTOLOAD:=$(call AutoProbe,mt7601u)
 endef
 
+ifdef CONFIG_TARGET_PROFILE
+TARGET_PROFILE=$(subst ",,$(CONFIG_TARGET_PROFILE))
+PATCH_PROFILE_NAME=patches-$(subst DEVICE_,,$(TARGET_PROFILE))
+endif
+
 ifdef CONFIG_PACKAGE_MAC80211_DEBUGFS
   config-y += \
 	CFG80211_DEBUGFS \
@@ -362,6 +367,7 @@ define Build/Patch
 	$(call PatchDir,$(PKG_BUILD_DIR),$(EXTERNAL_PATCH_DIR)/ath12k,ath12k/)
 	$(call PatchDir,$(PKG_BUILD_DIR),$(EXTERNAL_PATCH_DIR)/pending,pending/)
 	$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_TIP_DIR)/pending,pending/)
+	$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_PROFILE_NAME)/ath12k,ath12k/)
 	$(if $(QUILT),touch $(PKG_BUILD_DIR)/.quilt_used)
 endef
 

feeds/qca-wifi-7/mac80211/patches-zyxel_nwa130be/0001-thermal-thermal-setting.patch

@@ -0,0 +1,59 @@
+From 1a46aa106a50a06bfa4b669d87a8143c3d59f2f4 Mon Sep 17 00:00:00 2001
+From: YenLin Pan <yenlin.pan@zyxel.com.tw>
+Date: Wed, 14 May 2025 14:14:22 +0800
+Subject: [PATCH] thermal: thermal setting
+
+lv0 -100 -hi0 105 -off0 0
+lv1 95   -hi1 110 -off1 75
+lv2 100  -hi2 115 -off2 98
+lv3 105  -hi3 120 -off3 100
+
+Signed-off-by: YenLin Pan <YenLin.Pan@zyxel.com.tw>
+---
+ drivers/net/wireless/ath/ath12k/thermal.h | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath12k/thermal.h b/drivers/net/wireless/ath/ath12k/thermal.h
+index 5c91906..a493cd5 100644
+--- a/drivers/net/wireless/ath/ath12k/thermal.h
++++ b/drivers/net/wireless/ath/ath12k/thermal.h
+@@ -13,28 +13,28 @@
+ 
+ /* Below temperatures are in celsius */
+ #define ATH12K_THERMAL_LVL0_TEMP_LOW_MARK -100
+-#define ATH12K_THERMAL_LVL0_TEMP_HIGH_MARK 100
++#define ATH12K_THERMAL_LVL0_TEMP_HIGH_MARK 105
+ #define ATH12K_THERMAL_LVL1_TEMP_LOW_MARK 95
+-#define ATH12K_THERMAL_LVL1_TEMP_HIGH_MARK 105
++#define ATH12K_THERMAL_LVL1_TEMP_HIGH_MARK 110
+ #define ATH12K_THERMAL_LVL2_TEMP_LOW_MARK 100
+-#define ATH12K_THERMAL_LVL2_TEMP_HIGH_MARK 110
++#define ATH12K_THERMAL_LVL2_TEMP_HIGH_MARK 115
+ #define ATH12K_THERMAL_LVL3_TEMP_LOW_MARK 105
+ #define ATH12K_THERMAL_LVL3_TEMP_HIGH_MARK 120
+ 
+ #define ATH12K_THERMAL_LVL0_V2_TEMP_LOW_MARK -100
+-#define ATH12K_THERMAL_LVL0_V2_TEMP_HIGH_MARK 95
++#define ATH12K_THERMAL_LVL0_V2_TEMP_HIGH_MARK 105
+ #define ATH12K_THERMAL_LVL1_V2_TEMP_LOW_MARK 90
+-#define ATH12K_THERMAL_LVL1_V2_TEMP_HIGH_MARK 100
++#define ATH12K_THERMAL_LVL1_V2_TEMP_HIGH_MARK 110
+ #define ATH12K_THERMAL_LVL2_V2_TEMP_LOW_MARK 95
+ #define ATH12K_THERMAL_LVL2_V2_TEMP_HIGH_MARK 105
+ #define ATH12K_THERMAL_LVL3_V2_TEMP_LOW_MARK 100
+-#define ATH12K_THERMAL_LVL3_V2_TEMP_HIGH_MARK 110
++#define ATH12K_THERMAL_LVL3_V2_TEMP_HIGH_MARK 115
+ #define ATH12K_THERMAL_LVL4_V2_TEMP_LOW_MARK 105
+ #define ATH12K_THERMAL_LVL4_V2_TEMP_HIGH_MARK 120
+ 
+ #define ATH12K_THERMAL_LVL0_DUTY_CYCLE 0
+-#define ATH12K_THERMAL_LVL1_DUTY_CYCLE 50
+-#define ATH12K_THERMAL_LVL2_DUTY_CYCLE 90
++#define ATH12K_THERMAL_LVL1_DUTY_CYCLE 75
++#define ATH12K_THERMAL_LVL2_DUTY_CYCLE 98
+ #define ATH12K_THERMAL_LVL3_DUTY_CYCLE 100
+ 
+ #define ATH12K_THERMAL_LVL0_V2_DUTY_CYCLE ATH12K_THERMAL_LVL0_DUTY_CYCLE
+-- 
+2.34.1
+

feeds/qca-wifi-7/qca-ssdk-qca/Makefile

@@ -97,6 +97,11 @@ else ifneq ($(CONFIG_ARCH),)
 			      TARGET_NAME=$(subst ",,$(CONFIG_ARCH))-openwrt-linux$(if $(CONFIG_TARGET_SUFFIX),-$(subst ",,$(CONFIG_TARGET_SUFFIX)))
 endif
 
+ifdef CONFIG_TARGET_PROFILE
+TARGET_PROFILE=$(subst ",,$(CONFIG_TARGET_PROFILE))
+PATCH_PROFILE_NAME=patches-$(subst DEVICE_,,$(TARGET_PROFILE))
+endif
+
 QCASSDK_CONFIG_OPTS+= TOOL_PATH=$(TOOLCHAIN_BIN_PATH) \
                 SYS_PATH=$(LINUX_DIR) \
                 TOOLPREFIX=$(TARGET_CROSS) \
@@ -193,5 +198,10 @@ define KernelPackage/qca-ssdk-qca-hnat/install
 	$(INSTALL_BIN) ./files/qca-ssdk $(1)/etc/init.d/qca-ssdk
 endef
 
+define patch_profile
+	$(call PatchDir/Default,$(PKG_BUILD_DIR),./$(PATCH_PROFILE_NAME))
+endef
+
+Hooks/Prepare/Post += patch_profile
 $(eval $(call KernelPackage,qca-ssdk-qca-nohnat))
 $(eval $(call KernelPackage,qca-ssdk-qca-hnat))

feeds/qca-wifi-7/qca-ssdk-qca/patches-zyxel_nwa130be/0001-pinctrl-make-the-switch-LED-works.patch

@@ -0,0 +1,47 @@
+From 7fa9e9b683f1c573c58a14755347988919bc7d06 Mon Sep 17 00:00:00 2001
+From: YenLin Pan <yenlin.pan@zyxel.com.tw>
+Date: Wed, 14 May 2025 13:47:06 +0800
+Subject: [PATCH] pinctrl: make the switch LED works
+
+Enable switch LED pin definition for LED0/LED1/LED2 control
+
+Signed-off-by: YenLin Pan <YenLin.Pan@zyxel.com.tw>
+---
+ src/init/ssdk_mht_pinctrl.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/src/init/ssdk_mht_pinctrl.c b/src/init/ssdk_mht_pinctrl.c
+index 2debe59..1ae0002 100755
+--- a/src/init/ssdk_mht_pinctrl.c
++++ b/src/init/ssdk_mht_pinctrl.c
+@@ -33,11 +33,17 @@ static struct mht_pinctrl_setting mht_pin_settings[] = {
+     /*PINs default MUX Setting*/
+     MHT_PIN_SETTING_MUX(0,  MHT_PIN_FUNC_INTN_WOL),
+     MHT_PIN_SETTING_MUX(1,  MHT_PIN_FUNC_INTN),
+-#if 0
++#if 1
+     MHT_PIN_SETTING_MUX(2,  MHT_PIN_FUNC_P0_LED_0),
+     MHT_PIN_SETTING_MUX(3,  MHT_PIN_FUNC_P1_LED_0),
+     MHT_PIN_SETTING_MUX(4,  MHT_PIN_FUNC_P2_LED_0),
+     MHT_PIN_SETTING_MUX(5,  MHT_PIN_FUNC_P3_LED_0),
++    MHT_PIN_SETTING_MUX(6,  MHT_PIN_FUNC_P0_LED_2),
++    MHT_PIN_SETTING_MUX(7,  MHT_PIN_FUNC_P1_LED_2),
++    MHT_PIN_SETTING_MUX(8,  MHT_PIN_FUNC_P2_LED_2),
++    MHT_PIN_SETTING_MUX(9,  MHT_PIN_FUNC_P3_LED_2),
++#endif
++#if 0
+     MHT_PIN_SETTING_MUX(6,  MHT_PIN_FUNC_PPS_IN),
+     MHT_PIN_SETTING_MUX(7,  MHT_PIN_FUNC_TOD_IN),
+     MHT_PIN_SETTING_MUX(8,  MHT_PIN_FUNC_RTC_REFCLK_IN),
+@@ -49,7 +55,7 @@ static struct mht_pinctrl_setting mht_pin_settings[] = {
+     MHT_PIN_SETTING_MUX(13, MHT_PIN_FUNC_P0_TOD_OUT),
+     MHT_PIN_SETTING_MUX(14, MHT_PIN_FUNC_P0_CLK125_TDI),
+     MHT_PIN_SETTING_MUX(15, MHT_PIN_FUNC_P0_SYNC_CLKO_PTP),
+-#if 0
++#if 1
+     MHT_PIN_SETTING_MUX(16, MHT_PIN_FUNC_P0_LED_1),
+     MHT_PIN_SETTING_MUX(17, MHT_PIN_FUNC_P1_LED_1),
+     MHT_PIN_SETTING_MUX(18, MHT_PIN_FUNC_P2_LED_1),
+-- 
+2.34.1
+

feeds/tip/cloud_discovery/Makefile

@@ -12,7 +12,6 @@ define Package/cloud_discovery
   SECTION:=ucentral
   CATEGORY:=uCentral
   TITLE:=TIP cloud_discovery
-  DEPENDS:=+libest
 endef
 
 Build/Compile=

feeds/ucentral/rrmd/files/usr/share/rrmd/policy_chanutil.uc

@@ -19,6 +19,7 @@ switch(board_name) {
 case 'edgecore,eap105':
 case 'edgecore,oap101-6e':
 case 'edgecore,oap101e-6e':
+case 'zyxel,nwa130be':
     num_radios = 3;
     break;
 }

feeds/ucentral/ucentral-schema/Makefile

@@ -4,10 +4,10 @@ PKG_NAME:=ucentral-schema
 PKG_RELEASE:=1
 
 PKG_SOURCE_URL=https://github.com/Telecominfraproject/wlan-ucentral-schema.git
-PKG_MIRROR_HASH:=4788da65803c8674c5d983b2be6d50960708d7adb1bd86cbf62a763b88a1f6d8
+PKG_MIRROR_HASH:=cbb6508faa5e0b640e1990a806383f9f13fb5da75f38114f4f32e9c14b9845f1
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_DATE:=2025-01-27
-PKG_SOURCE_VERSION:=6faaa1f655e3fbf4b5f915c9782634a5a89c2be7
+PKG_SOURCE_VERSION:=9710867e1a2c775fa424fd7780ba6132eaa6fd9c
 PKG_MAINTAINER:=John Crispin <john@phrozen.org>
 PKG_LICENSE:=BSD-3-Clause
 

profiles/zyxel_nwa130be.yml

@@ -0,0 +1,16 @@
+---
+profile: zyxel_nwa130be
+target: ipq53xx
+subtarget: generic
+description: Build image for the zyxel nwa130be
+image: bin/targets/ipq53xx/generic/openwrt-ipq53xx-zyxel_nwa130be-squashfs-sysupgrade.tar
+feeds:
+  - name: qca
+    path: ../../feeds/qca-wifi-7
+packages:
+  - ipq53xx
+  - qca-ssdk-shell
+include:
+  - ucentral-ap
+diffconfig: |
+  CONFIG_KERNEL_IPQ_MEM_PROFILE=0