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https://github.com/Telecominfraproject/wlan-ap.git
synced 2025-10-29 17:42:41 +00:00
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1 Commits
v4.0.0-rc3
...
staging-WI
| Author | SHA1 | Date | |
|---|---|---|---|
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553f894dc7 |
@@ -44,11 +44,9 @@
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uniphyaddr_fixup = <0xC90F014>;
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mdio_clk_fixup; /* MDIO clock sequence fix up flag */
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tip,clk_div = <0xff>; /* MDIO Frequency reduction*/
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limit_rtlphy_10g_ablity;
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phy0: ethernet-phy@0 {
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reg = <8>;
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compatible ="ethernet-phy-ieee802.3-c45";
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};
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phy1: ethernet-phy@1 {
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20
feeds/qca-wifi-7/ipq53xx/files-6.1/drivers/net/phy/rtk/rtk_phy.c
Normal file → Executable file
20
feeds/qca-wifi-7/ipq53xx/files-6.1/drivers/net/phy/rtk/rtk_phy.c
Normal file → Executable file
@@ -7,7 +7,6 @@
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include "phy_rtl826xb_patch.h"
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#include "phy_rtl8251b_patch.h"
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@@ -31,7 +30,6 @@ static int rtl8251_match_phy_device(struct phy_device *phydev)
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static int rtl826xb_get_features(struct phy_device *phydev)
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{
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int ret;
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struct device_node *np;
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ret = genphy_c45_pma_read_abilities(phydev);
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if (ret)
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return ret;
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@@ -50,14 +48,6 @@ static int rtl826xb_get_features(struct phy_device *phydev)
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linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
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phydev->supported);
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np = of_find_node_by_name(NULL, "mdio");
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if (np)
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if (of_property_read_bool(np, "limit_rtlphy_10g_ablity"))
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{
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linkmode_clear_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, phydev->supported);
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}
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return 0;
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}
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@@ -90,6 +80,7 @@ static int rtkphy_config_init(struct phy_device *phydev)
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case REALTEK_PHY_ID_RTL8261N:
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case REALTEK_PHY_ID_RTL8264B:
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phydev_info(phydev, "%s:%u [RTL8261N/RTL826XB] phy_id: 0x%X PHYAD:%d\n", __FUNCTION__, __LINE__, phydev->drv->phy_id, phydev->mdio.addr);
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phy_modify_mmd_changed(phydev, 7, 0x20, BIT(12), 0);
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#if 1 /* toggle reset */
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phy_modify_mmd_changed(phydev, 30, 0x145, BIT(0) , 1);
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@@ -222,6 +213,7 @@ static int rtkphy_c45_aneg_done(struct phy_device *phydev)
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static int rtkphy_c45_read_status(struct phy_device *phydev)
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{
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int ret = 0, status = 0;
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uint16_t local;
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phydev->speed = SPEED_UNKNOWN;
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phydev->duplex = DUPLEX_UNKNOWN;
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phydev->pause = 0;
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@@ -240,6 +232,9 @@ static int rtkphy_c45_read_status(struct phy_device *phydev)
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if (ret)
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return ret;
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phy_write_mmd(phydev, 7, 0x20, 0x181);
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local = phy_read_mmd(phydev, 7, 0x20);
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status = phy_read_mmd(phydev, 31, 0xA414);
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if (status < 0)
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return status;
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@@ -247,6 +242,11 @@ static int rtkphy_c45_read_status(struct phy_device *phydev)
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phydev->lp_advertising, status & BIT(11));
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phy_resolve_aneg_linkmode(phydev);
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if((phydev->speed == 10000) && (local == 0x181))
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{
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phydev->speed = 5000;
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phydev->duplex = DUPLEX_FULL;
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}
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}
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else
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{
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@@ -1,116 +0,0 @@
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From 85a7c62d4e3385de1a379959dd45148cfdc95b3b Mon Sep 17 00:00:00 2001
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From: huangyunxiang <huangyunxiang@cigtech.com>
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Date: Tue, 29 Apr 2025 09:56:28 +0800
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Subject: [PATCH] qca-ssdk modify rtl826x phy mdio read/write as c45 mode and
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clear 10G ablity
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---
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src/hsl/phy/rtl826xb_phy.c | 55 ++++++-------------
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1 file changed, 17 insertions(+), 38 deletions(-)
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diff --git a/src/hsl/phy/rtl826xb_phy.c b/src/hsl/phy/rtl826xb_phy.c
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index a336348aa9..9a67b45948 100644
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--- a/src/hsl/phy/rtl826xb_phy.c
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+++ b/src/hsl/phy/rtl826xb_phy.c
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@@ -48,46 +48,39 @@ void rtl826xb_phy_lock_init(void)
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static a_uint16_t rtl826x_phy_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_mmd, a_uint16_t reg_id)
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{
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- a_uint32_t reg_id_c45 = RTL826XB_REG_ADDRESS(reg_mmd, reg_id);
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-
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- return __hsl_phy_mii_reg_read(dev_id, phy_id, reg_id_c45);
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+ return hsl_phy_mmd_reg_read(dev_id, phy_id, A_TRUE, reg_mmd, reg_id);
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}
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static sw_error_t rtl826x_phy_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_mmd, a_uint16_t reg_id, a_uint16_t reg_val)
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{
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- a_uint32_t reg_id_c45 = RTL826XB_REG_ADDRESS(reg_mmd, reg_id);
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-
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- return __hsl_phy_mii_reg_write(dev_id, phy_id, reg_id_c45, reg_val);
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+ return hsl_phy_mmd_reg_write(dev_id, phy_id, A_TRUE, reg_mmd, reg_id, reg_val);
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}
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static a_uint16_t rtl826x_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg)
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{
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- return __hsl_phy_mii_reg_read(dev_id, phy_id, reg);
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+ return hsl_phy_mii_reg_read(dev_id, phy_id, reg);
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}
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static sw_error_t rtl826x_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg, a_uint16_t reg_val)
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{
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- return __hsl_phy_mii_reg_write(dev_id, phy_id, reg, reg_val);
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+
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+ return hsl_phy_mii_reg_write(dev_id, phy_id, reg, reg_val);
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}
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static a_int16_t hal_miim_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t mmdAddr, a_uint16_t mmdReg)
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{
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- a_uint32_t reg_id_c45 = RTL826XB_REG_ADDRESS(mmdAddr, mmdReg);
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-
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- return __hsl_phy_mii_reg_read(dev_id, phy_id, reg_id_c45);
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+ return hsl_phy_mmd_reg_read(dev_id, phy_id, A_TRUE, mmdAddr, mmdReg);
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}
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static a_int32_t hal_miim_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t mmdAddr, a_uint16_t mmdReg, a_uint16_t phy_data)
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{
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- a_uint32_t reg_id_c45 = RTL826XB_REG_ADDRESS(mmdAddr, mmdReg);
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-
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- return __hsl_phy_mii_reg_write(dev_id, phy_id, reg_id_c45, phy_data);
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+ return hsl_phy_mmd_reg_write(dev_id, phy_id, A_TRUE, mmdAddr, mmdReg, phy_data);
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}
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@@ -1281,34 +1274,20 @@ phy_826xb_autoNegoAbility_set(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t a
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hsl_phy_phydev_autoneg_update(dev_id, phy_id, A_TRUE, autoneg);
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phyData = phy_common_general_reg_mmd_get(dev_id, phy_id, PHY_MMD_AN, 16);
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+ phyData &= (~(0x0020 | 0x0040 | FAL_PHY_ADV_100TX_HD | FAL_PHY_ADV_100TX_FD | FAL_PHY_ADV_PAUSE | FAL_PHY_ADV_ASY_PAUSE));
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+ phyData |= (autoneg & FAL_PHY_ADV_100TX_HD) ? (FAL_PHY_ADV_100TX_HD) : (0);
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+ phyData |= ((autoneg & FAL_PHY_ADV_100TX_FD)) ? (FAL_PHY_ADV_100TX_FD) : (0);
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- phyData &= (~(0x0020 | 0x0040 | 0x0080 | 0x0100 | 0x0400 | 0x0800));
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- phyData |= ((autoneg & 1 << 1)) ? (0x0040) : (0);
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- phyData |= ((autoneg & 1 << 2)) ? (0x0080) : (0);
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- phyData |= ((autoneg & 1 << 3)) ? (0x0100) : (0);
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- phyData |= ((autoneg & 1 << 4)) ? (0x0400) : (0);
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- phyData |= ((autoneg & 1 << 5)) ? (0x0800) : (0);
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-// phyData |= ((autoneg & 1 << 9)) ? (0x0400) : (0);
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-// phyData |= ((autoneg & 1 << 10)) ? (0x0800) : (0);
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-
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- phy_common_general_reg_mmd_set(dev_id, phy_id, PHY_MMD_AN, 16, phyData);
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-
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+ phy_common_general_reg_mmd_set(dev_id, phy_id, PHY_MMD_AN, 16, phyData);
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phyData = phy_common_general_reg_mmd_get(dev_id, phy_id, PHY_MMD_AN, 32);
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+ phyData &= (~(FAL_PHY_ADV_2500T_FD | FAL_PHY_ADV_5000T_FD | FAL_PHY_ADV_10000T_FD));
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+ phyData |= (autoneg & FAL_PHY_ADV_2500T_FD) ? (FAL_PHY_ADV_2500T_FD) : (0);
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+ phyData |= (autoneg & FAL_PHY_ADV_5000T_FD) ? (FAL_PHY_ADV_5000T_FD) : (0);
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- phyData &= (~(0x4000 | 0x2000 | 0x1000));
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- phyData |= (autoneg & 1 << 12) ? (0x0080) : (0);
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- phyData |= (autoneg & 1 << 13) ? (0x0100) : (0);
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- phyData |= (autoneg & 1 << 14) ? (0x1000) : (0);
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-
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- phy_common_general_reg_mmd_set(dev_id, phy_id, PHY_MMD_AN, 32, phyData);
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-
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-
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+ phy_common_general_reg_mmd_set(dev_id, phy_id, PHY_MMD_AN, 32, phyData);
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phyData = phy_common_general_reg_mmd_get(dev_id, phy_id, PHY_MMD_VEND2, 0xA412);
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-
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-
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- phyData &= (~(0x0100 | 0x0200));
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- phyData |= (autoneg & 1 << 9) ? (0x0200) : (0);
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-// phyData |= (autoneg & 1 << 5) ? (0x0200) : (0);
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+ phyData &= (~(0x0100 | FAL_PHY_ADV_1000T_FD));
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+ phyData |= (autoneg & FAL_PHY_ADV_1000T_FD) ? (FAL_PHY_ADV_1000T_FD) : (0);
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phy_common_general_reg_mmd_set(dev_id, phy_id, PHY_MMD_VEND2, 0xA412, phyData);
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--
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2.34.1
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@@ -4,10 +4,10 @@ PKG_NAME:=ucentral-schema
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PKG_RELEASE:=1
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PKG_SOURCE_URL=https://github.com/Telecominfraproject/wlan-ucentral-schema.git
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PKG_MIRROR_HASH:=280d87658fa36c1d5d6852dcb8203042eba6bbc9101ac317a2088e2dd68249da
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PKG_MIRROR_HASH:=cd070141672c85e72001e2e36616aa7159c6dc8ca4bbacca1b61a41c145cde2f
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PKG_SOURCE_PROTO:=git
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PKG_SOURCE_DATE:=2025-01-27
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PKG_SOURCE_VERSION:=52afdf8f1d1cb8445b6b56eba3768d0edffa63e1
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PKG_SOURCE_VERSION:=048a53d4a6cf3ef570dab9e2d10989844ae7c355
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PKG_MAINTAINER:=John Crispin <john@phrozen.org>
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PKG_LICENSE:=BSD-3-Clause
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