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Author SHA1 Message Date
alex18_huang
553f894dc7 WIFI-14564: Multiple ssids sometime didn't display dhcp option 82 rules
Added check when parsing ssid info retrieved from iwinfo.
Program will exit if expected interface count and iwinfo entry count mismatch.

Signed-off-by: alex18_huang <alex18_huang@accton.com>
2025-04-28 13:57:05 +08:00
4 changed files with 12 additions and 130 deletions

View File

@@ -44,11 +44,9 @@
uniphyaddr_fixup = <0xC90F014>;
mdio_clk_fixup; /* MDIO clock sequence fix up flag */
tip,clk_div = <0xff>; /* MDIO Frequency reduction*/
limit_rtlphy_10g_ablity;
phy0: ethernet-phy@0 {
reg = <8>;
compatible ="ethernet-phy-ieee802.3-c45";
};
phy1: ethernet-phy@1 {

View File

@@ -7,7 +7,6 @@
#include <linux/module.h>
#include <linux/phy.h>
#include <linux/delay.h>
#include <linux/of.h>
#include "phy_rtl826xb_patch.h"
#include "phy_rtl8251b_patch.h"
@@ -31,7 +30,6 @@ static int rtl8251_match_phy_device(struct phy_device *phydev)
static int rtl826xb_get_features(struct phy_device *phydev)
{
int ret;
struct device_node *np;
ret = genphy_c45_pma_read_abilities(phydev);
if (ret)
return ret;
@@ -50,14 +48,6 @@ static int rtl826xb_get_features(struct phy_device *phydev)
linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
phydev->supported);
np = of_find_node_by_name(NULL, "mdio");
if (np)
if (of_property_read_bool(np, "limit_rtlphy_10g_ablity"))
{
linkmode_clear_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, phydev->supported);
}
return 0;
}
@@ -90,6 +80,7 @@ static int rtkphy_config_init(struct phy_device *phydev)
case REALTEK_PHY_ID_RTL8261N:
case REALTEK_PHY_ID_RTL8264B:
phydev_info(phydev, "%s:%u [RTL8261N/RTL826XB] phy_id: 0x%X PHYAD:%d\n", __FUNCTION__, __LINE__, phydev->drv->phy_id, phydev->mdio.addr);
phy_modify_mmd_changed(phydev, 7, 0x20, BIT(12), 0);
#if 1 /* toggle reset */
phy_modify_mmd_changed(phydev, 30, 0x145, BIT(0) , 1);
@@ -222,6 +213,7 @@ static int rtkphy_c45_aneg_done(struct phy_device *phydev)
static int rtkphy_c45_read_status(struct phy_device *phydev)
{
int ret = 0, status = 0;
uint16_t local;
phydev->speed = SPEED_UNKNOWN;
phydev->duplex = DUPLEX_UNKNOWN;
phydev->pause = 0;
@@ -240,6 +232,9 @@ static int rtkphy_c45_read_status(struct phy_device *phydev)
if (ret)
return ret;
phy_write_mmd(phydev, 7, 0x20, 0x181);
local = phy_read_mmd(phydev, 7, 0x20);
status = phy_read_mmd(phydev, 31, 0xA414);
if (status < 0)
return status;
@@ -247,6 +242,11 @@ static int rtkphy_c45_read_status(struct phy_device *phydev)
phydev->lp_advertising, status & BIT(11));
phy_resolve_aneg_linkmode(phydev);
if((phydev->speed == 10000) && (local == 0x181))
{
phydev->speed = 5000;
phydev->duplex = DUPLEX_FULL;
}
}
else
{

View File

@@ -1,116 +0,0 @@
From 85a7c62d4e3385de1a379959dd45148cfdc95b3b Mon Sep 17 00:00:00 2001
From: huangyunxiang <huangyunxiang@cigtech.com>
Date: Tue, 29 Apr 2025 09:56:28 +0800
Subject: [PATCH] qca-ssdk modify rtl826x phy mdio read/write as c45 mode and
clear 10G ablity
---
src/hsl/phy/rtl826xb_phy.c | 55 ++++++-------------
1 file changed, 17 insertions(+), 38 deletions(-)
diff --git a/src/hsl/phy/rtl826xb_phy.c b/src/hsl/phy/rtl826xb_phy.c
index a336348aa9..9a67b45948 100644
--- a/src/hsl/phy/rtl826xb_phy.c
+++ b/src/hsl/phy/rtl826xb_phy.c
@@ -48,46 +48,39 @@ void rtl826xb_phy_lock_init(void)
static a_uint16_t rtl826x_phy_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_mmd, a_uint16_t reg_id)
{
- a_uint32_t reg_id_c45 = RTL826XB_REG_ADDRESS(reg_mmd, reg_id);
-
- return __hsl_phy_mii_reg_read(dev_id, phy_id, reg_id_c45);
+ return hsl_phy_mmd_reg_read(dev_id, phy_id, A_TRUE, reg_mmd, reg_id);
}
static sw_error_t rtl826x_phy_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_mmd, a_uint16_t reg_id, a_uint16_t reg_val)
{
- a_uint32_t reg_id_c45 = RTL826XB_REG_ADDRESS(reg_mmd, reg_id);
-
- return __hsl_phy_mii_reg_write(dev_id, phy_id, reg_id_c45, reg_val);
+ return hsl_phy_mmd_reg_write(dev_id, phy_id, A_TRUE, reg_mmd, reg_id, reg_val);
}
static a_uint16_t rtl826x_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg)
{
- return __hsl_phy_mii_reg_read(dev_id, phy_id, reg);
+ return hsl_phy_mii_reg_read(dev_id, phy_id, reg);
}
static sw_error_t rtl826x_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg, a_uint16_t reg_val)
{
- return __hsl_phy_mii_reg_write(dev_id, phy_id, reg, reg_val);
+
+ return hsl_phy_mii_reg_write(dev_id, phy_id, reg, reg_val);
}
static a_int16_t hal_miim_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t mmdAddr, a_uint16_t mmdReg)
{
- a_uint32_t reg_id_c45 = RTL826XB_REG_ADDRESS(mmdAddr, mmdReg);
-
- return __hsl_phy_mii_reg_read(dev_id, phy_id, reg_id_c45);
+ return hsl_phy_mmd_reg_read(dev_id, phy_id, A_TRUE, mmdAddr, mmdReg);
}
static a_int32_t hal_miim_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t mmdAddr, a_uint16_t mmdReg, a_uint16_t phy_data)
{
- a_uint32_t reg_id_c45 = RTL826XB_REG_ADDRESS(mmdAddr, mmdReg);
-
- return __hsl_phy_mii_reg_write(dev_id, phy_id, reg_id_c45, phy_data);
+ return hsl_phy_mmd_reg_write(dev_id, phy_id, A_TRUE, mmdAddr, mmdReg, phy_data);
}
@@ -1281,34 +1274,20 @@ phy_826xb_autoNegoAbility_set(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t a
hsl_phy_phydev_autoneg_update(dev_id, phy_id, A_TRUE, autoneg);
phyData = phy_common_general_reg_mmd_get(dev_id, phy_id, PHY_MMD_AN, 16);
+ phyData &= (~(0x0020 | 0x0040 | FAL_PHY_ADV_100TX_HD | FAL_PHY_ADV_100TX_FD | FAL_PHY_ADV_PAUSE | FAL_PHY_ADV_ASY_PAUSE));
+ phyData |= (autoneg & FAL_PHY_ADV_100TX_HD) ? (FAL_PHY_ADV_100TX_HD) : (0);
+ phyData |= ((autoneg & FAL_PHY_ADV_100TX_FD)) ? (FAL_PHY_ADV_100TX_FD) : (0);
- phyData &= (~(0x0020 | 0x0040 | 0x0080 | 0x0100 | 0x0400 | 0x0800));
- phyData |= ((autoneg & 1 << 1)) ? (0x0040) : (0);
- phyData |= ((autoneg & 1 << 2)) ? (0x0080) : (0);
- phyData |= ((autoneg & 1 << 3)) ? (0x0100) : (0);
- phyData |= ((autoneg & 1 << 4)) ? (0x0400) : (0);
- phyData |= ((autoneg & 1 << 5)) ? (0x0800) : (0);
-// phyData |= ((autoneg & 1 << 9)) ? (0x0400) : (0);
-// phyData |= ((autoneg & 1 << 10)) ? (0x0800) : (0);
-
- phy_common_general_reg_mmd_set(dev_id, phy_id, PHY_MMD_AN, 16, phyData);
-
+ phy_common_general_reg_mmd_set(dev_id, phy_id, PHY_MMD_AN, 16, phyData);
phyData = phy_common_general_reg_mmd_get(dev_id, phy_id, PHY_MMD_AN, 32);
+ phyData &= (~(FAL_PHY_ADV_2500T_FD | FAL_PHY_ADV_5000T_FD | FAL_PHY_ADV_10000T_FD));
+ phyData |= (autoneg & FAL_PHY_ADV_2500T_FD) ? (FAL_PHY_ADV_2500T_FD) : (0);
+ phyData |= (autoneg & FAL_PHY_ADV_5000T_FD) ? (FAL_PHY_ADV_5000T_FD) : (0);
- phyData &= (~(0x4000 | 0x2000 | 0x1000));
- phyData |= (autoneg & 1 << 12) ? (0x0080) : (0);
- phyData |= (autoneg & 1 << 13) ? (0x0100) : (0);
- phyData |= (autoneg & 1 << 14) ? (0x1000) : (0);
-
- phy_common_general_reg_mmd_set(dev_id, phy_id, PHY_MMD_AN, 32, phyData);
-
-
+ phy_common_general_reg_mmd_set(dev_id, phy_id, PHY_MMD_AN, 32, phyData);
phyData = phy_common_general_reg_mmd_get(dev_id, phy_id, PHY_MMD_VEND2, 0xA412);
-
-
- phyData &= (~(0x0100 | 0x0200));
- phyData |= (autoneg & 1 << 9) ? (0x0200) : (0);
-// phyData |= (autoneg & 1 << 5) ? (0x0200) : (0);
+ phyData &= (~(0x0100 | FAL_PHY_ADV_1000T_FD));
+ phyData |= (autoneg & FAL_PHY_ADV_1000T_FD) ? (FAL_PHY_ADV_1000T_FD) : (0);
phy_common_general_reg_mmd_set(dev_id, phy_id, PHY_MMD_VEND2, 0xA412, phyData);
--
2.34.1

View File

@@ -4,10 +4,10 @@ PKG_NAME:=ucentral-schema
PKG_RELEASE:=1
PKG_SOURCE_URL=https://github.com/Telecominfraproject/wlan-ucentral-schema.git
PKG_MIRROR_HASH:=280d87658fa36c1d5d6852dcb8203042eba6bbc9101ac317a2088e2dd68249da
PKG_MIRROR_HASH:=cd070141672c85e72001e2e36616aa7159c6dc8ca4bbacca1b61a41c145cde2f
PKG_SOURCE_PROTO:=git
PKG_SOURCE_DATE:=2025-01-27
PKG_SOURCE_VERSION:=52afdf8f1d1cb8445b6b56eba3768d0edffa63e1
PKG_SOURCE_VERSION:=048a53d4a6cf3ef570dab9e2d10989844ae7c355
PKG_MAINTAINER:=John Crispin <john@phrozen.org>
PKG_LICENSE:=BSD-3-Clause