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mec1322: keep 32KHz on for ROSC accuracy

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32KHz osc is necessary to key ROSC in +-2% accuracy.
If 32KHz osc is off/on during the heavy sleep, UART produces
garbage characters to Tx port until its clock to be stabilized.

BUG=none
TEST=Cyan
BRANCH=none

Change-Id: Ie045b9f152eb7dc8d888a2840babefac68081cef
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/288421
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
This commit is contained in:
Kyoung Kim
2015-07-24 16:36:16 -07:00
committed by ChromeOS Commit Bot
parent 4ff95401b5
commit 0183e3cc7f
1 changed files with 1 additions and 7 deletions
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8
chip/mec1322/clock.c
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@@ -164,9 +164,6 @@ static void prepare_for_deep_sleep(void)
CPU_NVIC_ST_CTRL &= ~ST_ENABLE;
CPU_NVIC_ST_CTRL &= ~ST_COUNTFLAG;
/* Disable 32KHz clock */
MEC1322_VBAT_CE &= ~0x2;
/* Disable JTAG */
MEC1322_EC_JTAG_EN &= ~1;
/* Power down ADC VREF, ADC_VREF overrides ADC_CTRL. */
@@ -212,9 +209,6 @@ static void resume_from_deep_sleep(void)
/* Enable watchdog */
MEC1322_WDG_CTL |= 1;
/* Enable 32KHz clock */
MEC1322_VBAT_CE |= 0x2;
MEC1322_PCR_SLOW_CLK_CTL |= 0x1e0;
MEC1322_PCR_CHIP_SLP_EN &= ~0x3;
MEC1322_PCR_EC_SLP_EN &= ~0xe0700ff7;
@@ -223,7 +217,7 @@ static void resume_from_deep_sleep(void)
MEC1322_PCR_SYS_SLP_CTL = 0xF8; /* default */
/* Enable UART */
/* Enable LPC */
MEC1322_LPC_ACT |= 1;
MEC1322_LPC_CLK_CTRL &= ~0x2;