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Merge pull request #112 from danh-arm:dh/refactor-plat-header-v4 into for-v0.4

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This commit is contained in:
Dan Handley
2014-05-27 18:34:30 +01:00
parent f53d0fce3f 9865ac1576
commit 22e002da5f
75 changed files with 1360 additions and 1307 deletions
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2
Makefile
View File

@@ -160,9 +160,9 @@ INCLUDES += -Iinclude/bl1 \
-Iinclude/drivers/arm \
-Iinclude/lib \
-Iinclude/lib/aarch64 \
-Iinclude/plat/common \
-Iinclude/stdlib \
-Iinclude/stdlib/sys \
-Iplat/${PLAT} \
${PLAT_INCLUDES} \
${SPD_INCLUDES}

2
bl1/bl1.ld.S
View File

@@ -28,7 +28,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <platform.h>
#include <platform_def.h>
OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)

2
bl1/bl1_main.c
View File

@@ -32,9 +32,9 @@
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <bl1.h>
#include <debug.h>
#include <platform.h>
#include <platform_def.h>
#include <stdio.h>
#include "bl1_private.h"

4
bl1/bl1_private.h
View File

@@ -34,7 +34,7 @@
/******************************************
* Function prototypes
*****************************************/
extern void bl1_arch_setup(void);
extern void bl1_arch_next_el_setup(void);
void bl1_arch_setup(void);
void bl1_arch_next_el_setup(void);
#endif /* __BL1_PRIVATE_H__ */

2
bl2/bl2.ld.S
View File

@@ -28,7 +28,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <platform.h>
#include <platform_def.h>
OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)

2
bl2/bl2_main.c
View File

@@ -32,9 +32,9 @@
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <bl2.h>
#include <debug.h>
#include <platform.h>
#include <platform_def.h>
#include <stdio.h>
#include "bl2_private.h"

2
bl2/bl2_private.h
View File

@@ -34,6 +34,6 @@
/******************************************
* Function prototypes
*****************************************/
extern void bl2_arch_setup(void);
void bl2_arch_setup(void);
#endif /* __BL2_PRIVATE_H__ */

6
bl31/aarch64/runtime_exceptions.S
View File

@@ -32,7 +32,7 @@
#include <asm_macros.S>
#include <context.h>
#include <interrupt_mgmt.h>
#include <platform.h>
#include <platform_def.h>
#include <runtime_svc.h>
.globl runtime_exceptions
@@ -84,7 +84,7 @@
* interrupt controller reports a spurious interrupt then
* return to where we came from.
*/
bl ic_get_pending_interrupt_type
bl plat_ic_get_pending_interrupt_type
cmp x0, #INTR_TYPE_INVAL
b.eq interrupt_exit_\label
@@ -105,7 +105,7 @@
* Read the id of the highest priority pending interrupt. If
* no interrupt is asserted then return to where we came from.
*/
bl ic_get_pending_interrupt_id
bl plat_ic_get_pending_interrupt_id
cmp x0, #INTR_ID_UNAVAILABLE
b.eq interrupt_exit_\label
#endif

2
bl31/bl31.ld.S
View File

@@ -28,7 +28,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <platform.h>
#include <platform_def.h>
OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)

3
bl31/bl31_main.c
View File

@@ -34,6 +34,7 @@
#include <bl_common.h>
#include <bl31.h>
#include <context_mgmt.h>
#include <platform.h>
#include <runtime_svc.h>
#include <stdio.h>
@@ -164,7 +165,7 @@ void bl31_prepare_next_image_entry()
bl31_next_el_arch_setup(image_type);
/* Program EL3 registers to enable entry into the next EL */
next_image_info = bl31_get_next_image_info(image_type);
next_image_info = bl31_plat_get_next_image_ep_info(image_type);
assert(next_image_info);
scr = read_scr();

1
bl31/context_mgmt.c
View File

@@ -37,6 +37,7 @@
#include <context_mgmt.h>
#include <interrupt_mgmt.h>
#include <platform.h>
#include <platform_def.h>
#include <runtime_svc.h>
/*******************************************************************************

2
bl32/tsp/aarch64/tsp_entrypoint.S
View File

@@ -220,7 +220,7 @@ func tsp_cpu_on_entry
* Initialise the MMU
* ---------------------------------------------
*/
bl enable_mmu_el1
bl bl32_plat_enable_mmu
/* ---------------------------------------------
* Give ourselves a stack allocated in Normal

8
bl32/tsp/tsp-fvp.mk
View File

@@ -31,7 +31,7 @@
# TSP source files specific to FVP platform
BL32_SOURCES += drivers/arm/gic/gic_v2.c \
plat/common/aarch64/platform_mp_stack.S \
plat/fvp/aarch64/plat_common.c \
plat/fvp/aarch64/plat_helpers.S \
plat/fvp/bl32_plat_setup.c \
plat/fvp/plat_gic.c
plat/fvp/aarch64/fvp_common.c \
plat/fvp/aarch64/fvp_helpers.S \
plat/fvp/bl32_fvp_setup.c \
plat/fvp/fvp_gic.c

2
bl32/tsp/tsp.ld.S
View File

@@ -28,7 +28,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <platform.h>
#include <platform_def.h>
OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)

7
bl32/tsp/tsp_interrupt.c
View File

@@ -34,6 +34,7 @@
#include <gic_v2.h>
#include <tsp.h>
#include <platform.h>
#include <platform_def.h>
/*******************************************************************************
* This function updates the TSP statistics for FIQs handled synchronously i.e
@@ -81,7 +82,7 @@ int32_t tsp_fiq_handler()
* secure physical generic timer interrupt in which case, handle it.
* Otherwise throw this interrupt at the EL3 firmware.
*/
id = ic_get_pending_interrupt_id();
id = plat_ic_get_pending_interrupt_id();
/* TSP can only handle the secure physical timer interrupt */
if (id != IRQ_SEC_PHY_TIMER)
@@ -91,10 +92,10 @@ int32_t tsp_fiq_handler()
* Handle the interrupt. Also sanity check if it has been preempted by
* another secure interrupt through an assertion.
*/
id = ic_acknowledge_interrupt();
id = plat_ic_acknowledge_interrupt();
assert(id == IRQ_SEC_PHY_TIMER);
tsp_generic_timer_handler();
ic_end_of_interrupt(id);
plat_ic_end_of_interrupt(id);
/* Update the statistics and print some messages */
tsp_stats[linear_id].fiq_count++;

2
bl32/tsp/tsp_main.c
View File

@@ -30,9 +30,9 @@
#include <arch_helpers.h>
#include <bl_common.h>
#include <bl32.h>
#include <debug.h>
#include <platform.h>
#include <platform_def.h>
#include <spinlock.h>
#include <stdio.h>
#include <tsp.h>

1
bl32/tsp/tsp_timer.c
View File

@@ -29,6 +29,7 @@
*/
#include <arch_helpers.h>
#include <assert.h>
#include <platform.h>
#include <tsp.h>
/*******************************************************************************

5
common/bl_common.c
View File

@@ -74,9 +74,10 @@ void change_security_state(unsigned int target_security_state)
/*******************************************************************************
* The next function is a weak definition. Platform specific
* code can override it if it wishes to.
* The next function has a weak definition. Platform specific code can override
* it if it wishes to.
******************************************************************************/
#pragma weak init_bl2_mem_layout
/*******************************************************************************
* Function that takes a memory layout into which BL2 has been either top or

2
drivers/arm/cci400/cci400.c
View File

@@ -30,7 +30,7 @@
#include <cci400.h>
#include <mmio.h>
#include <platform.h>
#include <platform_def.h>
static inline unsigned long get_slave_iface_base(unsigned long mpidr)
{

1
drivers/arm/pl011/pl011.c
View File

@@ -29,7 +29,6 @@
*/
#include <assert.h>
#include <platform.h>
#include <pl011.h>
void pl011_setbaudrate(unsigned long base_addr, unsigned int baudrate)

1
drivers/arm/pl011/pl011_console.c
View File

@@ -30,7 +30,6 @@
#include <assert.h>
#include <console.h>
#include <platform.h>
#include <pl011.h>
static unsigned long uart_base;

2
drivers/io/io_fip.c
View File

@@ -29,6 +29,7 @@
*/
#include <assert.h>
#include <bl_common.h>
#include <debug.h>
#include <errno.h>
#include <firmware_image_package.h>
@@ -36,6 +37,7 @@
#include <io_fip.h>
#include <io_storage.h>
#include <platform.h>
#include <platform_def.h>
#include <stdint.h>
#include <string.h>
#include <uuid.h>

28
include/bl31/bl31.h
View File

@@ -33,30 +33,14 @@
#include <stdint.h>
/*******************************************************************************
* Data declarations
******************************************************************************/
extern unsigned long bl31_entrypoint;
/******************************************
* Forward declarations
*****************************************/
struct meminfo;
struct entry_point_info;
struct bl31_parms;
/*******************************************************************************
* Function prototypes
******************************************************************************/
extern void bl31_arch_setup(void);
extern void bl31_next_el_arch_setup(uint32_t security_state);
extern void bl31_set_next_image_type(uint32_t type);
extern uint32_t bl31_get_next_image_type(void);
extern void bl31_prepare_next_image_entry();
extern struct entry_point_info *bl31_get_next_image_info(uint32_t type);
extern void bl31_early_platform_setup(struct bl31_params *from_bl2,
void *plat_params_from_bl2);
extern void bl31_platform_setup(void);
extern void bl31_register_bl32_init(int32_t (*)(void));
void bl31_arch_setup(void);
void bl31_next_el_arch_setup(uint32_t security_state);
void bl31_set_next_image_type(uint32_t type);
uint32_t bl31_get_next_image_type(void);
void bl31_prepare_next_image_entry();
void bl31_register_bl32_init(int32_t (*)(void));
#endif /* __BL31_H__ */

40
include/bl31/context_mgmt.h
View File

@@ -36,24 +36,24 @@
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
extern void cm_init(void);
extern void *cm_get_context(uint64_t mpidr, uint32_t security_state);
extern void cm_set_context(uint64_t mpidr,
void *context,
uint32_t security_state);
extern void cm_el3_sysregs_context_save(uint32_t security_state);
extern void cm_el3_sysregs_context_restore(uint32_t security_state);
extern void cm_el1_sysregs_context_save(uint32_t security_state);
extern void cm_el1_sysregs_context_restore(uint32_t security_state);
extern void cm_set_el3_eret_context(uint32_t security_state, uint64_t entrypoint,
uint32_t spsr, uint32_t scr);
extern void cm_set_elr_el3(uint32_t security_state, uint64_t entrypoint);
extern void cm_write_scr_el3_bit(uint32_t security_state,
uint32_t bit_pos,
uint32_t value);
extern void cm_set_next_eret_context(uint32_t security_state);
extern void cm_init_pcpu_ptr_cache();
extern void cm_set_pcpu_ptr_cache(const void *pcpu_ptr);
extern void *cm_get_pcpu_ptr_cache(void);
extern uint32_t cm_get_scr_el3(uint32_t security_state);
void cm_init(void);
void *cm_get_context(uint64_t mpidr, uint32_t security_state);
void cm_set_context(uint64_t mpidr,
void *context,
uint32_t security_state);
void cm_el3_sysregs_context_save(uint32_t security_state);
void cm_el3_sysregs_context_restore(uint32_t security_state);
void cm_el1_sysregs_context_save(uint32_t security_state);
void cm_el1_sysregs_context_restore(uint32_t security_state);
void cm_set_el3_eret_context(uint32_t security_state, uint64_t entrypoint,
uint32_t spsr, uint32_t scr);
void cm_set_elr_el3(uint32_t security_state, uint64_t entrypoint);
void cm_write_scr_el3_bit(uint32_t security_state,
uint32_t bit_pos,
uint32_t value);
void cm_set_next_eret_context(uint32_t security_state);
void cm_init_pcpu_ptr_cache();
void cm_set_pcpu_ptr_cache(const void *pcpu_ptr);
void *cm_get_pcpu_ptr_cache(void);
uint32_t cm_get_scr_el3(uint32_t security_state);
#endif /* __CM_H__ */

12
include/bl31/interrupt_mgmt.h
View File

@@ -117,12 +117,12 @@ typedef uint64_t (*interrupt_type_handler_t)(uint32_t id,
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
extern uint32_t get_scr_el3_from_routing_model(uint32_t security_state);
extern int32_t set_routing_model(uint32_t type, uint32_t flags);
extern int32_t register_interrupt_type_handler(uint32_t type,
interrupt_type_handler_t handler,
uint32_t flags);
extern interrupt_type_handler_t get_interrupt_type_handler(uint32_t interrupt_type);
uint32_t get_scr_el3_from_routing_model(uint32_t security_state);
int32_t set_routing_model(uint32_t type, uint32_t flags);
int32_t register_interrupt_type_handler(uint32_t type,
interrupt_type_handler_t handler,
uint32_t flags);
interrupt_type_handler_t get_interrupt_type_handler(uint32_t interrupt_type);
#endif /*__ASSEMBLY__*/
#endif /* __INTERRUPT_MGMT_H__ */

6
include/bl31/runtime_svc.h
View File

@@ -264,10 +264,10 @@ CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc_t, handle), \
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
extern void runtime_svc_init();
void runtime_svc_init();
extern uint64_t __RT_SVC_DESCS_START__;
extern uint64_t __RT_SVC_DESCS_END__;
extern uint64_t get_crash_stack(uint64_t mpidr);
extern void runtime_exceptions(void);
uint64_t get_crash_stack(uint64_t mpidr);
void runtime_exceptions(void);
#endif /*__ASSEMBLY__*/
#endif /* __RUNTIME_SVC_H__ */

54
include/bl31/services/psci.h
View File

@@ -178,36 +178,36 @@ typedef struct spd_pm_ops {
/*******************************************************************************
* Function & Data prototypes
******************************************************************************/
extern unsigned int psci_version(void);
extern int __psci_cpu_suspend(unsigned int, unsigned long, unsigned long);
extern int __psci_cpu_off(void);
extern int psci_affinity_info(unsigned long, unsigned int);
extern int psci_migrate(unsigned int);
extern unsigned int psci_migrate_info_type(void);
extern unsigned long psci_migrate_info_up_cpu(void);
extern void psci_system_off(void);
extern void psci_system_reset(void);
extern int psci_cpu_on(unsigned long,
unsigned long,
unsigned long);
extern void __dead2 psci_power_down_wfi(void);
extern void psci_aff_on_finish_entry(void);
extern void psci_aff_suspend_finish_entry(void);
extern void psci_register_spd_pm_hook(const spd_pm_ops_t *);
extern int psci_get_suspend_stateid(unsigned long mpidr);
extern int psci_get_suspend_afflvl(unsigned long mpidr);
unsigned int psci_version(void);
int __psci_cpu_suspend(unsigned int, unsigned long, unsigned long);
int __psci_cpu_off(void);
int psci_affinity_info(unsigned long, unsigned int);
int psci_migrate(unsigned int);
unsigned int psci_migrate_info_type(void);
unsigned long psci_migrate_info_up_cpu(void);
void psci_system_off(void);
void psci_system_reset(void);
int psci_cpu_on(unsigned long,
unsigned long,
unsigned long);
void __dead2 psci_power_down_wfi(void);
void psci_aff_on_finish_entry(void);
void psci_aff_suspend_finish_entry(void);
void psci_register_spd_pm_hook(const spd_pm_ops_t *);
int psci_get_suspend_stateid(unsigned long mpidr);
int psci_get_suspend_afflvl(unsigned long mpidr);
extern uint64_t psci_smc_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
uint64_t x4,
void *cookie,
void *handle,
uint64_t flags);
uint64_t psci_smc_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
uint64_t x4,
void *cookie,
void *handle,
uint64_t flags);
/* PSCI setup function */
extern int32_t psci_setup(void);
int32_t psci_setup(void);
#endif /*__ASSEMBLY__*/

48
include/bl32/bl32.h
View File

@@ -1,48 +0,0 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __BL32_H__
#define __BL32_H__
#include <stdint.h>
/******************************************
* Forward declarations
*****************************************/
struct meminfo;
/******************************************
* Function prototypes
*****************************************/
extern void bl32_platform_setup(void);
extern struct meminfo *bl32_plat_sec_mem_layout(void);
extern uint64_t bl32_main(void);
#endif /* __BL32_H__ */

66
include/bl32/payloads/tsp.h
View File

@@ -113,7 +113,7 @@
#ifndef __ASSEMBLY__
#include <cassert.h>
#include <platform.h> /* For CACHE_WRITEBACK_GRANULE */
#include <platform_def.h> /* For CACHE_WRITEBACK_GRANULE */
#include <spinlock.h>
#include <stdint.h>
@@ -157,43 +157,43 @@ typedef struct tsp_args {
*/
CASSERT(TSP_ARGS_SIZE == sizeof(tsp_args_t), assert_sp_args_size_mismatch);
extern void tsp_get_magic(uint64_t args[4]);
void tsp_get_magic(uint64_t args[4]);
extern tsp_args_t *tsp_cpu_resume_main(uint64_t arg0,
uint64_t arg1,
uint64_t arg2,
uint64_t arg3,
uint64_t arg4,
uint64_t arg5,
uint64_t arg6,
uint64_t arg7);
extern tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0,
uint64_t arg1,
uint64_t arg2,
uint64_t arg3,
uint64_t arg4,
uint64_t arg5,
uint64_t arg6,
uint64_t arg7);
extern tsp_args_t *tsp_cpu_on_main(void);
extern tsp_args_t *tsp_cpu_off_main(uint64_t arg0,
uint64_t arg1,
uint64_t arg2,
uint64_t arg3,
uint64_t arg4,
uint64_t arg5,
uint64_t arg6,
uint64_t arg7);
tsp_args_t *tsp_cpu_resume_main(uint64_t arg0,
uint64_t arg1,
uint64_t arg2,
uint64_t arg3,
uint64_t arg4,
uint64_t arg5,
uint64_t arg6,
uint64_t arg7);
tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0,
uint64_t arg1,
uint64_t arg2,
uint64_t arg3,
uint64_t arg4,
uint64_t arg5,
uint64_t arg6,
uint64_t arg7);
tsp_args_t *tsp_cpu_on_main(void);
tsp_args_t *tsp_cpu_off_main(uint64_t arg0,
uint64_t arg1,
uint64_t arg2,
uint64_t arg3,
uint64_t arg4,
uint64_t arg5,
uint64_t arg6,
uint64_t arg7);
/* Generic Timer functions */
extern void tsp_generic_timer_start(void);
extern void tsp_generic_timer_handler(void);
extern void tsp_generic_timer_stop(void);
extern void tsp_generic_timer_save(void);
extern void tsp_generic_timer_restore(void);
void tsp_generic_timer_start(void);
void tsp_generic_timer_handler(void);
void tsp_generic_timer_stop(void);
void tsp_generic_timer_save(void);
void tsp_generic_timer_restore(void);
/* FIQ management functions */
extern void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3);
void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3);
/* Data structure to keep track of TSP statistics */
extern spinlock_t console_lock;

26
include/common/bl_common.h
View File

@@ -194,23 +194,15 @@ CASSERT(sizeof(unsigned long) ==
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
extern unsigned long page_align(unsigned long, unsigned);
extern void change_security_state(unsigned int);
extern void init_bl2_mem_layout(meminfo_t *,
meminfo_t *,
unsigned int,
unsigned long) __attribute__((weak));
extern void init_bl31_mem_layout(const meminfo_t *,
meminfo_t *,
unsigned int) __attribute__((weak));
extern unsigned long image_size(const char *);
extern int load_image(meminfo_t *,
const char *,
unsigned int,
unsigned long,
image_info_t *,
entry_point_info_t *);
extern unsigned long *get_el_change_mem_ptr(void);
unsigned long page_align(unsigned long, unsigned);
void change_security_state(unsigned int);
unsigned long image_size(const char *);
int load_image(meminfo_t *,
const char *,
unsigned int,
unsigned long,
image_info_t *,
entry_point_info_t *);
extern const char build_message[];
#endif /*__ASSEMBLY__*/

6
include/common/debug.h
View File

@@ -57,15 +57,15 @@
* spin. This can be expanded in the future to provide more information.
*/
#if DEBUG
extern void __dead2 do_panic(const char *file, int line);
void __dead2 do_panic(const char *file, int line);
#define panic() do_panic(__FILE__, __LINE__)
#else
extern void __dead2 do_panic(void);
void __dead2 do_panic(void);
#define panic() do_panic()
#endif
extern void print_string_value(char *s, unsigned long *mem);
void print_string_value(char *s, unsigned long *mem);
#endif /* __DEBUG_H__ */

4
include/drivers/arm/cci400.h
View File

@@ -66,7 +66,7 @@
#define CHANGE_PENDING_BIT (1 << 0)
/* Function declarations */
extern void cci_enable_coherency(unsigned long mpidr);
extern void cci_disable_coherency(unsigned long mpidr);
void cci_enable_coherency(unsigned long mpidr);
void cci_disable_coherency(unsigned long mpidr);
#endif /* __CCI_400_H__ */

70
include/drivers/arm/gic_v2.h
View File

@@ -143,41 +143,41 @@
* GIC Distributor function prototypes
******************************************************************************/
extern unsigned int gicd_read_igroupr(unsigned int, unsigned int);
extern unsigned int gicd_read_isenabler(unsigned int, unsigned int);
extern unsigned int gicd_read_icenabler(unsigned int, unsigned int);
extern unsigned int gicd_read_ispendr(unsigned int, unsigned int);
extern unsigned int gicd_read_icpendr(unsigned int, unsigned int);
extern unsigned int gicd_read_isactiver(unsigned int, unsigned int);
extern unsigned int gicd_read_icactiver(unsigned int, unsigned int);
extern unsigned int gicd_read_ipriorityr(unsigned int, unsigned int);
extern unsigned int gicd_read_itargetsr(unsigned int, unsigned int);
extern unsigned int gicd_read_icfgr(unsigned int, unsigned int);
extern unsigned int gicd_read_cpendsgir(unsigned int, unsigned int);
extern unsigned int gicd_read_spendsgir(unsigned int, unsigned int);
extern void gicd_write_igroupr(unsigned int, unsigned int, unsigned int);
extern void gicd_write_isenabler(unsigned int, unsigned int, unsigned int);
extern void gicd_write_icenabler(unsigned int, unsigned int, unsigned int);
extern void gicd_write_ispendr(unsigned int, unsigned int, unsigned int);
extern void gicd_write_icpendr(unsigned int, unsigned int, unsigned int);
extern void gicd_write_isactiver(unsigned int, unsigned int, unsigned int);
extern void gicd_write_icactiver(unsigned int, unsigned int, unsigned int);
extern void gicd_write_ipriorityr(unsigned int, unsigned int, unsigned int);
extern void gicd_write_itargetsr(unsigned int, unsigned int, unsigned int);
extern void gicd_write_icfgr(unsigned int, unsigned int, unsigned int);
extern void gicd_write_cpendsgir(unsigned int, unsigned int, unsigned int);
extern void gicd_write_spendsgir(unsigned int, unsigned int, unsigned int);
extern unsigned int gicd_get_igroupr(unsigned int, unsigned int);
extern void gicd_set_igroupr(unsigned int, unsigned int);
extern void gicd_clr_igroupr(unsigned int, unsigned int);
extern void gicd_set_isenabler(unsigned int, unsigned int);
extern void gicd_set_icenabler(unsigned int, unsigned int);
extern void gicd_set_ispendr(unsigned int, unsigned int);
extern void gicd_set_icpendr(unsigned int, unsigned int);
extern void gicd_set_isactiver(unsigned int, unsigned int);
extern void gicd_set_icactiver(unsigned int, unsigned int);
extern void gicd_set_ipriorityr(unsigned int, unsigned int, unsigned int);
extern void gicd_set_itargetsr(unsigned int, unsigned int, unsigned int);
unsigned int gicd_read_igroupr(unsigned int, unsigned int);
unsigned int gicd_read_isenabler(unsigned int, unsigned int);
unsigned int gicd_read_icenabler(unsigned int, unsigned int);
unsigned int gicd_read_ispendr(unsigned int, unsigned int);
unsigned int gicd_read_icpendr(unsigned int, unsigned int);
unsigned int gicd_read_isactiver(unsigned int, unsigned int);
unsigned int gicd_read_icactiver(unsigned int, unsigned int);
unsigned int gicd_read_ipriorityr(unsigned int, unsigned int);
unsigned int gicd_read_itargetsr(unsigned int, unsigned int);
unsigned int gicd_read_icfgr(unsigned int, unsigned int);
unsigned int gicd_read_cpendsgir(unsigned int, unsigned int);
unsigned int gicd_read_spendsgir(unsigned int, unsigned int);
void gicd_write_igroupr(unsigned int, unsigned int, unsigned int);
void gicd_write_isenabler(unsigned int, unsigned int, unsigned int);
void gicd_write_icenabler(unsigned int, unsigned int, unsigned int);
void gicd_write_ispendr(unsigned int, unsigned int, unsigned int);
void gicd_write_icpendr(unsigned int, unsigned int, unsigned int);
void gicd_write_isactiver(unsigned int, unsigned int, unsigned int);
void gicd_write_icactiver(unsigned int, unsigned int, unsigned int);
void gicd_write_ipriorityr(unsigned int, unsigned int, unsigned int);
void gicd_write_itargetsr(unsigned int, unsigned int, unsigned int);
void gicd_write_icfgr(unsigned int, unsigned int, unsigned int);
void gicd_write_cpendsgir(unsigned int, unsigned int, unsigned int);
void gicd_write_spendsgir(unsigned int, unsigned int, unsigned int);
unsigned int gicd_get_igroupr(unsigned int, unsigned int);
void gicd_set_igroupr(unsigned int, unsigned int);
void gicd_clr_igroupr(unsigned int, unsigned int);
void gicd_set_isenabler(unsigned int, unsigned int);
void gicd_set_icenabler(unsigned int, unsigned int);
void gicd_set_ispendr(unsigned int, unsigned int);
void gicd_set_icpendr(unsigned int, unsigned int);
void gicd_set_isactiver(unsigned int, unsigned int);
void gicd_set_icactiver(unsigned int, unsigned int);
void gicd_set_ipriorityr(unsigned int, unsigned int, unsigned int);
void gicd_set_itargetsr(unsigned int, unsigned int, unsigned int);
/*******************************************************************************

14
include/drivers/arm/gic_v3.h
View File

@@ -68,13 +68,13 @@
******************************************************************************/
uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr);
extern unsigned int read_icc_sre_el1(void);
extern unsigned int read_icc_sre_el2(void);
extern unsigned int read_icc_sre_el3(void);
extern void write_icc_sre_el1(unsigned int);
extern void write_icc_sre_el2(unsigned int);
extern void write_icc_sre_el3(unsigned int);
extern void write_icc_pmr_el1(unsigned int);
unsigned int read_icc_sre_el1(void);
unsigned int read_icc_sre_el2(void);
unsigned int read_icc_sre_el3(void);
void write_icc_sre_el1(unsigned int);
void write_icc_sre_el2(unsigned int);
void write_icc_sre_el3(unsigned int);
void write_icc_pmr_el1(unsigned int);
/*******************************************************************************
* GIC Redistributor interface accessors

2
include/drivers/io_driver.h
View File

@@ -32,7 +32,7 @@
#define __IO_DRIVER_H__
#include <io_storage.h>
#include <platform.h> /* For MAX_IO_DEVICES */
#include <platform_def.h> /* For MAX_IO_DEVICES */
#include <stdint.h>

15
include/lib/aarch64/arch.h
View File

@@ -394,4 +394,19 @@
#define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK
/*******************************************************************************
* Definitions of register offsets and fields in the CNTCTLBase Frame of the
* system level implementation of the Generic Timer.
******************************************************************************/
#define CNTNSAR 0x4
#define CNTNSAR_NS_SHIFT(x) x
#define CNTACR_BASE(x) (0x40 + (x << 2))
#define CNTACR_RPCT_SHIFT 0x0
#define CNTACR_RVCT_SHIFT 0x1
#define CNTACR_RFRQ_SHIFT 0x2
#define CNTACR_RVOFF_SHIFT 0x3
#define CNTACR_RWVT_SHIFT 0x4
#define CNTACR_RWPT_SHIFT 0x5
#endif /* __ARCH_H__ */

358
include/lib/aarch64/arch_helpers.h
View File

@@ -37,243 +37,243 @@
/*******************************************************************************
* Aarch64 translation tables manipulation helper prototypes
******************************************************************************/
extern unsigned long create_table_desc(unsigned long *next_table_ptr);
extern unsigned long create_block_desc(unsigned long desc,
unsigned long addr,
unsigned int level);
extern unsigned long create_device_block(unsigned long output_addr,
unsigned int level,
unsigned int ns);
extern unsigned long create_romem_block(unsigned long output_addr,
unsigned int level,
unsigned int ns);
extern unsigned long create_rwmem_block(unsigned long output_addr,
unsigned int level,
unsigned int ns);
unsigned long create_table_desc(unsigned long *next_table_ptr);
unsigned long create_block_desc(unsigned long desc,
unsigned long addr,
unsigned int level);
unsigned long create_device_block(unsigned long output_addr,
unsigned int level,
unsigned int ns);
unsigned long create_romem_block(unsigned long output_addr,
unsigned int level,
unsigned int ns);
unsigned long create_rwmem_block(unsigned long output_addr,
unsigned int level,
unsigned int ns);
/*******************************************************************************
* TLB maintenance accessor prototypes
******************************************************************************/
extern void tlbialle1(void);
extern void tlbialle1is(void);
extern void tlbialle2(void);
extern void tlbialle2is(void);
extern void tlbialle3(void);
extern void tlbialle3is(void);
extern void tlbivmalle1(void);
void tlbialle1(void);
void tlbialle1is(void);
void tlbialle2(void);
void tlbialle2is(void);
void tlbialle3(void);
void tlbialle3is(void);
void tlbivmalle1(void);
/*******************************************************************************
* Cache maintenance accessor prototypes
******************************************************************************/
extern void dcisw(unsigned long);
extern void dccisw(unsigned long);
extern void dccsw(unsigned long);
extern void dccvac(unsigned long);
extern void dcivac(unsigned long);
extern void dccivac(unsigned long);
extern void dccvau(unsigned long);
extern void dczva(unsigned long);
extern void flush_dcache_range(unsigned long, unsigned long);
extern void inv_dcache_range(unsigned long, unsigned long);
extern void dcsw_op_louis(unsigned int);
extern void dcsw_op_all(unsigned int);
void dcisw(unsigned long);
void dccisw(unsigned long);
void dccsw(unsigned long);
void dccvac(unsigned long);
void dcivac(unsigned long);
void dccivac(unsigned long);
void dccvau(unsigned long);
void dczva(unsigned long);
void flush_dcache_range(unsigned long, unsigned long);
void inv_dcache_range(unsigned long, unsigned long);
void dcsw_op_louis(unsigned int);
void dcsw_op_all(unsigned int);
extern void disable_mmu_el3(void);
extern void disable_mmu_icache_el3(void);
void disable_mmu_el3(void);
void disable_mmu_icache_el3(void);
/*******************************************************************************
* Misc. accessor prototypes
******************************************************************************/
extern void enable_irq(void);
extern void enable_fiq(void);
extern void enable_serror(void);
extern void enable_debug_exceptions(void);
void enable_irq(void);
void enable_fiq(void);
void enable_serror(void);
void enable_debug_exceptions(void);
extern void disable_irq(void);
extern void disable_fiq(void);
extern void disable_serror(void);
extern void disable_debug_exceptions(void);
void disable_irq(void);
void disable_fiq(void);
void disable_serror(void);
void disable_debug_exceptions(void);
extern unsigned long read_id_pfr1_el1(void);
extern unsigned long read_id_aa64pfr0_el1(void);
extern unsigned long read_current_el(void);
extern unsigned long read_daif(void);
extern unsigned long read_spsr_el1(void);
extern unsigned long read_spsr_el2(void);
extern unsigned long read_spsr_el3(void);
extern unsigned long read_elr_el1(void);
extern unsigned long read_elr_el2(void);
extern unsigned long read_elr_el3(void);
unsigned long read_id_pfr1_el1(void);
unsigned long read_id_aa64pfr0_el1(void);
unsigned long read_current_el(void);
unsigned long read_daif(void);
unsigned long read_spsr_el1(void);
unsigned long read_spsr_el2(void);
unsigned long read_spsr_el3(void);
unsigned long read_elr_el1(void);
unsigned long read_elr_el2(void);
unsigned long read_elr_el3(void);
extern void write_daif(unsigned long);
extern void write_spsr_el1(unsigned long);
extern void write_spsr_el2(unsigned long);
extern void write_spsr_el3(unsigned long);
extern void write_elr_el1(unsigned long);
extern void write_elr_el2(unsigned long);
extern void write_elr_el3(unsigned long);
void write_daif(unsigned long);
void write_spsr_el1(unsigned long);
void write_spsr_el2(unsigned long);
void write_spsr_el3(unsigned long);
void write_elr_el1(unsigned long);
void write_elr_el2(unsigned long);
void write_elr_el3(unsigned long);
extern void wfi(void);
extern void wfe(void);
extern void rfe(void);
extern void sev(void);
extern void dsb(void);
extern void isb(void);
void wfi(void);
void wfe(void);
void rfe(void);
void sev(void);
void dsb(void);
void isb(void);
extern unsigned int get_afflvl_shift(unsigned int);
extern unsigned int mpidr_mask_lower_afflvls(unsigned long, unsigned int);
unsigned int get_afflvl_shift(unsigned int);
unsigned int mpidr_mask_lower_afflvls(unsigned long, unsigned int);
extern void __dead2 eret(unsigned long, unsigned long,
unsigned long, unsigned long,
unsigned long, unsigned long,
unsigned long, unsigned long);
void __dead2 eret(unsigned long, unsigned long,
unsigned long, unsigned long,
unsigned long, unsigned long,
unsigned long, unsigned long);
extern void __dead2 smc(unsigned long, unsigned long,
unsigned long, unsigned long,
unsigned long, unsigned long,
unsigned long, unsigned long);
void __dead2 smc(unsigned long, unsigned long,
unsigned long, unsigned long,
unsigned long, unsigned long,
unsigned long, unsigned long);
/*******************************************************************************
* System register accessor prototypes
******************************************************************************/
extern unsigned long read_midr(void);
extern unsigned long read_mpidr(void);
unsigned long read_midr(void);
unsigned long read_mpidr(void);
extern unsigned long read_scr(void);
extern unsigned long read_hcr(void);
unsigned long read_scr(void);
unsigned long read_hcr(void);
extern unsigned long read_vbar_el1(void);
extern unsigned long read_vbar_el2(void);
extern unsigned long read_vbar_el3(void);
unsigned long read_vbar_el1(void);
unsigned long read_vbar_el2(void);
unsigned long read_vbar_el3(void);
extern unsigned long read_sctlr_el1(void);
extern unsigned long read_sctlr_el2(void);
extern unsigned long read_sctlr_el3(void);
unsigned long read_sctlr_el1(void);
unsigned long read_sctlr_el2(void);
unsigned long read_sctlr_el3(void);
extern unsigned long read_actlr_el1(void);
extern unsigned long read_actlr_el2(void);
extern unsigned long read_actlr_el3(void);
unsigned long read_actlr_el1(void);
unsigned long read_actlr_el2(void);
unsigned long read_actlr_el3(void);
extern unsigned long read_esr_el1(void);
extern unsigned long read_esr_el2(void);
extern unsigned long read_esr_el3(void);
unsigned long read_esr_el1(void);
unsigned long read_esr_el2(void);
unsigned long read_esr_el3(void);
extern unsigned long read_afsr0_el1(void);
extern unsigned long read_afsr0_el2(void);
extern unsigned long read_afsr0_el3(void);
unsigned long read_afsr0_el1(void);
unsigned long read_afsr0_el2(void);
unsigned long read_afsr0_el3(void);
extern unsigned long read_afsr1_el1(void);
extern unsigned long read_afsr1_el2(void);
extern unsigned long read_afsr1_el3(void);
unsigned long read_afsr1_el1(void);
unsigned long read_afsr1_el2(void);
unsigned long read_afsr1_el3(void);
extern unsigned long read_far_el1(void);
extern unsigned long read_far_el2(void);
extern unsigned long read_far_el3(void);
unsigned long read_far_el1(void);
unsigned long read_far_el2(void);
unsigned long read_far_el3(void);
extern unsigned long read_mair_el1(void);
extern unsigned long read_mair_el2(void);
extern unsigned long read_mair_el3(void);
unsigned long read_mair_el1(void);
unsigned long read_mair_el2(void);
unsigned long read_mair_el3(void);
extern unsigned long read_amair_el1(void);
extern unsigned long read_amair_el2(void);
extern unsigned long read_amair_el3(void);
unsigned long read_amair_el1(void);
unsigned long read_amair_el2(void);
unsigned long read_amair_el3(void);
extern unsigned long read_rvbar_el1(void);
extern unsigned long read_rvbar_el2(void);
extern unsigned long read_rvbar_el3(void);
unsigned long read_rvbar_el1(void);
unsigned long read_rvbar_el2(void);
unsigned long read_rvbar_el3(void);
extern unsigned long read_rmr_el1(void);
extern unsigned long read_rmr_el2(void);
extern unsigned long read_rmr_el3(void);
unsigned long read_rmr_el1(void);
unsigned long read_rmr_el2(void);
unsigned long read_rmr_el3(void);
extern unsigned long read_tcr_el1(void);
extern unsigned long read_tcr_el2(void);
extern unsigned long read_tcr_el3(void);
unsigned long read_tcr_el1(void);
unsigned long read_tcr_el2(void);
unsigned long read_tcr_el3(void);
extern unsigned long read_ttbr0_el1(void);
extern unsigned long read_ttbr0_el2(void);
extern unsigned long read_ttbr0_el3(void);
unsigned long read_ttbr0_el1(void);
unsigned long read_ttbr0_el2(void);
unsigned long read_ttbr0_el3(void);
extern unsigned long read_ttbr1_el1(void);
unsigned long read_ttbr1_el1(void);
extern unsigned long read_cptr_el2(void);
extern unsigned long read_cptr_el3(void);
unsigned long read_cptr_el2(void);
unsigned long read_cptr_el3(void);
extern unsigned long read_cpacr(void);
extern unsigned long read_cpuectlr(void);
extern unsigned int read_cntfrq_el0(void);
extern unsigned int read_cntps_ctl_el1(void);
extern unsigned int read_cntps_tval_el1(void);
extern unsigned long read_cntps_cval_el1(void);
extern unsigned long read_cntpct_el0(void);
extern unsigned long read_cnthctl_el2(void);
unsigned long read_cpacr(void);
unsigned long read_cpuectlr(void);
unsigned int read_cntfrq_el0(void);
unsigned int read_cntps_ctl_el1(void);
unsigned int read_cntps_tval_el1(void);
unsigned long read_cntps_cval_el1(void);
unsigned long read_cntpct_el0(void);
unsigned long read_cnthctl_el2(void);
extern unsigned long read_tpidr_el3(void);
unsigned long read_tpidr_el3(void);
extern void write_scr(unsigned long);
extern void write_hcr(unsigned long);
extern void write_cpacr(unsigned long);
extern void write_cntfrq_el0(unsigned int);
extern void write_cntps_ctl_el1(unsigned int);
extern void write_cntps_tval_el1(unsigned int);
extern void write_cntps_cval_el1(unsigned long);
extern void write_cnthctl_el2(unsigned long);
void write_scr(unsigned long);
void write_hcr(unsigned long);
void write_cpacr(unsigned long);
void write_cntfrq_el0(unsigned int);
void write_cntps_ctl_el1(unsigned int);
void write_cntps_tval_el1(unsigned int);
void write_cntps_cval_el1(unsigned long);
void write_cnthctl_el2(unsigned long);
extern void write_vbar_el1(unsigned long);
extern void write_vbar_el2(unsigned long);
extern void write_vbar_el3(unsigned long);
void write_vbar_el1(unsigned long);
void write_vbar_el2(unsigned long);
void write_vbar_el3(unsigned long);
extern void write_sctlr_el1(unsigned long);
extern void write_sctlr_el2(unsigned long);
extern void write_sctlr_el3(unsigned long);
void write_sctlr_el1(unsigned long);
void write_sctlr_el2(unsigned long);
void write_sctlr_el3(unsigned long);
extern void write_actlr_el1(unsigned long);
extern void write_actlr_el2(unsigned long);
extern void write_actlr_el3(unsigned long);
void write_actlr_el1(unsigned long);
void write_actlr_el2(unsigned long);
void write_actlr_el3(unsigned long);
extern void write_esr_el1(unsigned long);
extern void write_esr_el2(unsigned long);
extern void write_esr_el3(unsigned long);
void write_esr_el1(unsigned long);
void write_esr_el2(unsigned long);
void write_esr_el3(unsigned long);
extern void write_afsr0_el1(unsigned long);
extern void write_afsr0_el2(unsigned long);
extern void write_afsr0_el3(unsigned long);
void write_afsr0_el1(unsigned long);
void write_afsr0_el2(unsigned long);
void write_afsr0_el3(unsigned long);
extern void write_afsr1_el1(unsigned long);
extern void write_afsr1_el2(unsigned long);
extern void write_afsr1_el3(unsigned long);
void write_afsr1_el1(unsigned long);
void write_afsr1_el2(unsigned long);
void write_afsr1_el3(unsigned long);
extern void write_far_el1(unsigned long);
extern void write_far_el2(unsigned long);
extern void write_far_el3(unsigned long);
void write_far_el1(unsigned long);
void write_far_el2(unsigned long);
void write_far_el3(unsigned long);
extern void write_mair_el1(unsigned long);
extern void write_mair_el2(unsigned long);
extern void write_mair_el3(unsigned long);
void write_mair_el1(unsigned long);
void write_mair_el2(unsigned long);
void write_mair_el3(unsigned long);
extern void write_amair_el1(unsigned long);
extern void write_amair_el2(unsigned long);
extern void write_amair_el3(unsigned long);
void write_amair_el1(unsigned long);
void write_amair_el2(unsigned long);
void write_amair_el3(unsigned long);
extern void write_rmr_el1(unsigned long);
extern void write_rmr_el2(unsigned long);
extern void write_rmr_el3(unsigned long);
void write_rmr_el1(unsigned long);
void write_rmr_el2(unsigned long);
void write_rmr_el3(unsigned long);
extern void write_tcr_el1(unsigned long);
extern void write_tcr_el2(unsigned long);
extern void write_tcr_el3(unsigned long);
void write_tcr_el1(unsigned long);
void write_tcr_el2(unsigned long);
void write_tcr_el3(unsigned long);
extern void write_ttbr0_el1(unsigned long);
extern void write_ttbr0_el2(unsigned long);
extern void write_ttbr0_el3(unsigned long);
void write_ttbr0_el1(unsigned long);
void write_ttbr0_el2(unsigned long);
void write_ttbr0_el3(unsigned long);
extern void write_ttbr1_el1(unsigned long);
void write_ttbr1_el1(unsigned long);
extern void write_cpuectlr(unsigned long);
extern void write_cptr_el2(unsigned long);
extern void write_cptr_el3(unsigned long);
void write_cpuectlr(unsigned long);
void write_cptr_el2(unsigned long);
void write_cptr_el3(unsigned long);
extern void write_tpidr_el3(unsigned long);
void write_tpidr_el3(unsigned long);
#define IS_IN_EL(x) \
(GET_EL(read_current_el()) == MODE_EL##x)

11
include/lib/aarch64/xlat_tables.h
View File

@@ -60,12 +60,13 @@ typedef struct mmap_region {
mmap_attr_t attr;
} mmap_region_t;
extern void mmap_add_region(unsigned long base, unsigned long size,
unsigned attr);
extern void mmap_add(const mmap_region_t *mm);
void mmap_add_region(unsigned long base, unsigned long size,
unsigned attr);
void mmap_add(const mmap_region_t *mm);
extern void init_xlat_tables(void);
void init_xlat_tables(void);
extern uint64_t l1_xlation_table[];
void enable_mmu_el1(void);
void enable_mmu_el3(void);
#endif /* __XLAT_TABLES_H__ */

2
include/lib/bakery_lock.h
View File

@@ -31,7 +31,7 @@
#ifndef __BAKERY_LOCK_H__
#define __BAKERY_LOCK_H__
#include <platform.h>
#include <platform_def.h>
#define BAKERY_LOCK_MAX_CPUS PLATFORM_CORE_COUNT

12
include/lib/mmio.h
View File

@@ -33,13 +33,13 @@
#include <stdint.h>
extern void mmio_write_8(uintptr_t addr, uint8_t value);
extern uint8_t mmio_read_8(uintptr_t addr);
void mmio_write_8(uintptr_t addr, uint8_t value);
uint8_t mmio_read_8(uintptr_t addr);
extern void mmio_write_32(uintptr_t addr, uint32_t value);
extern uint32_t mmio_read_32(uintptr_t addr);
void mmio_write_32(uintptr_t addr, uint32_t value);
uint32_t mmio_read_32(uintptr_t addr);
extern void mmio_write_64(uintptr_t addr, uint64_t value);
extern uint64_t mmio_read_64(uintptr_t addr);
void mmio_write_64(uintptr_t addr, uint64_t value);
uint64_t mmio_read_64(uintptr_t addr);
#endif /* __MMIO_H__ */

180
include/plat/common/platform.h Normal file
View File

@@ -0,0 +1,180 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLATFORM_H__
#define __PLATFORM_H__
#include <stdint.h>
/*******************************************************************************
* Forward declarations
******************************************************************************/
struct plat_pm_ops;
struct meminfo;
struct image_info;
struct entry_point_info;
struct bl31_params;
/*******************************************************************************
* Function declarations
******************************************************************************/
/*******************************************************************************
* Mandatory common functions
******************************************************************************/
uint64_t plat_get_syscnt_freq(void);
int plat_get_image_source(const char *image_name,
uintptr_t *dev_handle,
uintptr_t *image_spec);
unsigned long plat_get_ns_image_entrypoint(void);
/*******************************************************************************
* Mandatory interrupt management functions
******************************************************************************/
uint32_t plat_ic_get_pending_interrupt_id(void);
uint32_t plat_ic_get_pending_interrupt_type(void);
uint32_t plat_ic_acknowledge_interrupt(void);
uint32_t plat_ic_get_interrupt_type(uint32_t id);
void plat_ic_end_of_interrupt(uint32_t id);
uint32_t plat_interrupt_type_to_line(uint32_t type,
uint32_t security_state);
/*******************************************************************************
* Optional common functions (may be overridden)
******************************************************************************/
unsigned int platform_get_core_pos(unsigned long mpidr);
unsigned long platform_get_stack(unsigned long mpidr);
void plat_report_exception(unsigned long);
/*******************************************************************************
* Mandatory BL1 functions
******************************************************************************/
void bl1_plat_arch_setup(void);
void bl1_platform_setup(void);
struct meminfo *bl1_plat_sec_mem_layout(void);
/*
* This function allows the platform to change the entrypoint information for
* BL2, after BL1 has loaded BL2 into memory but before BL2 is executed.
*/
void bl1_plat_set_bl2_ep_info(struct image_info *image,
struct entry_point_info *ep);
/*******************************************************************************
* Optional BL1 functions (may be overridden)
******************************************************************************/
void init_bl2_mem_layout(struct meminfo *,
struct meminfo *,
unsigned int,
unsigned long);
/*******************************************************************************
* Mandatory BL2 functions
******************************************************************************/
void bl2_plat_arch_setup(void);
void bl2_platform_setup(void);
struct meminfo *bl2_plat_sec_mem_layout(void);
/*
* This function returns a pointer to the shared memory that the platform has
* kept aside to pass trusted firmware related information that BL3-1
* could need
*/
struct bl31_params *bl2_plat_get_bl31_params(void);
/*
* This function returns a pointer to the shared memory that the platform
* has kept to point to entry point information of BL31 to BL2
*/
struct entry_point_info *bl2_plat_get_bl31_ep_info(void);
/*
* This function flushes to main memory all the params that are
* passed to BL3-1
*/
void bl2_plat_flush_bl31_params(void);
/*
* The next 3 functions allow the platform to change the entrypoint
* information for the 3rd level BL images, after BL2 has loaded the 3rd
* level BL images into memory but before BL3-1 is executed.
*/
void bl2_plat_set_bl31_ep_info(struct image_info *image,
struct entry_point_info *ep);
void bl2_plat_set_bl32_ep_info(struct image_info *image,
struct entry_point_info *ep);
void bl2_plat_set_bl33_ep_info(struct image_info *image,
struct entry_point_info *ep);
/* Gets the memory layout for BL32 */
void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info);
/* Gets the memory layout for BL33 */
void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info);
/*******************************************************************************
* Optional BL2 functions (may be overridden)
******************************************************************************/
/*******************************************************************************
* Mandatory BL3-1 functions
******************************************************************************/
void bl31_early_platform_setup(struct bl31_params *from_bl2,
void *plat_params_from_bl2);
void bl31_plat_arch_setup(void);
void bl31_platform_setup(void);
struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type);
/*******************************************************************************
* Mandatory PSCI functions (BL3-1)
******************************************************************************/
int platform_setup_pm(const struct plat_pm_ops **);
int plat_get_max_afflvl(void);
unsigned int plat_get_aff_count(unsigned int, unsigned long);
unsigned int plat_get_aff_state(unsigned int, unsigned long);
/*******************************************************************************
* Optional BL3-1 functions (may be overridden)
******************************************************************************/
void bl31_plat_enable_mmu();
/*******************************************************************************
* Mandatory BL3-2 functions (only if platform contains a BL3-2)
******************************************************************************/
void bl32_platform_setup(void);
/*******************************************************************************
* Optional BL3-2 functions (may be overridden)
******************************************************************************/
void bl32_plat_enable_mmu();
#endif /* __PLATFORM_H__ */

65
lib/aarch64/xlat_tables.c
View File

@@ -28,8 +28,10 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <arch_helpers.h>
#include <assert.h>
#include <platform.h>
#include <platform_def.h>
#include <string.h>
#include <xlat_tables.h>
@@ -49,7 +51,7 @@
#define NUM_L1_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
uint64_t l1_xlation_table[NUM_L1_ENTRIES]
static uint64_t l1_xlation_table[NUM_L1_ENTRIES]
__aligned(NUM_L1_ENTRIES * sizeof(uint64_t));
static uint64_t xlat_tables[MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES]
@@ -226,3 +228,62 @@ void init_xlat_tables(void)
print_mmap();
init_xlation_table(mmap, 0, l1_xlation_table, 1);
}
/*******************************************************************************
* Macro generating the code for the function enabling the MMU in the given
* exception level, assuming that the pagetables have already been created.
*
* _el: Exception level at which the function will run
* _tcr_extra: Extra bits to set in the TCR register. This mask will
* be OR'ed with the default TCR value.
* _tlbi_fct: Function to invalidate the TLBs at the current
* exception level
******************************************************************************/
#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \
void enable_mmu_el##_el(void) \
{ \
uint64_t mair, tcr, ttbr; \
uint32_t sctlr; \
\
assert(IS_IN_EL(_el)); \
assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \
\
/* Set attributes in the right indices of the MAIR */ \
mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \
mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \
ATTR_IWBWA_OWBWA_NTR_INDEX); \
write_mair_el##_el(mair); \
\
/* Invalidate TLBs at the current exception level */ \
_tlbi_fct(); \
\
/* Set TCR bits as well. */ \
/* Inner & outer WBWA & shareable + T0SZ = 32 */ \
tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \
TCR_RGN_INNER_WBA | TCR_T0SZ_4GB; \
tcr |= _tcr_extra; \
write_tcr_el##_el(tcr); \
\
/* Set TTBR bits as well */ \
ttbr = (uint64_t) l1_xlation_table; \
write_ttbr0_el##_el(ttbr); \
\
/* Ensure all translation table writes have drained */ \
/* into memory, the TLB invalidation is complete, */ \
/* and translation register writes are committed */ \
/* before enabling the MMU */ \
dsb(); \
isb(); \
\
sctlr = read_sctlr_el##_el(); \
sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT | SCTLR_I_BIT; \
sctlr |= SCTLR_A_BIT | SCTLR_C_BIT; \
write_sctlr_el##_el(sctlr); \
\
/* Ensure the MMU enable takes effect immediately */ \
isb(); \
}
/* Define EL1 and EL3 variants of the function enabling the MMU */
DEFINE_ENABLE_MMU_EL(1, 0, tlbivmalle1)
DEFINE_ENABLE_MMU_EL(3, TCR_EL3_RES1, tlbialle3)

1
lib/locks/bakery/bakery_lock.c
View File

@@ -31,6 +31,7 @@
#include <arch_helpers.h>
#include <assert.h>
#include <bakery_lock.h>
#include <platform.h>
#include <string.h>
/*

4
lib/semihosting/semihosting.c
View File

@@ -37,8 +37,8 @@
#define SEMIHOSTING_SUPPORTED 1
#endif
extern long semihosting_call(unsigned long operation,
void *system_block_address);
long semihosting_call(unsigned long operation,
void *system_block_address);
typedef struct {
const char *file_name;

31
include/bl1/bl1.h → plat/common/aarch64/plat_common.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,19 +28,22 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __BL1_H__
#define __BL1_H__
#include <xlat_tables.h>
/*
* The following 2 platform setup functions are weakly defined. They
* provide typical implementations that may be re-used by multiple
* platforms but may also be overridden by a platform if required.
*/
#pragma weak bl31_plat_enable_mmu
#pragma weak bl32_plat_enable_mmu
/******************************************
* Forward declarations
*****************************************/
struct meminfo;
void bl31_plat_enable_mmu()
{
enable_mmu_el3();
}
/******************************************
* Function prototypes
*****************************************/
extern void bl1_platform_setup(void);
extern struct meminfo *bl1_plat_sec_mem_layout(void);
#endif /* __BL1_H__ */
void bl32_plat_enable_mmu()
{
enable_mmu_el1();
}

2
plat/common/aarch64/platform_helpers.S
View File

@@ -30,7 +30,7 @@
#include <arch.h>
#include <asm_macros.S>
#include <platform.h>
#include <platform_def.h>
.weak platform_get_core_pos

2
plat/common/aarch64/platform_mp_stack.S
View File

@@ -30,7 +30,7 @@
#include <arch.h>
#include <asm_macros.S>
#include <platform.h>
#include <platform_def.h>
.local pcpu_dv_mem_stack

2
plat/common/aarch64/platform_up_stack.S
View File

@@ -30,7 +30,7 @@
#include <arch.h>
#include <asm_macros.S>
#include <platform.h>
#include <platform_def.h>
.local pcpu_dv_mem_stack

114
plat/fvp/aarch64/plat_common.c → plat/fvp/aarch64/fvp_common.c
View File

@@ -37,6 +37,7 @@
#include <mmio.h>
#include <platform.h>
#include <xlat_tables.h>
#include "../fvp_def.h"
/*******************************************************************************
* This array holds the characteristics of the differences between the three
@@ -45,66 +46,7 @@
* configuration) & used thereafter. Each BL will have its own copy to allow
* independent operation.
******************************************************************************/
static unsigned long platform_config[CONFIG_LIMIT];
/*******************************************************************************
* Macro generating the code for the function enabling the MMU in the given
* exception level, assuming that the pagetables have already been created.
*
* _el: Exception level at which the function will run
* _tcr_extra: Extra bits to set in the TCR register. This mask will
* be OR'ed with the default TCR value.
* _tlbi_fct: Function to invalidate the TLBs at the current
* exception level
******************************************************************************/
#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \
void enable_mmu_el##_el(void) \
{ \
uint64_t mair, tcr, ttbr; \
uint32_t sctlr; \
\
assert(IS_IN_EL(_el)); \
assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \
\
/* Set attributes in the right indices of the MAIR */ \
mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \
mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \
ATTR_IWBWA_OWBWA_NTR_INDEX); \
write_mair_el##_el(mair); \
\
/* Invalidate TLBs at the current exception level */ \
_tlbi_fct(); \
\
/* Set TCR bits as well. */ \
/* Inner & outer WBWA & shareable + T0SZ = 32 */ \
tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \
TCR_RGN_INNER_WBA | TCR_T0SZ_4GB; \
tcr |= _tcr_extra; \
write_tcr_el##_el(tcr); \
\
/* Set TTBR bits as well */ \
ttbr = (uint64_t) l1_xlation_table; \
write_ttbr0_el##_el(ttbr); \
\
/* Ensure all translation table writes have drained */ \
/* into memory, the TLB invalidation is complete, */ \
/* and translation register writes are committed */ \
/* before enabling the MMU */ \
dsb(); \
isb(); \
\
sctlr = read_sctlr_el##_el(); \
sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT | SCTLR_I_BIT; \
sctlr |= SCTLR_A_BIT | SCTLR_C_BIT; \
write_sctlr_el##_el(sctlr); \
\
/* Ensure the MMU enable takes effect immediately */ \
isb(); \
}
/* Define EL1 and EL3 variants of the function enabling the MMU */
DEFINE_ENABLE_MMU_EL(1, 0, tlbivmalle1)
DEFINE_ENABLE_MMU_EL(3, TCR_EL3_RES1, tlbialle3)
static unsigned long fvp_config[CONFIG_LIMIT];
/*
* Table of regions to map using the MMU.
@@ -131,7 +73,7 @@ const mmap_region_t fvp_mmap[] = {
* the platform memory map & initialize the mmu, for the given exception level
******************************************************************************/
#define DEFINE_CONFIGURE_MMU_EL(_el) \
void configure_mmu_el##_el(unsigned long total_base, \
void fvp_configure_mmu_el##_el(unsigned long total_base, \
unsigned long total_size, \
unsigned long ro_start, \
unsigned long ro_limit, \
@@ -156,10 +98,10 @@ DEFINE_CONFIGURE_MMU_EL(1)
DEFINE_CONFIGURE_MMU_EL(3)
/* Simple routine which returns a configuration variable value */
unsigned long platform_get_cfgvar(unsigned int var_id)
unsigned long fvp_get_cfgvar(unsigned int var_id)
{
assert(var_id < CONFIG_LIMIT);
return platform_config[var_id];
return fvp_config[var_id];
}
/*******************************************************************************
@@ -169,7 +111,7 @@ unsigned long platform_get_cfgvar(unsigned int var_id)
* these platforms. This information is stored in a per-BL array to allow the
* code to take the correct path.Per BL platform configuration.
******************************************************************************/
int platform_config_setup(void)
int fvp_config_setup(void)
{
unsigned int rev, hbi, bld, arch, sys_id, midr_pn;
@@ -188,16 +130,16 @@ int platform_config_setup(void)
*/
switch (bld) {
case BLD_GIC_VE_MMAP:
platform_config[CONFIG_GICD_ADDR] = VE_GICD_BASE;
platform_config[CONFIG_GICC_ADDR] = VE_GICC_BASE;
platform_config[CONFIG_GICH_ADDR] = VE_GICH_BASE;
platform_config[CONFIG_GICV_ADDR] = VE_GICV_BASE;
fvp_config[CONFIG_GICD_ADDR] = VE_GICD_BASE;
fvp_config[CONFIG_GICC_ADDR] = VE_GICC_BASE;
fvp_config[CONFIG_GICH_ADDR] = VE_GICH_BASE;
fvp_config[CONFIG_GICV_ADDR] = VE_GICV_BASE;
break;
case BLD_GIC_A53A57_MMAP:
platform_config[CONFIG_GICD_ADDR] = BASE_GICD_BASE;
platform_config[CONFIG_GICC_ADDR] = BASE_GICC_BASE;
platform_config[CONFIG_GICH_ADDR] = BASE_GICH_BASE;
platform_config[CONFIG_GICV_ADDR] = BASE_GICV_BASE;
fvp_config[CONFIG_GICD_ADDR] = BASE_GICD_BASE;
fvp_config[CONFIG_GICC_ADDR] = BASE_GICC_BASE;
fvp_config[CONFIG_GICH_ADDR] = BASE_GICH_BASE;
fvp_config[CONFIG_GICV_ADDR] = BASE_GICV_BASE;
break;
default:
assert(0);
@@ -209,25 +151,25 @@ int platform_config_setup(void)
*/
switch (hbi) {
case HBI_FOUNDATION:
platform_config[CONFIG_MAX_AFF0] = 4;
platform_config[CONFIG_MAX_AFF1] = 1;
platform_config[CONFIG_CPU_SETUP] = 0;
platform_config[CONFIG_BASE_MMAP] = 0;
platform_config[CONFIG_HAS_CCI] = 0;
platform_config[CONFIG_HAS_TZC] = 0;
fvp_config[CONFIG_MAX_AFF0] = 4;
fvp_config[CONFIG_MAX_AFF1] = 1;
fvp_config[CONFIG_CPU_SETUP] = 0;
fvp_config[CONFIG_BASE_MMAP] = 0;
fvp_config[CONFIG_HAS_CCI] = 0;
fvp_config[CONFIG_HAS_TZC] = 0;
break;
case HBI_FVP_BASE:
midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK;
if ((midr_pn == MIDR_PN_A57) || (midr_pn == MIDR_PN_A53))
platform_config[CONFIG_CPU_SETUP] = 1;
fvp_config[CONFIG_CPU_SETUP] = 1;
else
platform_config[CONFIG_CPU_SETUP] = 0;
fvp_config[CONFIG_CPU_SETUP] = 0;
platform_config[CONFIG_MAX_AFF0] = 4;
platform_config[CONFIG_MAX_AFF1] = 2;
platform_config[CONFIG_BASE_MMAP] = 1;
platform_config[CONFIG_HAS_CCI] = 1;
platform_config[CONFIG_HAS_TZC] = 1;
fvp_config[CONFIG_MAX_AFF0] = 4;
fvp_config[CONFIG_MAX_AFF1] = 2;
fvp_config[CONFIG_BASE_MMAP] = 1;
fvp_config[CONFIG_HAS_CCI] = 1;
fvp_config[CONFIG_HAS_TZC] = 1;
break;
default:
assert(0);
@@ -263,7 +205,7 @@ void fvp_cci_setup(void)
* for locks as no other cpu is active at the
* moment
*/
cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI);
if (cci_setup)
cci_enable_coherency(read_mpidr());
}

6
plat/fvp/aarch64/plat_helpers.S → plat/fvp/aarch64/fvp_helpers.S
View File

@@ -32,15 +32,15 @@
#include <asm_macros.S>
#include <bl_common.h>
#include <gic_v2.h>
#include <platform.h>
#include "../drivers/pwrc/fvp_pwrc.h"
#include "../fvp_def.h"
.globl platform_get_entrypoint
.globl plat_secondary_cold_boot_setup
.globl platform_mem_init
.globl plat_report_exception
.macro platform_choose_gicmmap param1, param2, x_tmp, w_tmp, res
.macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res
ldr \x_tmp, =VE_SYSREGS_BASE + V2M_SYS_ID
ldr \w_tmp, [\x_tmp]
ubfx \w_tmp, \w_tmp, #SYS_ID_BLD_SHIFT, #SYS_ID_BLD_LENGTH
@@ -78,7 +78,7 @@ func plat_secondary_cold_boot_setup
*/
ldr x0, =VE_GICC_BASE
ldr x1, =BASE_GICC_BASE
platform_choose_gicmmap x0, x1, x2, w2, x1
fvp_choose_gicmmap x0, x1, x2, w2, x1
mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
str w0, [x1, #GICC_CTLR]

20
plat/fvp/bl1_plat_setup.c → plat/fvp/bl1_fvp_setup.c
View File

@@ -31,10 +31,12 @@
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <bl1.h>
#include <console.h>
#include <mmio.h>
#include <platform.h>
#include <platform_def.h>
#include "fvp_def.h"
#include "fvp_private.h"
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
@@ -103,7 +105,7 @@ void bl1_early_platform_setup(void)
}
/* Initialize the platform config for future decision making */
platform_config_setup();
fvp_config_setup();
}
/*******************************************************************************
@@ -114,7 +116,7 @@ void bl1_early_platform_setup(void)
void bl1_platform_setup(void)
{
/* Initialise the IO layer and register platform IO devices */
io_setup();
fvp_io_setup();
}
@@ -127,12 +129,12 @@ void bl1_plat_arch_setup(void)
{
fvp_cci_setup();
configure_mmu_el3(bl1_tzram_layout.total_base,
bl1_tzram_layout.total_size,
TZROM_BASE,
TZROM_BASE + TZROM_SIZE,
BL1_COHERENT_RAM_BASE,
BL1_COHERENT_RAM_LIMIT);
fvp_configure_mmu_el3(bl1_tzram_layout.total_base,
bl1_tzram_layout.total_size,
TZROM_BASE,
TZROM_BASE + TZROM_SIZE,
BL1_COHERENT_RAM_BASE,
BL1_COHERENT_RAM_LIMIT);
}

22
plat/fvp/bl2_plat_setup.c → plat/fvp/bl2_fvp_setup.c
View File

@@ -31,10 +31,12 @@
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <bl2.h>
#include <console.h>
#include <platform.h>
#include <platform_def.h>
#include <string.h>
#include "fvp_def.h"
#include "fvp_private.h"
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
@@ -177,7 +179,7 @@ void bl2_early_platform_setup(meminfo_t *mem_layout)
bl2_tzram_layout.next = 0;
/* Initialize the platform config for future decision making */
platform_config_setup();
fvp_config_setup();
}
/*******************************************************************************
@@ -192,10 +194,10 @@ void bl2_platform_setup(void)
* other platforms might have more programmable security devices
* present.
*/
plat_security_setup();
fvp_security_setup();
/* Initialise the IO layer and register platform IO devices */
io_setup();
fvp_io_setup();
}
/* Flush the TF params and the TF plat params */
@@ -212,12 +214,12 @@ void bl2_plat_flush_bl31_params(void)
******************************************************************************/
void bl2_plat_arch_setup()
{
configure_mmu_el1(bl2_tzram_layout.total_base,
bl2_tzram_layout.total_size,
BL2_RO_BASE,
BL2_RO_LIMIT,
BL2_COHERENT_RAM_BASE,
BL2_COHERENT_RAM_LIMIT);
fvp_configure_mmu_el1(bl2_tzram_layout.total_base,
bl2_tzram_layout.total_size,
BL2_RO_BASE,
BL2_RO_LIMIT,
BL2_COHERENT_RAM_BASE,
BL2_COHERENT_RAM_LIMIT);
}
/*******************************************************************************

30
plat/fvp/bl31_plat_setup.c → plat/fvp/bl31_fvp_setup.c
View File

@@ -38,6 +38,8 @@
#include <platform.h>
#include <stddef.h>
#include "drivers/pwrc/fvp_pwrc.h"
#include "fvp_def.h"
#include "fvp_private.h"
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
@@ -86,16 +88,16 @@ static bl31_params_t *bl2_to_bl31_params;
* while BL32 corresponds to the secure image type. A NULL pointer is returned
* if the image does not exist.
******************************************************************************/
entry_point_info_t *bl31_get_next_image_info(uint32_t type)
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
{
entry_point_info_t *next_image_info;
#if RESET_TO_BL31
if (type == NON_SECURE)
plat_get_entry_point_info(NON_SECURE, &bl33_entrypoint_info);
fvp_get_entry_point_info(NON_SECURE, &bl33_entrypoint_info);
else
plat_get_entry_point_info(SECURE, &bl32_entrypoint_info);
fvp_get_entry_point_info(SECURE, &bl32_entrypoint_info);
next_image_info = (type == NON_SECURE) ?
&bl33_entrypoint_info :
@@ -132,7 +134,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
console_init(PL011_UART0_BASE);
/* Initialize the platform config for future decision making */
platform_config_setup();
fvp_config_setup();
#if RESET_TO_BL31
/* There are no parameters from BL2 if BL31 is a reset vector */
@@ -146,7 +148,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
* other platforms might have more programmable security devices
* present.
*/
plat_security_setup();
fvp_security_setup();
#else
/* Check params passed from BL2 should not be NULL,
* We are not checking plat_params_from_bl2 as NULL as we are not
@@ -197,7 +199,7 @@ void bl31_platform_setup()
fvp_pwrc_setup();
/* Topologies are best known to the platform. */
plat_setup_topology();
fvp_setup_topology();
}
/*******************************************************************************
@@ -208,14 +210,14 @@ void bl31_plat_arch_setup()
{
#if RESET_TO_BL31
fvp_cci_setup();
#endif
configure_mmu_el3(BL31_RO_BASE,
(BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
BL31_RO_BASE,
BL31_RO_LIMIT,
BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT);
#endif
fvp_configure_mmu_el3(BL31_RO_BASE,
(BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
BL31_RO_BASE,
BL31_RO_LIMIT,
BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT);
}
#if RESET_TO_BL31
@@ -223,7 +225,7 @@ void bl31_plat_arch_setup()
* Generate the entry point info for Non Secure and Secure images
* for transferring control from BL31
******************************************************************************/
void plat_get_entry_point_info(unsigned long target_security,
void fvp_get_entry_point_info(unsigned long target_security,
entry_point_info_t *target_entry_info)
{
if (target_security == NON_SECURE) {

18
plat/fvp/bl32_plat_setup.c → plat/fvp/bl32_fvp_setup.c
View File

@@ -28,11 +28,11 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch_helpers.h>
#include <bl_common.h>
#include <bl32.h>
#include <console.h>
#include <platform.h>
#include "fvp_def.h"
#include "fvp_private.h"
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
@@ -75,7 +75,7 @@ void bl32_early_platform_setup(void)
console_init(PL011_UART1_BASE);
/* Initialize the platform config for future decision making */
platform_config_setup();
fvp_config_setup();
}
/*******************************************************************************
@@ -92,10 +92,10 @@ void bl32_platform_setup()
******************************************************************************/
void bl32_plat_arch_setup()
{
configure_mmu_el1(BL32_RO_BASE,
(BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE),
BL32_RO_BASE,
BL32_RO_LIMIT,
BL32_COHERENT_RAM_BASE,
BL32_COHERENT_RAM_LIMIT);
fvp_configure_mmu_el1(BL32_RO_BASE,
(BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE),
BL32_RO_BASE,
BL32_RO_LIMIT,
BL32_COHERENT_RAM_BASE,
BL32_COHERENT_RAM_LIMIT);
}

1
plat/fvp/drivers/pwrc/fvp_pwrc.c
View File

@@ -30,6 +30,7 @@
#include <bakery_lock.h>
#include <mmio.h>
#include "../../fvp_def.h"
#include "fvp_pwrc.h"
/*

16
plat/fvp/drivers/pwrc/fvp_pwrc.h
View File

@@ -63,14 +63,14 @@
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
extern int fvp_pwrc_setup(void);
extern void fvp_pwrc_write_pcoffr(unsigned long);
extern void fvp_pwrc_write_ppoffr(unsigned long);
extern void fvp_pwrc_write_pponr(unsigned long);
extern void fvp_pwrc_set_wen(unsigned long);
extern void fvp_pwrc_clr_wen(unsigned long);
extern unsigned int fvp_pwrc_read_psysr(unsigned long);
extern unsigned int fvp_pwrc_get_cpu_wkr(unsigned long);
int fvp_pwrc_setup(void);
void fvp_pwrc_write_pcoffr(unsigned long);
void fvp_pwrc_write_ppoffr(unsigned long);
void fvp_pwrc_write_pponr(unsigned long);
void fvp_pwrc_set_wen(unsigned long);
void fvp_pwrc_clr_wen(unsigned long);
unsigned int fvp_pwrc_read_psysr(unsigned long);
unsigned int fvp_pwrc_get_cpu_wkr(unsigned long);
#endif /*__ASSEMBLY__*/

234
plat/fvp/fvp_def.h Normal file
View File

@@ -0,0 +1,234 @@
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FVP_DEF_H__
#define __FVP_DEF_H__
#include <platform_def.h> /* for TZROM_SIZE */
/* Firmware Image Package */
#define FIP_IMAGE_NAME "fip.bin"
/* Constants for accessing platform configuration */
#define CONFIG_GICD_ADDR 0
#define CONFIG_GICC_ADDR 1
#define CONFIG_GICH_ADDR 2
#define CONFIG_GICV_ADDR 3
#define CONFIG_MAX_AFF0 4
#define CONFIG_MAX_AFF1 5
/* Indicate whether the CPUECTLR SMP bit should be enabled. */
#define CONFIG_CPU_SETUP 6
#define CONFIG_BASE_MMAP 7
/* Indicates whether CCI should be enabled on the platform. */
#define CONFIG_HAS_CCI 8
#define CONFIG_HAS_TZC 9
#define CONFIG_LIMIT 10
/*******************************************************************************
* FVP memory map related constants
******************************************************************************/
#define FLASH0_BASE 0x08000000
#define FLASH0_SIZE TZROM_SIZE
#define FLASH1_BASE 0x0c000000
#define FLASH1_SIZE 0x04000000
#define PSRAM_BASE 0x14000000
#define PSRAM_SIZE 0x04000000
#define VRAM_BASE 0x18000000
#define VRAM_SIZE 0x02000000
/* Aggregate of all devices in the first GB */
#define DEVICE0_BASE 0x1a000000
#define DEVICE0_SIZE 0x12200000
#define DEVICE1_BASE 0x2f000000
#define DEVICE1_SIZE 0x200000
#define NSRAM_BASE 0x2e000000
#define NSRAM_SIZE 0x10000
#define MBOX_OFF 0x1000
/* Base address where parameters to BL31 are stored */
#define PARAMS_BASE TZDRAM_BASE
#define DRAM1_BASE 0x80000000ull
#define DRAM1_SIZE 0x80000000ull
#define DRAM1_END (DRAM1_BASE + DRAM1_SIZE - 1)
#define DRAM1_SEC_SIZE 0x01000000ull
#define DRAM_BASE DRAM1_BASE
#define DRAM_SIZE DRAM1_SIZE
#define DRAM2_BASE 0x880000000ull
#define DRAM2_SIZE 0x780000000ull
#define DRAM2_END (DRAM2_BASE + DRAM2_SIZE - 1)
#define PCIE_EXP_BASE 0x40000000
#define TZRNG_BASE 0x7fe60000
#define TZNVCTR_BASE 0x7fe70000
#define TZROOTKEY_BASE 0x7fe80000
/* Memory mapped Generic timer interfaces */
#define SYS_CNTCTL_BASE 0x2a430000
#define SYS_CNTREAD_BASE 0x2a800000
#define SYS_TIMCTL_BASE 0x2a810000
/* V2M motherboard system registers & offsets */
#define VE_SYSREGS_BASE 0x1c010000
#define V2M_SYS_ID 0x0
#define V2M_SYS_LED 0x8
#define V2M_SYS_CFGDATA 0xa0
#define V2M_SYS_CFGCTRL 0xa4
/* Load address of BL33 in the FVP port */
#define NS_IMAGE_OFFSET (DRAM1_BASE + 0x8000000) /* DRAM + 128MB */
/*
* V2M sysled bit definitions. The values written to this
* register are defined in arch.h & runtime_svc.h. Only
* used by the primary cpu to diagnose any cold boot issues.
*
* SYS_LED[0] - Security state (S=0/NS=1)
* SYS_LED[2:1] - Exception Level (EL3-EL0)
* SYS_LED[7:3] - Exception Class (Sync/Async & origin)
*
*/
#define SYS_LED_SS_SHIFT 0x0
#define SYS_LED_EL_SHIFT 0x1
#define SYS_LED_EC_SHIFT 0x3
#define SYS_LED_SS_MASK 0x1
#define SYS_LED_EL_MASK 0x3
#define SYS_LED_EC_MASK 0x1f
/* V2M sysid register bits */
#define SYS_ID_REV_SHIFT 27
#define SYS_ID_HBI_SHIFT 16
#define SYS_ID_BLD_SHIFT 12
#define SYS_ID_ARCH_SHIFT 8
#define SYS_ID_FPGA_SHIFT 0
#define SYS_ID_REV_MASK 0xf
#define SYS_ID_HBI_MASK 0xfff
#define SYS_ID_BLD_MASK 0xf
#define SYS_ID_ARCH_MASK 0xf
#define SYS_ID_FPGA_MASK 0xff
#define SYS_ID_BLD_LENGTH 4
#define REV_FVP 0x0
#define HBI_FVP_BASE 0x020
#define HBI_FOUNDATION 0x010
#define BLD_GIC_VE_MMAP 0x0
#define BLD_GIC_A53A57_MMAP 0x1
#define ARCH_MODEL 0x1
/* FVP Power controller base address*/
#define PWRC_BASE 0x1c100000
/*******************************************************************************
* CCI-400 related constants
******************************************************************************/
#define CCI400_BASE 0x2c090000
#define CCI400_SL_IFACE_CLUSTER0 3
#define CCI400_SL_IFACE_CLUSTER1 4
#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \
CCI400_SL_IFACE_CLUSTER1 : \
CCI400_SL_IFACE_CLUSTER0)
/*******************************************************************************
* GIC-400 & interrupt handling related constants
******************************************************************************/
/* VE compatible GIC memory map */
#define VE_GICD_BASE 0x2c001000
#define VE_GICC_BASE 0x2c002000
#define VE_GICH_BASE 0x2c004000
#define VE_GICV_BASE 0x2c006000
/* Base FVP compatible GIC memory map */
#define BASE_GICD_BASE 0x2f000000
#define BASE_GICR_BASE 0x2f100000
#define BASE_GICC_BASE 0x2c000000
#define BASE_GICH_BASE 0x2c010000
#define BASE_GICV_BASE 0x2c02f000
#define IRQ_TZ_WDOG 56
#define IRQ_SEC_PHY_TIMER 29
#define IRQ_SEC_SGI_0 8
#define IRQ_SEC_SGI_1 9
#define IRQ_SEC_SGI_2 10
#define IRQ_SEC_SGI_3 11
#define IRQ_SEC_SGI_4 12
#define IRQ_SEC_SGI_5 13
#define IRQ_SEC_SGI_6 14
#define IRQ_SEC_SGI_7 15
#define IRQ_SEC_SGI_8 16
/*******************************************************************************
* PL011 related constants
******************************************************************************/
#define PL011_UART0_BASE 0x1c090000
#define PL011_UART1_BASE 0x1c0a0000
#define PL011_UART2_BASE 0x1c0b0000
#define PL011_UART3_BASE 0x1c0c0000
/*******************************************************************************
* TrustZone address space controller related constants
******************************************************************************/
#define TZC400_BASE 0x2a4a0000
/*
* The NSAIDs for this platform as used to program the TZC400.
*/
/* The FVP has 4 bits of NSAIDs. Used with TZC FAIL_ID (ACE Lite ID width) */
#define FVP_AID_WIDTH 4
/* NSAIDs used by devices in TZC filter 0 on FVP */
#define FVP_NSAID_DEFAULT 0
#define FVP_NSAID_PCI 1
#define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */
#define FVP_NSAID_AP 9 /* Application Processors */
#define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */
/* NSAIDs used by devices in TZC filter 2 on FVP */
#define FVP_NSAID_HDLCD0 2
#define FVP_NSAID_CLCD 7
#endif /* __FVP_DEF_H__ */

28
plat/fvp/plat_gic.c → plat/fvp/fvp_gic.c
View File

@@ -37,6 +37,8 @@
#include <interrupt_mgmt.h>
#include <platform.h>
#include <stdint.h>
#include "fvp_def.h"
#include "fvp_private.h"
/*******************************************************************************
* This function does some minimal GICv3 configuration. The Firmware itself does
@@ -275,8 +277,8 @@ void gic_setup(void)
{
unsigned int gicd_base, gicc_base;
gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR);
gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
gicd_base = fvp_get_cfgvar(CONFIG_GICD_ADDR);
gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
gic_cpuif_setup(gicc_base);
gic_distif_setup(gicd_base);
@@ -296,7 +298,7 @@ void gic_setup(void)
******************************************************************************/
uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
{
uint32_t gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
uint32_t gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
assert(type == INTR_TYPE_S_EL1 ||
type == INTR_TYPE_EL3 ||
@@ -322,11 +324,11 @@ uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
* the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
* interrupt pending.
******************************************************************************/
uint32_t ic_get_pending_interrupt_type()
uint32_t plat_ic_get_pending_interrupt_type()
{
uint32_t id, gicc_base;
gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
id = gicc_read_hppir(gicc_base);
/* Assume that all secure interrupts are S-EL1 interrupts */
@@ -344,11 +346,11 @@ uint32_t ic_get_pending_interrupt_type()
* the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
* interrupt pending.
******************************************************************************/
uint32_t ic_get_pending_interrupt_id()
uint32_t plat_ic_get_pending_interrupt_id()
{
uint32_t id, gicc_base;
gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
id = gicc_read_hppir(gicc_base);
if (id < 1022)
@@ -368,18 +370,18 @@ uint32_t ic_get_pending_interrupt_id()
* This functions reads the GIC cpu interface Interrupt Acknowledge register
* to start handling the pending interrupt. It returns the contents of the IAR.
******************************************************************************/
uint32_t ic_acknowledge_interrupt()
uint32_t plat_ic_acknowledge_interrupt()
{
return gicc_read_IAR(platform_get_cfgvar(CONFIG_GICC_ADDR));
return gicc_read_IAR(fvp_get_cfgvar(CONFIG_GICC_ADDR));
}
/*******************************************************************************
* This functions writes the GIC cpu interface End Of Interrupt register with
* the passed value to finish handling the active interrupt
******************************************************************************/
void ic_end_of_interrupt(uint32_t id)
void plat_ic_end_of_interrupt(uint32_t id)
{
gicc_write_EOIR(platform_get_cfgvar(CONFIG_GICC_ADDR), id);
gicc_write_EOIR(fvp_get_cfgvar(CONFIG_GICC_ADDR), id);
return;
}
@@ -388,11 +390,11 @@ void ic_end_of_interrupt(uint32_t id)
* this interrupt has been configured under by the interrupt controller i.e.
* group0 or group1.
******************************************************************************/
uint32_t ic_get_interrupt_type(uint32_t id)
uint32_t plat_ic_get_interrupt_type(uint32_t id)
{
uint32_t group;
group = gicd_get_igroupr(platform_get_cfgvar(CONFIG_GICD_ADDR), id);
group = gicd_get_igroupr(fvp_get_cfgvar(CONFIG_GICD_ADDR), id);
/* Assume that all secure interrupts are S-EL1 interrupts */
if (group == GRP0)

4
plat/fvp/plat_io_storage.c → plat/fvp/fvp_io_storage.c
View File

@@ -35,9 +35,9 @@
#include <io_memmap.h>
#include <io_storage.h>
#include <io_semihosting.h>
#include <platform.h>
#include <semihosting.h> /* For FOPEN_MODE_... */
#include <string.h>
#include "fvp_def.h"
/* IO devices */
static io_plat_data_t io_data;
@@ -168,7 +168,7 @@ static int open_semihosting(const uintptr_t spec)
return result;
}
void io_setup (void)
void fvp_io_setup (void)
{
int io_result = IO_FAIL;

21
plat/fvp/plat_pm.c → plat/fvp/fvp_pm.c
View File

@@ -34,8 +34,11 @@
#include <cci400.h>
#include <mmio.h>
#include <platform.h>
#include <platform_def.h>
#include <psci.h>
#include "drivers/pwrc/fvp_pwrc.h"
#include "fvp_def.h"
#include "fvp_private.h"
/*******************************************************************************
* FVP handler called when an affinity instance is about to enter standby.
@@ -136,7 +139,7 @@ int fvp_affinst_off(unsigned long mpidr,
* Disable coherency if this cluster is to be
* turned off
*/
cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI);
if (cci_setup) {
cci_disable_coherency(mpidr);
}
@@ -157,7 +160,7 @@ int fvp_affinst_off(unsigned long mpidr,
* Take this cpu out of intra-cluster coherency if
* the FVP flavour supports the SMP bit.
*/
cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP);
cpu_setup = fvp_get_cfgvar(CONFIG_CPU_SETUP);
if (cpu_setup) {
ectlr = read_cpuectlr();
ectlr &= ~CPUECTLR_SMP_BIT;
@@ -168,7 +171,7 @@ int fvp_affinst_off(unsigned long mpidr,
* Prevent interrupts from spuriously waking up
* this cpu
*/
gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
gic_cpuif_deactivate(gicc_base);
/*
@@ -216,7 +219,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
* Disable coherency if this cluster is to be
* turned off
*/
cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI);
if (cci_setup) {
cci_disable_coherency(mpidr);
}
@@ -236,7 +239,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
* Take this cpu out of intra-cluster coherency if
* the FVP flavour supports the SMP bit.
*/
cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP);
cpu_setup = fvp_get_cfgvar(CONFIG_CPU_SETUP);
if (cpu_setup) {
ectlr = read_cpuectlr();
ectlr &= ~CPUECTLR_SMP_BIT;
@@ -254,7 +257,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
* Prevent interrupts from spuriously waking up
* this cpu
*/
gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
gic_cpuif_deactivate(gicc_base);
/*
@@ -322,7 +325,7 @@ int fvp_affinst_on_finish(unsigned long mpidr,
* Turn on intra-cluster coherency if the FVP flavour supports
* it.
*/
cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP);
cpu_setup = fvp_get_cfgvar(CONFIG_CPU_SETUP);
if (cpu_setup) {
ectlr = read_cpuectlr();
ectlr |= CPUECTLR_SMP_BIT;
@@ -342,8 +345,8 @@ int fvp_affinst_on_finish(unsigned long mpidr,
flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
sizeof(unsigned long));
gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR);
gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
gicd_base = fvp_get_cfgvar(CONFIG_GICD_ADDR);
gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
/* Enable the gic cpu interface */
gic_cpuif_setup(gicc_base);

106
include/bl2/bl2.h → plat/fvp/fvp_private.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,46 +28,82 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __BL2_H__
#define __BL2_H__
#ifndef __FVP_PRIVATE_H__
#define __FVP_PRIVATE_H__
/******************************************
* Data declarations
*****************************************/
extern unsigned long long bl2_entrypoint;
#include <bl_common.h>
#include <platform_def.h>
/******************************************
typedef volatile struct mailbox {
unsigned long value
__attribute__((__aligned__(CACHE_WRITEBACK_GRANULE)));
} mailbox_t;
/*******************************************************************************
* This structure represents the superset of information that is passed to
* BL31 e.g. while passing control to it from BL2 which is bl31_params
* and bl31_plat_params and its elements
******************************************************************************/
typedef struct bl2_to_bl31_params_mem {
bl31_params_t bl31_params;
image_info_t bl31_image_info;
image_info_t bl32_image_info;
image_info_t bl33_image_info;
entry_point_info_t bl33_ep_info;
entry_point_info_t bl32_ep_info;
entry_point_info_t bl31_ep_info;
} bl2_to_bl31_params_mem_t;
/*******************************************************************************
* Forward declarations
*****************************************/
******************************************************************************/
struct meminfo;
struct bl31_args;
/******************************************
* Function prototypes
*****************************************/
extern void bl2_platform_setup(void);
extern struct meminfo *bl2_plat_sec_mem_layout(void);
/*******************************************************************************
* This function returns a pointer to the shared memory that the platform has
* kept aside to pass trusted firmware related information that BL3-1
* could need
* Function and variable prototypes
******************************************************************************/
extern struct bl31_params *bl2_plat_get_bl31_params(void);
void fvp_configure_mmu_el1(unsigned long total_base,
unsigned long total_size,
unsigned long,
unsigned long,
unsigned long,
unsigned long);
void fvp_configure_mmu_el3(unsigned long total_base,
unsigned long total_size,
unsigned long,
unsigned long,
unsigned long,
unsigned long);
unsigned long fvp_get_cfgvar(unsigned int);
int fvp_config_setup(void);
#if RESET_TO_BL31
void fvp_get_entry_point_info(unsigned long target_security,
struct entry_point_info *target_entry_info);
#endif
void fvp_cci_setup(void);
/* Declarations for fvp_gic.c */
void gic_cpuif_deactivate(unsigned int);
void gic_cpuif_setup(unsigned int);
void gic_pcpu_distif_setup(unsigned int);
void gic_setup(void);
/* Declarations for fvp_topology.c */
int fvp_setup_topology(void);
/* Declarations for fvp_io_storage.c */
void fvp_io_setup(void);
/* Declarations for fvp_security.c */
void fvp_security_setup(void);
/* Sets the entrypoint for BL32 */
void fvp_set_bl32_ep_info(struct entry_point_info *bl32_ep);
/* Sets the entrypoint for BL33 */
void fvp_set_bl33_ep_info(struct entry_point_info *bl33_ep);
/*******************************************************************************
* This function returns a pointer to the shared memory that the platform
* has kept to point to entry point information of BL31 to BL2
******************************************************************************/
extern struct entry_point_info *bl2_plat_get_bl31_ep_info(void);
/************************************************************************
* This function flushes to main memory all the params that are
* passed to BL3-1
**************************************************************************/
extern void bl2_plat_flush_bl31_params(void);
#endif /* __BL2_H__ */
#endif /* __FVP_PRIVATE_H__ */

9
plat/fvp/plat_security.c → plat/fvp/fvp_security.c
View File

@@ -29,9 +29,10 @@
*/
#include <assert.h>
#include <platform.h>
#include <tzc400.h>
#include <debug.h>
#include <tzc400.h>
#include "fvp_def.h"
#include "fvp_private.h"
/* Used to improve readability for configuring regions. */
#define FILTER_SHIFT(filter) (1 << filter)
@@ -42,7 +43,7 @@
* TODO:
* Might want to enable interrupt on violations when supported?
*/
void plat_security_setup(void)
void fvp_security_setup(void)
{
tzc_instance_t controller;
@@ -55,7 +56,7 @@ void plat_security_setup(void)
* configurations, those would be configured here.
*/
if (!platform_get_cfgvar(CONFIG_HAS_TZC))
if (!fvp_get_cfgvar(CONFIG_HAS_TZC))
return;
/*

4
plat/fvp/plat_topology.c → plat/fvp/fvp_topology.c
View File

@@ -29,7 +29,7 @@
*/
#include <assert.h>
#include <platform.h>
#include <platform_def.h>
/* TODO: Reusing psci error codes & state information. Get our own! */
#include <psci.h>
#include "drivers/pwrc/fvp_pwrc.h"
@@ -190,7 +190,7 @@ int plat_get_max_afflvl()
* the FVP flavour its running on. We construct all the mpidrs we can handle
* and rely on the PWRC.PSYSR to flag absent cpus when their status is queried.
******************************************************************************/
int plat_setup_topology()
int fvp_setup_topology()
{
unsigned char aff0, aff1, aff_state, aff0_offset = 0;
unsigned long mpidr;

4
plat/fvp/include/plat_macros.S
View File

@@ -29,7 +29,7 @@
*/
#include <gic_v2.h>
#include <platform.h>
#include "../fvp_def.h"
.section .rodata.gic_reg_name, "aS"
gic_regs: .asciz "gic_iar", "gic_ctlr", ""
@@ -44,7 +44,7 @@ gic_regs: .asciz "gic_iar", "gic_ctlr", ""
*/
.macro plat_print_gic_regs
mov x0, #CONFIG_GICC_ADDR
bl platform_get_cfgvar
bl fvp_get_cfgvar
/* gic base address is now in x0 */
ldr w1, [x0, #GICC_IAR]
ldr w2, [x0, #GICD_CTLR]

180
plat/fvp/include/platform_def.h Normal file
View File

@@ -0,0 +1,180 @@
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLATFORM_DEF_H__
#define __PLATFORM_DEF_H__
#include <arch.h>
/*******************************************************************************
* Platform binary types for linking
******************************************************************************/
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
/*******************************************************************************
* Generic platform constants
******************************************************************************/
/* Size of cacheable stacks */
#define PLATFORM_STACK_SIZE 0x800
/* Size of coherent stacks for debug and release builds */
#if DEBUG
#define PCPU_DV_MEM_STACK_SIZE 0x400
#else
#define PCPU_DV_MEM_STACK_SIZE 0x300
#endif
#define FIRMWARE_WELCOME_STR "Booting trusted firmware boot loader stage 1\n\r"
/* Trusted Boot Firmware BL2 */
#define BL2_IMAGE_NAME "bl2.bin"
/* EL3 Runtime Firmware BL31 */
#define BL31_IMAGE_NAME "bl31.bin"
/* Secure Payload BL32 (Trusted OS) */
#define BL32_IMAGE_NAME "bl32.bin"
/* Non-Trusted Firmware BL33 */
#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */
#define PLATFORM_CACHE_LINE_SIZE 64
#define PLATFORM_CLUSTER_COUNT 2ull
#define PLATFORM_CLUSTER0_CORE_COUNT 4
#define PLATFORM_CLUSTER1_CORE_COUNT 4
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
PLATFORM_CLUSTER0_CORE_COUNT)
#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
#define PRIMARY_CPU 0x0
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
#define TZROM_BASE 0x00000000
#define TZROM_SIZE 0x04000000
#define TZRAM_BASE 0x04000000
#define TZRAM_SIZE 0x40000
/* Location of trusted dram on the base fvp */
#define TZDRAM_BASE 0x06000000
#define TZDRAM_SIZE 0x02000000
/*******************************************************************************
* BL1 specific defines.
* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
* addresses.
******************************************************************************/
#define BL1_RO_BASE TZROM_BASE
#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE)
#define BL1_RW_BASE TZRAM_BASE
#define BL1_RW_LIMIT BL31_BASE
/*******************************************************************************
* BL2 specific defines.
******************************************************************************/
#define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xc000)
#define BL2_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
#define BL31_BASE (TZRAM_BASE + 0x6000)
#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
#define BL31_LIMIT BL32_BASE
#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
#define BL31_LIMIT BL2_BASE
#endif
/*******************************************************************************
* BL32 specific defines.
******************************************************************************/
/*
* On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
*/
#define TSP_IN_TZRAM 0
#define TSP_IN_TZDRAM 1
#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
# define TSP_SEC_MEM_BASE TZRAM_BASE
# define TSP_SEC_MEM_SIZE TZRAM_SIZE
# define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1c000)
# define BL32_LIMIT BL2_BASE
#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
# define TSP_SEC_MEM_BASE TZDRAM_BASE
# define TSP_SEC_MEM_SIZE TZDRAM_SIZE
# define BL32_BASE (TZDRAM_BASE + 0x2000)
# define BL32_LIMIT (TZDRAM_BASE + (1 << 21))
#else
# error "Unsupported TSP_RAM_LOCATION_ID value"
#endif
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define ADDR_SPACE_SIZE (1ull << 32)
#define MAX_XLAT_TABLES 3
#define MAX_MMAP_REGIONS 16
/*******************************************************************************
* ID of the secure physical generic timer interrupt.
******************************************************************************/
#define IRQ_SEC_PHY_TIMER 29
/*******************************************************************************
* CCI-400 related constants
******************************************************************************/
#define CCI400_BASE 0x2c090000
#define CCI400_SL_IFACE_CLUSTER0 3
#define CCI400_SL_IFACE_CLUSTER1 4
#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \
CCI400_SL_IFACE_CLUSTER1 : \
CCI400_SL_IFACE_CLUSTER0)
/*******************************************************************************
* Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only
* to the platform as it might have a combination of integrated and external
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
* line at any cache level. They could belong to different cpus/clusters &
* get written while being protected by different locks causing corruption of
* a valid mailbox address.
******************************************************************************/
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
#endif /* __PLATFORM_DEF_H__ */

549
plat/fvp/platform.h
View File

@@ -1,549 +0,0 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLATFORM_H__
#define __PLATFORM_H__
#include <arch.h>
#include <bl_common.h>
/*******************************************************************************
* Platform binary types for linking
******************************************************************************/
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
/*******************************************************************************
* Generic platform constants
******************************************************************************/
/* Size of cacheable stacks */
#define PLATFORM_STACK_SIZE 0x800
/* Size of coherent stacks for debug and release builds */
#if DEBUG
#define PCPU_DV_MEM_STACK_SIZE 0x400
#else
#define PCPU_DV_MEM_STACK_SIZE 0x300
#endif
#define FIRMWARE_WELCOME_STR "Booting trusted firmware boot loader stage 1\n\r"
/* Trusted Boot Firmware BL2 */
#define BL2_IMAGE_NAME "bl2.bin"
/* EL3 Runtime Firmware BL31 */
#define BL31_IMAGE_NAME "bl31.bin"
/* Secure Payload BL32 (Trusted OS) */
#define BL32_IMAGE_NAME "bl32.bin"
/* Non-Trusted Firmware BL33 and its load address */
#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */
#define NS_IMAGE_OFFSET (DRAM1_BASE + 0x8000000) /* DRAM + 128MB */
/* Firmware Image Package */
#define FIP_IMAGE_NAME "fip.bin"
#define PLATFORM_CACHE_LINE_SIZE 64
#define PLATFORM_CLUSTER_COUNT 2ull
#define PLATFORM_CLUSTER0_CORE_COUNT 4
#define PLATFORM_CLUSTER1_CORE_COUNT 4
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
PLATFORM_CLUSTER0_CORE_COUNT)
#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
#define PRIMARY_CPU 0x0
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4
/* Constants for accessing platform configuration */
#define CONFIG_GICD_ADDR 0
#define CONFIG_GICC_ADDR 1
#define CONFIG_GICH_ADDR 2
#define CONFIG_GICV_ADDR 3
#define CONFIG_MAX_AFF0 4
#define CONFIG_MAX_AFF1 5
/* Indicate whether the CPUECTLR SMP bit should be enabled. */
#define CONFIG_CPU_SETUP 6
#define CONFIG_BASE_MMAP 7
/* Indicates whether CCI should be enabled on the platform. */
#define CONFIG_HAS_CCI 8
#define CONFIG_HAS_TZC 9
#define CONFIG_LIMIT 10
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
#define TZROM_BASE 0x00000000
#define TZROM_SIZE 0x04000000
#define TZRAM_BASE 0x04000000
#define TZRAM_SIZE 0x40000
#define FLASH0_BASE 0x08000000
#define FLASH0_SIZE TZROM_SIZE
#define FLASH1_BASE 0x0c000000
#define FLASH1_SIZE 0x04000000
#define PSRAM_BASE 0x14000000
#define PSRAM_SIZE 0x04000000
#define VRAM_BASE 0x18000000
#define VRAM_SIZE 0x02000000
/* Aggregate of all devices in the first GB */
#define DEVICE0_BASE 0x1a000000
#define DEVICE0_SIZE 0x12200000
#define DEVICE1_BASE 0x2f000000
#define DEVICE1_SIZE 0x200000
#define NSRAM_BASE 0x2e000000
#define NSRAM_SIZE 0x10000
/* Location of trusted dram on the base fvp */
#define TZDRAM_BASE 0x06000000
#define TZDRAM_SIZE 0x02000000
#define MBOX_OFF 0x1000
/* Base address where parameters to BL31 are stored */
#define PARAMS_BASE TZDRAM_BASE
#define DRAM1_BASE 0x80000000ull
#define DRAM1_SIZE 0x80000000ull
#define DRAM1_END (DRAM1_BASE + DRAM1_SIZE - 1)
#define DRAM1_SEC_SIZE 0x01000000ull
#define DRAM_BASE DRAM1_BASE
#define DRAM_SIZE DRAM1_SIZE
#define DRAM2_BASE 0x880000000ull
#define DRAM2_SIZE 0x780000000ull
#define DRAM2_END (DRAM2_BASE + DRAM2_SIZE - 1)
#define PCIE_EXP_BASE 0x40000000
#define TZRNG_BASE 0x7fe60000
#define TZNVCTR_BASE 0x7fe70000
#define TZROOTKEY_BASE 0x7fe80000
/* Memory mapped Generic timer interfaces */
#define SYS_CNTCTL_BASE 0x2a430000
#define SYS_CNTREAD_BASE 0x2a800000
#define SYS_TIMCTL_BASE 0x2a810000
/* Counter timer module offsets */
#define CNTNSAR 0x4
#define CNTNSAR_NS_SHIFT(x) x
#define CNTACR_BASE(x) (0x40 + (x << 2))
#define CNTACR_RPCT_SHIFT 0x0
#define CNTACR_RVCT_SHIFT 0x1
#define CNTACR_RFRQ_SHIFT 0x2
#define CNTACR_RVOFF_SHIFT 0x3
#define CNTACR_RWVT_SHIFT 0x4
#define CNTACR_RWPT_SHIFT 0x5
/* V2M motherboard system registers & offsets */
#define VE_SYSREGS_BASE 0x1c010000
#define V2M_SYS_ID 0x0
#define V2M_SYS_LED 0x8
#define V2M_SYS_CFGDATA 0xa0
#define V2M_SYS_CFGCTRL 0xa4
/*
* V2M sysled bit definitions. The values written to this
* register are defined in arch.h & runtime_svc.h. Only
* used by the primary cpu to diagnose any cold boot issues.
*
* SYS_LED[0] - Security state (S=0/NS=1)
* SYS_LED[2:1] - Exception Level (EL3-EL0)
* SYS_LED[7:3] - Exception Class (Sync/Async & origin)
*
*/
#define SYS_LED_SS_SHIFT 0x0
#define SYS_LED_EL_SHIFT 0x1
#define SYS_LED_EC_SHIFT 0x3
#define SYS_LED_SS_MASK 0x1
#define SYS_LED_EL_MASK 0x3
#define SYS_LED_EC_MASK 0x1f
/* V2M sysid register bits */
#define SYS_ID_REV_SHIFT 27
#define SYS_ID_HBI_SHIFT 16
#define SYS_ID_BLD_SHIFT 12
#define SYS_ID_ARCH_SHIFT 8
#define SYS_ID_FPGA_SHIFT 0
#define SYS_ID_REV_MASK 0xf
#define SYS_ID_HBI_MASK 0xfff
#define SYS_ID_BLD_MASK 0xf
#define SYS_ID_ARCH_MASK 0xf
#define SYS_ID_FPGA_MASK 0xff
#define SYS_ID_BLD_LENGTH 4
#define REV_FVP 0x0
#define HBI_FVP_BASE 0x020
#define HBI_FOUNDATION 0x010
#define BLD_GIC_VE_MMAP 0x0
#define BLD_GIC_A53A57_MMAP 0x1
#define ARCH_MODEL 0x1
/* FVP Power controller base address*/
#define PWRC_BASE 0x1c100000
/*******************************************************************************
* Platform specific per affinity states. Distinction between off and suspend
* is made to allow reporting of a suspended cpu as still being on e.g. in the
* affinity_info psci call.
******************************************************************************/
#define PLATFORM_MAX_AFF0 4
#define PLATFORM_MAX_AFF1 2
#define PLAT_AFF_UNK 0xff
#define PLAT_AFF0_OFF 0x0
#define PLAT_AFF0_ONPENDING 0x1
#define PLAT_AFF0_SUSPEND 0x2
#define PLAT_AFF0_ON 0x3
#define PLAT_AFF1_OFF 0x0
#define PLAT_AFF1_ONPENDING 0x1
#define PLAT_AFF1_SUSPEND 0x2
#define PLAT_AFF1_ON 0x3
/*******************************************************************************
* BL1 specific defines.
* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
* addresses.
******************************************************************************/
#define BL1_RO_BASE TZROM_BASE
#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE)
#define BL1_RW_BASE TZRAM_BASE
#define BL1_RW_LIMIT BL31_BASE
/*******************************************************************************
* BL2 specific defines.
******************************************************************************/
#define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xc000)
#define BL2_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
#define BL31_BASE (TZRAM_BASE + 0x6000)
#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
#define BL31_LIMIT BL32_BASE
#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
#define BL31_LIMIT BL2_BASE
#endif
/*******************************************************************************
* BL32 specific defines.
******************************************************************************/
/*
* On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
*/
#define TSP_IN_TZRAM 0
#define TSP_IN_TZDRAM 1
#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
# define TSP_SEC_MEM_BASE TZRAM_BASE
# define TSP_SEC_MEM_SIZE TZRAM_SIZE
# define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1c000)
# define BL32_LIMIT BL2_BASE
#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
# define TSP_SEC_MEM_BASE TZDRAM_BASE
# define TSP_SEC_MEM_SIZE TZDRAM_SIZE
# define BL32_BASE (TZDRAM_BASE + 0x2000)
# define BL32_LIMIT (TZDRAM_BASE + (1 << 21))
#else
# error "Unsupported TSP_RAM_LOCATION_ID value"
#endif
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define ADDR_SPACE_SIZE (1ull << 32)
#define MAX_XLAT_TABLES 3
#define MAX_MMAP_REGIONS 16
/*******************************************************************************
* CCI-400 related constants
******************************************************************************/
#define CCI400_BASE 0x2c090000
#define CCI400_SL_IFACE_CLUSTER0 3
#define CCI400_SL_IFACE_CLUSTER1 4
#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \
CCI400_SL_IFACE_CLUSTER1 : \
CCI400_SL_IFACE_CLUSTER0)
/*******************************************************************************
* GIC-400 & interrupt handling related constants
******************************************************************************/
/* VE compatible GIC memory map */
#define VE_GICD_BASE 0x2c001000
#define VE_GICC_BASE 0x2c002000
#define VE_GICH_BASE 0x2c004000
#define VE_GICV_BASE 0x2c006000
/* Base FVP compatible GIC memory map */
#define BASE_GICD_BASE 0x2f000000
#define BASE_GICR_BASE 0x2f100000
#define BASE_GICC_BASE 0x2c000000
#define BASE_GICH_BASE 0x2c010000
#define BASE_GICV_BASE 0x2c02f000
#define IRQ_TZ_WDOG 56
#define IRQ_SEC_PHY_TIMER 29
#define IRQ_SEC_SGI_0 8
#define IRQ_SEC_SGI_1 9
#define IRQ_SEC_SGI_2 10
#define IRQ_SEC_SGI_3 11
#define IRQ_SEC_SGI_4 12
#define IRQ_SEC_SGI_5 13
#define IRQ_SEC_SGI_6 14
#define IRQ_SEC_SGI_7 15
#define IRQ_SEC_SGI_8 16
/*******************************************************************************
* PL011 related constants
******************************************************************************/
#define PL011_UART0_BASE 0x1c090000
#define PL011_UART1_BASE 0x1c0a0000
#define PL011_UART2_BASE 0x1c0b0000
#define PL011_UART3_BASE 0x1c0c0000
/*******************************************************************************
* TrustZone address space controller related constants
******************************************************************************/
#define TZC400_BASE 0x2a4a0000
/*
* The NSAIDs for this platform as used to program the TZC400.
*/
/* The FVP has 4 bits of NSAIDs. Used with TZC FAIL_ID (ACE Lite ID width) */
#define FVP_AID_WIDTH 4
/* NSAIDs used by devices in TZC filter 0 on FVP */
#define FVP_NSAID_DEFAULT 0
#define FVP_NSAID_PCI 1
#define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */
#define FVP_NSAID_AP 9 /* Application Processors */
#define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */
/* NSAIDs used by devices in TZC filter 2 on FVP */
#define FVP_NSAID_HDLCD0 2
#define FVP_NSAID_CLCD 7
/*******************************************************************************
* Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only
* to the platform as it might have a combination of integrated and external
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
* line at any cache level. They could belong to different cpus/clusters &
* get written while being protected by different locks causing corruption of
* a valid mailbox address.
******************************************************************************/
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
#ifndef __ASSEMBLY__
#include <stdint.h>
#include <bl_common.h>
typedef volatile struct mailbox {
unsigned long value
__attribute__((__aligned__(CACHE_WRITEBACK_GRANULE)));
} mailbox_t;
/*******************************************************************************
* Forward declarations
******************************************************************************/
struct plat_pm_ops;
struct meminfo;
struct bl31_params;
struct image_info;
struct entry_point_info;
/*******************************************************************************
* This structure represents the superset of information that is passed to
* BL31 e.g. while passing control to it from BL2 which is bl31_params
* and another platform specific params
******************************************************************************/
typedef struct bl2_to_bl31_params_mem {
struct bl31_params bl31_params;
struct image_info bl31_image_info;
struct image_info bl32_image_info;
struct image_info bl33_image_info;
struct entry_point_info bl33_ep_info;
struct entry_point_info bl32_ep_info;
struct entry_point_info bl31_ep_info;
} bl2_to_bl31_params_mem_t;
/*******************************************************************************
* Function and variable prototypes
******************************************************************************/
extern unsigned long *bl1_normal_ram_base;
extern unsigned long *bl1_normal_ram_len;
extern unsigned long *bl1_normal_ram_limit;
extern unsigned long *bl1_normal_ram_zi_base;
extern unsigned long *bl1_normal_ram_zi_len;
extern unsigned long *bl1_coherent_ram_base;
extern unsigned long *bl1_coherent_ram_len;
extern unsigned long *bl1_coherent_ram_limit;
extern unsigned long *bl1_coherent_ram_zi_base;
extern unsigned long *bl1_coherent_ram_zi_len;
extern unsigned long warm_boot_entrypoint;
extern void bl1_plat_arch_setup(void);
extern void bl2_plat_arch_setup(void);
extern void bl31_plat_arch_setup(void);
extern int platform_setup_pm(const struct plat_pm_ops **);
extern unsigned int platform_get_core_pos(unsigned long mpidr);
extern void enable_mmu_el1(void);
extern void enable_mmu_el3(void);
extern void configure_mmu_el1(unsigned long total_base,
unsigned long total_size,
unsigned long ro_start,
unsigned long ro_limit,
unsigned long coh_start,
unsigned long coh_limit);
extern void configure_mmu_el3(unsigned long total_base,
unsigned long total_size,
unsigned long ro_start,
unsigned long ro_limit,
unsigned long coh_start,
unsigned long coh_limit);
extern unsigned long platform_get_cfgvar(unsigned int);
extern int platform_config_setup(void);
extern void plat_report_exception(unsigned long);
extern unsigned long plat_get_ns_image_entrypoint(void);
extern unsigned long platform_get_stack(unsigned long mpidr);
extern uint64_t plat_get_syscnt_freq(void);
#if RESET_TO_BL31
extern void plat_get_entry_point_info(unsigned long target_security,
struct entry_point_info *target_entry_info);
#endif
extern void fvp_cci_setup(void);
/* Declarations for plat_gic.c */
extern uint32_t ic_get_pending_interrupt_id(void);
extern uint32_t ic_get_pending_interrupt_type(void);
extern uint32_t ic_acknowledge_interrupt(void);
extern uint32_t ic_get_interrupt_type(uint32_t id);
extern void ic_end_of_interrupt(uint32_t id);
extern void gic_cpuif_deactivate(unsigned int);
extern void gic_cpuif_setup(unsigned int);
extern void gic_pcpu_distif_setup(unsigned int);
extern void gic_setup(void);
extern uint32_t plat_interrupt_type_to_line(uint32_t type,
uint32_t security_state);
/* Declarations for plat_topology.c */
extern int plat_setup_topology(void);
extern int plat_get_max_afflvl(void);
extern unsigned int plat_get_aff_count(unsigned int, unsigned long);
extern unsigned int plat_get_aff_state(unsigned int, unsigned long);
/* Declarations for plat_io_storage.c */
extern void io_setup(void);
extern int plat_get_image_source(const char *image_name,
uintptr_t *dev_handle, uintptr_t *image_spec);
/* Declarations for plat_security.c */
extern void plat_security_setup(void);
/*
* Before calling this function BL2 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
* the entrypoint of BL2 and set SPSR and security state.
* On FVP we are only setting the security state, entrypoint
*/
extern void bl1_plat_set_bl2_ep_info(struct image_info *image,
struct entry_point_info *ep);
/*
* Before calling this function BL31 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
* the entrypoint of BL31 and set SPSR and security state.
* On FVP we are only setting the security state, entrypoint
*/
extern void bl2_plat_set_bl31_ep_info(struct image_info *image,
struct entry_point_info *ep);
/*
* Before calling this function BL32 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
* the entrypoint of BL32 and set SPSR and security state.
* On FVP we are only setting the security state, entrypoint
*/
extern void bl2_plat_set_bl32_ep_info(struct image_info *image,
struct entry_point_info *ep);
/*
* Before calling this function BL33 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
* the entrypoint of BL33 and set SPSR and security state.
* On FVP we are only setting the security state, entrypoint
*/
extern void bl2_plat_set_bl33_ep_info(struct image_info *image,
struct entry_point_info *ep);
/* Gets the memory layout for BL32 */
extern void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info);
/* Gets the memory layout for BL33 */
extern void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info);
/* Sets the entrypoint for BL32 */
extern void fvp_set_bl32_ep_info(struct entry_point_info *bl32_ep_info);
/* Sets the entrypoint for BL33 */
extern void fvp_set_bl33_ep_info(struct entry_point_info *bl33_ep_info);
#endif /*__ASSEMBLY__*/
#endif /* __PLATFORM_H__ */

33
plat/fvp/platform.mk
View File

@@ -51,40 +51,41 @@ PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011.c \
drivers/io/io_memmap.c \
drivers/io/io_semihosting.c \
lib/mmio.c \
lib/aarch64/sysreg_helpers.S \
lib/aarch64/sysreg_helpers.S \
lib/aarch64/xlat_tables.c \
lib/semihosting/semihosting.c \
lib/semihosting/aarch64/semihosting_call.S \
plat/fvp/plat_io_storage.c
plat/common/aarch64/plat_common.c \
plat/fvp/fvp_io_storage.c
BL1_SOURCES += drivers/arm/cci400/cci400.c \
plat/common/aarch64/platform_up_stack.S \
plat/fvp/bl1_plat_setup.c \
plat/fvp/aarch64/plat_common.c \
plat/fvp/aarch64/plat_helpers.S
plat/fvp/bl1_fvp_setup.c \
plat/fvp/aarch64/fvp_common.c \
plat/fvp/aarch64/fvp_helpers.S
BL2_SOURCES += drivers/arm/tzc400/tzc400.c \
plat/common/aarch64/platform_up_stack.S \
plat/fvp/bl2_plat_setup.c \
plat/fvp/plat_security.c \
plat/fvp/aarch64/plat_common.c
plat/fvp/bl2_fvp_setup.c \
plat/fvp/fvp_security.c \
plat/fvp/aarch64/fvp_common.c
BL31_SOURCES += drivers/arm/gic/gic_v2.c \
drivers/arm/gic/gic_v3.c \
drivers/arm/gic/aarch64/gic_v3_sysregs.S \
drivers/arm/cci400/cci400.c \
plat/common/aarch64/platform_mp_stack.S \
plat/fvp/bl31_plat_setup.c \
plat/fvp/plat_gic.c \
plat/fvp/plat_pm.c \
plat/fvp/plat_topology.c \
plat/fvp/aarch64/plat_helpers.S \
plat/fvp/aarch64/plat_common.c \
plat/fvp/bl31_fvp_setup.c \
plat/fvp/fvp_gic.c \
plat/fvp/fvp_pm.c \
plat/fvp/fvp_topology.c \
plat/fvp/aarch64/fvp_helpers.S \
plat/fvp/aarch64/fvp_common.c \
plat/fvp/drivers/pwrc/fvp_pwrc.c
ifeq (${RESET_TO_BL31}, 1)
BL31_SOURCES += drivers/arm/tzc400/tzc400.c \
plat/fvp/plat_security.c
BL31_SOURCES += drivers/arm/tzc400/tzc400.c \
plat/fvp/fvp_security.c
endif
# Flag used by the FVP port to determine the version of ARM GIC architecture

1
services/spd/tspd/tspd_common.c
View File

@@ -32,7 +32,6 @@
#include <assert.h>
#include <bl_common.h>
#include <context_mgmt.h>
#include <platform.h>
#include <string.h>
#include "tspd_private.h"

2
services/spd/tspd/tspd_main.c
View File

@@ -160,7 +160,7 @@ int32_t tspd_setup(void)
* absence is a critical failure. TODO: Add support to
* conditionally include the SPD service
*/
image_info = bl31_get_next_image_info(SECURE);
image_info = bl31_plat_get_next_image_ep_info(SECURE);
assert(image_info);
/*

1
services/spd/tspd/tspd_pm.c
View File

@@ -33,6 +33,7 @@
#include <bl_common.h>
#include <context_mgmt.h>
#include <debug.h>
#include <platform.h>
#include <tsp.h>
#include "tspd_private.h"

12
services/spd/tspd/tspd_private.h
View File

@@ -34,7 +34,7 @@
#include <arch.h>
#include <context.h>
#include <interrupt_mgmt.h>
#include <platform.h>
#include <platform_def.h>
#include <psci.h>
/*******************************************************************************
@@ -188,11 +188,11 @@ struct tsp_vectors;
/*******************************************************************************
* Function & Data prototypes
******************************************************************************/
extern uint64_t tspd_enter_sp(uint64_t *c_rt_ctx);
extern void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret);
extern uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx);
extern void __dead2 tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret);
extern int32_t tspd_init_secure_context(uint64_t entrypoint,
uint64_t tspd_enter_sp(uint64_t *c_rt_ctx);
void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret);
uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx);
void __dead2 tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret);
int32_t tspd_init_secure_context(uint64_t entrypoint,
uint32_t rw,
uint64_t mpidr,
tsp_context_t *tsp_ctx);

3
services/std_svc/psci/psci_afflvl_on.c
View File

@@ -34,6 +34,7 @@
#include <bl_common.h>
#include <bl31.h>
#include <context_mgmt.h>
#include <platform.h>
#include <runtime_svc.h>
#include <stddef.h>
#include "psci_private.h"
@@ -362,7 +363,7 @@ static unsigned int psci_afflvl0_on_finish(unsigned long mpidr,
/*
* Arch. management: Turn on mmu & restore architectural state
*/
enable_mmu_el3();
bl31_plat_enable_mmu();
/*
* All the platform specific actions for turning this cpu

17
services/std_svc/psci/psci_common.c
View File

@@ -35,6 +35,7 @@
#include <context.h>
#include <context_mgmt.h>
#include <debug.h>
#include <platform.h>
#include "psci_private.h"
/*
@@ -45,13 +46,11 @@ const spd_pm_ops_t *psci_spd_pm;
/*******************************************************************************
* Arrays that contains information needs to resume a cpu's execution when woken
* out of suspend or off states. 'psci_ns_einfo_idx' keeps track of the next
* free index in the 'psci_ns_entry_info' & 'psci_suspend_context' arrays. Each
* cpu is allocated a single entry in each array during startup.
* out of suspend or off states. Each cpu is allocated a single entry in each
* array during startup.
******************************************************************************/
suspend_context_t psci_suspend_context[PSCI_NUM_AFFS];
ns_entry_info_t psci_ns_entry_info[PSCI_NUM_AFFS];
unsigned int psci_ns_einfo_idx;
/*******************************************************************************
* Grand array that holds the platform's topology information for state
@@ -61,16 +60,6 @@ unsigned int psci_ns_einfo_idx;
aff_map_node_t psci_aff_map[PSCI_NUM_AFFS]
__attribute__ ((section("tzfw_coherent_mem")));
/*******************************************************************************
* In a system, a certain number of affinity instances are present at an
* affinity level. The cumulative number of instances across all levels are
* stored in 'psci_aff_map'. The topology tree has been flattenned into this
* array. To retrieve nodes, information about the extents of each affinity
* level i.e. start index and end index needs to be present. 'psci_aff_limits'
* stores this information.
******************************************************************************/
aff_limits_node_t psci_aff_limits[MPIDR_MAX_AFFLVL + 1];
/*******************************************************************************
* Pointer to functions exported by the platform to complete power mgmt. ops
******************************************************************************/

94
services/std_svc/psci/psci_private.h
View File

@@ -86,12 +86,8 @@ typedef unsigned int (*afflvl_power_on_finisher_t)(unsigned long,
******************************************************************************/
extern suspend_context_t psci_suspend_context[PSCI_NUM_AFFS];
extern ns_entry_info_t psci_ns_entry_info[PSCI_NUM_AFFS];
extern unsigned int psci_ns_einfo_idx;
extern aff_limits_node_t psci_aff_limits[MPIDR_MAX_AFFLVL + 1];
extern const plat_pm_ops_t *psci_plat_pm_ops;
extern aff_map_node_t psci_aff_map[PSCI_NUM_AFFS];
extern afflvl_power_on_finisher_t psci_afflvl_off_finish_handlers[];
extern afflvl_power_on_finisher_t psci_afflvl_sus_finish_handlers[];
/*******************************************************************************
* SPD's power management hooks registered with PSCI
@@ -102,59 +98,59 @@ extern const spd_pm_ops_t *psci_spd_pm;
* Function prototypes
******************************************************************************/
/* Private exported functions from psci_common.c */
extern int get_max_afflvl(void);
extern unsigned short psci_get_state(aff_map_node_t *node);
extern unsigned short psci_get_phys_state(aff_map_node_t *node);
extern void psci_set_state(aff_map_node_t *node, unsigned short state);
extern void psci_get_ns_entry_info(unsigned int index);
extern unsigned long mpidr_set_aff_inst(unsigned long, unsigned char, int);
extern int psci_validate_mpidr(unsigned long, int);
extern int get_power_on_target_afflvl(unsigned long mpidr);
extern void psci_afflvl_power_on_finish(unsigned long,
int,
int,
afflvl_power_on_finisher_t *);
extern int psci_set_ns_entry_info(unsigned int index,
unsigned long entrypoint,
unsigned long context_id);
extern int psci_check_afflvl_range(int start_afflvl, int end_afflvl);
extern void psci_acquire_afflvl_locks(unsigned long mpidr,
int start_afflvl,
int end_afflvl,
mpidr_aff_map_nodes_t mpidr_nodes);
extern void psci_release_afflvl_locks(unsigned long mpidr,
int start_afflvl,
int end_afflvl,
mpidr_aff_map_nodes_t mpidr_nodes);
int get_max_afflvl(void);
unsigned short psci_get_state(aff_map_node_t *node);
unsigned short psci_get_phys_state(aff_map_node_t *node);
void psci_set_state(aff_map_node_t *node, unsigned short state);
void psci_get_ns_entry_info(unsigned int index);
unsigned long mpidr_set_aff_inst(unsigned long, unsigned char, int);
int psci_validate_mpidr(unsigned long, int);
int get_power_on_target_afflvl(unsigned long mpidr);
void psci_afflvl_power_on_finish(unsigned long,
int,
int,
afflvl_power_on_finisher_t *);
int psci_set_ns_entry_info(unsigned int index,
unsigned long entrypoint,
unsigned long context_id);
int psci_check_afflvl_range(int start_afflvl, int end_afflvl);
void psci_acquire_afflvl_locks(unsigned long mpidr,
int start_afflvl,
int end_afflvl,
mpidr_aff_map_nodes_t mpidr_nodes);
void psci_release_afflvl_locks(unsigned long mpidr,
int start_afflvl,
int end_afflvl,
mpidr_aff_map_nodes_t mpidr_nodes);
/* Private exported functions from psci_setup.c */
extern int psci_get_aff_map_nodes(unsigned long mpidr,
int start_afflvl,
int end_afflvl,
mpidr_aff_map_nodes_t mpidr_nodes);
extern aff_map_node_t *psci_get_aff_map_node(unsigned long, int);
int psci_get_aff_map_nodes(unsigned long mpidr,
int start_afflvl,
int end_afflvl,
mpidr_aff_map_nodes_t mpidr_nodes);
aff_map_node_t *psci_get_aff_map_node(unsigned long, int);
/* Private exported functions from psci_affinity_on.c */
extern int psci_afflvl_on(unsigned long,
unsigned long,
unsigned long,
int,
int);
int psci_afflvl_on(unsigned long,
unsigned long,
unsigned long,
int,
int);
/* Private exported functions from psci_affinity_off.c */
extern int psci_afflvl_off(unsigned long, int, int);
int psci_afflvl_off(unsigned long, int, int);
/* Private exported functions from psci_affinity_suspend.c */
extern void psci_set_suspend_power_state(aff_map_node_t *node,
unsigned int power_state);
extern int psci_get_aff_map_node_suspend_afflvl(aff_map_node_t *node);
extern int psci_afflvl_suspend(unsigned long,
unsigned long,
unsigned long,
unsigned int,
int,
int);
extern unsigned int psci_afflvl_suspend_finish(unsigned long, int, int);
void psci_set_suspend_power_state(aff_map_node_t *node,
unsigned int power_state);
int psci_get_aff_map_node_suspend_afflvl(aff_map_node_t *node);
int psci_afflvl_suspend(unsigned long,
unsigned long,
unsigned long,
unsigned int,
int,
int);
unsigned int psci_afflvl_suspend_finish(unsigned long, int, int);
#endif /* __PSCI_PRIVATE_H__ */

16
services/std_svc/psci/psci_setup.c
View File

@@ -47,6 +47,22 @@
******************************************************************************/
static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT];
/*******************************************************************************
* In a system, a certain number of affinity instances are present at an
* affinity level. The cumulative number of instances across all levels are
* stored in 'psci_aff_map'. The topology tree has been flattenned into this
* array. To retrieve nodes, information about the extents of each affinity
* level i.e. start index and end index needs to be present. 'psci_aff_limits'
* stores this information.
******************************************************************************/
static aff_limits_node_t psci_aff_limits[MPIDR_MAX_AFFLVL + 1];
/*******************************************************************************
* 'psci_ns_einfo_idx' keeps track of the next free index in the
* 'psci_ns_entry_info' & 'psci_suspend_context' arrays.
******************************************************************************/
static unsigned int psci_ns_einfo_idx;
/*******************************************************************************
* Routines for retrieving the node corresponding to an affinity level instance
* in the mpidr. The first one uses binary search to find the node corresponding