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NVIC: Adjust priority setting

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Cortex-m0 we supports 2 bit priorities for the NVIC, yet we clear with 0x7 (3
bits). Change so we now clear with 0x3

Also limited priority to the max available (so we don't set extra bits we don't
want or modulus the priority, otherwise setting priority 8 will actual give you
priority 0) in both cortex-m and cortex-m0.

BUG=None, discovered while looking at the code
TEST=Should be no functional change, NVIC priorities should still work the same.
BRANCH=None

Change-Id: I31ba041449cae96983753b297e2631c310a406c4
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236086
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Alexandru M Stan
2014-12-16 14:47:32 -08:00
committed by chrome-internal-fetch
parent 3c0d9166cf
commit 3b101e56a9
2 changed files with 5 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
core/cortex-m/task.c
View File

@@ -453,6 +453,8 @@ static void __nvic_init_irqs(void)
uint8_t irq = __irqprio[i].irq;
uint8_t prio = __irqprio[i].priority;
uint32_t prio_shift = irq % 4 * 8 + 5;
if (prio > 0x7)
prio = 0x7;
CPU_NVIC_PRI(irq / 4) =
(CPU_NVIC_PRI(irq / 4) &
~(0x7 << prio_shift)) |

4
core/cortex-m0/task.c
View File

@@ -431,9 +431,11 @@ static void __nvic_init_irqs(void)
uint8_t irq = __irqprio[i].irq;
uint8_t prio = __irqprio[i].priority;
uint32_t prio_shift = irq % 4 * 8 + 6;
if (prio > 0x3)
prio = 0x3;
CPU_NVIC_PRI(irq / 4) =
(CPU_NVIC_PRI(irq / 4) &
~(0x7 << prio_shift)) |
~(0x3 << prio_shift)) |
(prio << prio_shift);
}
}