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Fix leaving SUSP_VR_EN enabled if S5 rails fail to come up

Browse Source 
We noticed this on a baytrail board, but the same problem exists in
haswell as well.  And while looking there, found that we skipped the
S5G3 state if the 5V rail failed to come up.

Fortunately, these are all rare corner cases; rails will always come
up on a good system.  So this only affects systems during bringup and
factory, not devices in the field.

BUG=chrome-os-partner:24915
BRANCH=rambi (and technically haswell, but may not be worth merging)
TEST=Try booting a system with a bad power rail; see that SUSP_VR_EN=0
     after the system fails to boot.

Change-Id: Ifd10841d298a0f2510a8b182250b717ea5643c99
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183733
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Randall Spangler
2014-01-23 15:41:10 -08:00
committed by chrome-internal-fetch
parent 2d39c66ee9
commit 44feb4b4e7
3 changed files with 9 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
board/samus/power_sequence.c
View File

@@ -210,6 +210,7 @@ enum power_state power_handle_state(enum power_state state)
while ((power_get_signals() & IN_PGOOD_PP5000) != 0) {
if (task_wait_event(SECOND) == TASK_EVENT_TIMER) {
CPRINTF("[%T timeout waiting for PP5000\n");
gpio_set_level(GPIO_PP5000_EN, 0);
chipset_force_shutdown();
return POWER_G3;
}
@@ -227,6 +228,9 @@ enum power_state power_handle_state(enum power_state state)
/* Wait for 1.05V to come up and CPU to notice */
if (power_wait_signals(IN_PGOOD_PP1050 |
IN_PCH_SLP_SUS_DEASSERTED)) {
gpio_set_level(GPIO_PP1050_EN, 0);
gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
gpio_set_level(GPIO_PP5000_EN, 0);
chipset_force_shutdown();
return POWER_G3;
}
@@ -243,6 +247,8 @@ enum power_state power_handle_state(enum power_state state)
gpio_set_level(GPIO_PP1800_EN, 1);
gpio_set_level(GPIO_PP1200_EN, 1);
if (power_wait_signals(IN_PGOOD_S3)) {
gpio_set_level(GPIO_PP1800_EN, 0);
gpio_set_level(GPIO_PP1200_EN, 0);
chipset_force_shutdown();
return POWER_S5;
}

1
power/baytrail.c
View File

@@ -190,6 +190,7 @@ enum power_state power_handle_state(enum power_state state)
gpio_set_level(GPIO_SUSP_VR_EN, 1);
if (power_wait_signals(IN_PGOOD_S5)) {
gpio_set_level(GPIO_SUSP_VR_EN, 0);
chipset_force_shutdown();
return POWER_G3;
}

3
power/haswell.c
View File

@@ -213,6 +213,7 @@ enum power_state power_handle_state(enum power_state state)
gpio_set_level(GPIO_SUSP_VR_EN, 1);
if (power_wait_signals(IN_PGOOD_PP1050)) {
gpio_set_level(GPIO_SUSP_VR_EN, 0);
chipset_force_shutdown();
return POWER_G3;
}
@@ -229,7 +230,7 @@ enum power_state power_handle_state(enum power_state state)
gpio_set_level(GPIO_PP5000_EN, 1);
if (power_wait_signals(IN_PGOOD_PP5000)) {
chipset_force_shutdown();
return POWER_G3;
return POWER_S5G3;
}
/* Wait for the always-on rails to be good */