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power: cannonlake: SLP_SUS_L deasserted == S5.

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When SLP_SUS_L is deasserted, that means the chipset is in S5.

BUG=None
BRANCH=None
TEST=Flash meowth; boot from AC only, verify that when SoC actually
boots the power state is reported as S0 instead of G3.

Change-Id: Ib9cd76aa9efd6f81df432205b8c1e8c342e32af6
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/837485
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Aseda Aboagye
2017-12-20 11:29:51 -08:00
committed by chrome-bot
parent 7c688c0f69
commit 4a7aceed59
1 changed files with 6 additions and 0 deletions
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6
power/cannonlake.c
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@@ -113,6 +113,12 @@ enum power_state power_handle_state(enum power_state state)
}
switch (state) {
case POWER_G3:
/* If SLP_SUS_L is deasserted, we're no longer in G3. */
if (power_has_signals(IN_PCH_SLP_SUS_DEASSERTED))
return POWER_S5;
break;
case POWER_G3S5:
/* Turn on the PP3300_DSW rail. */
gpio_set_level(GPIO_EN_PP3300_DSW, 1);