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CNL: Use SYS_RST_L for warm/cold chipset reset.

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The EC cannot control warm vs cold reset of the chipset using the
SYS_RST_L pin; it's just a reset request.  This commit changes the
behaviour of chipset_reset to assert SYS_RST_L regardless if a cold or a
warm reset is requested.

BUG=b:63508740
BRANCH=None
TEST=make -j buildall; Flash a modified image on npcx7_evb, verify that
no panics or asserts are hit.

Change-Id: Idfd6f556bf909c7df4e8bd50a79b60719478cde7
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/585573
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Aseda Aboagye
2017-07-25 11:33:15 -07:00
committed by chrome-bot
parent d483c289a9
commit 61a80d620a
2 changed files with 18 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
power/cannonlake.c
View File

@@ -53,26 +53,28 @@ void chipset_handle_espi_reset_assert(void)
void chipset_reset(int cold_reset)
{
CPRINTS("%s(%d)", __func__, cold_reset);
/*
* The EC cannot control warm vs cold reset of the chipset using
* SYS_RESET_L; it's more of a request.
*/
CPRINTS("%s()", __func__);
if (cold_reset) {
if (gpio_get_level(GPIO_SYS_RESET_L) == 0)
return;
gpio_set_level(GPIO_SYS_RESET_L, 0);
/* Debounce time for SYS_RESET_L is 16 ms */
udelay(20 * MSEC);
gpio_set_level(GPIO_SYS_RESET_L, 1);
} else {
/* Warm reset. */
/*
* TODO(aaboagye): something about platform reset?? But we
* don't have that...
*/
}
if (gpio_get_level(GPIO_SYS_RESET_L) == 0)
return;
/*
* Debounce time for SYS_RESET_L is 16 ms. Wait twice that period to be
* safe.
*/
gpio_set_level(GPIO_SYS_RESET_L, 0);
udelay(32 * MSEC);
gpio_set_level(GPIO_SYS_RESET_L, 1);
}
enum power_state chipset_force_g3(void)
{
chipset_force_shutdown();
CPRINTS("Faking G3. (NOOP for now.)");
/* TODO(aaboagye): Do the right thing for real. */
/* TODO(aaboagye): maybe turn off DSW load switch. */

3
power/cannonlake.h
View File

@@ -17,8 +17,7 @@
IN_PCH_SLP_S4_DEASSERTED | \
IN_PCH_SLP_SUS_DEASSERTED)
/* TODO(aaboagye): Should this be PMIC_DPWROK ? */
#define IN_PGOOD_ALL_CORE 0
#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_PMIC_DPWROK)
#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)