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stm32: configure OSC pins as GPIO

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For Lucas DVT, we are re-using the external oscillator pins as GPIO.
Set the special purpose mux and add them to the GPIO list.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BUG=None
TEST=run software on Lucas EVT board

Change-Id: I969c97ba4b56d7cce570f3fe5f17d44687020fe5
Reviewed-on: https://gerrit.chromium.org/gerrit/25393
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Vincent Palatin
2012-06-15 16:09:02 +00:00
committed by Gerrit
parent e14d961407
commit 661742dea9
3 changed files with 10 additions and 7 deletions
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5
board/snow/board.c
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@@ -49,8 +49,10 @@ const struct gpio_info gpio_list[GPIO_COUNT] = {
{"EN_PP5000", GPIO_A, (1<<11), GPIO_OUT_LOW, NULL},
{"EN_PP3300", GPIO_A, (1<<8), GPIO_OUT_LOW, NULL},
{"PMIC_PWRON_L",GPIO_A, (1<<12), GPIO_OUT_HIGH, NULL},
{"ENTERING_RW", GPIO_D, (1<<0), GPIO_OUT_LOW, NULL},
{"CHARGER_EN", GPIO_B, (1<<2), GPIO_OUT_LOW, NULL},
{"EC_INT", GPIO_B, (1<<9), GPIO_HI_Z, NULL},
{"CODEC_INT", GPIO_D, (1<<1), GPIO_HI_Z, NULL},
{"KB_OUT00", GPIO_B, (1<<0), GPIO_KB_OUTPUT, NULL},
{"KB_OUT01", GPIO_B, (1<<8), GPIO_KB_OUTPUT, NULL},
{"KB_OUT02", GPIO_B, (1<<12), GPIO_KB_OUTPUT, NULL},
@@ -80,6 +82,9 @@ void configure_board(void)
/* Enable SPI */
STM32_RCC_APB2ENR |= (1<<12);
/* remap OSC_IN/OSC_OUT to PD0/PD1 */
STM32_GPIO_AFIO_MAPR |= 1 << 15;
/* SPI1 on pins PA4-7 (alt. function push-pull, 10MHz) */
val = STM32_GPIO_CRL_OFF(GPIO_A) & ~0xffff0000;
val |= 0x99990000;

2
board/snow/board.h
View File

@@ -56,8 +56,10 @@ enum gpio_signal {
GPIO_EN_PP5000, /* 5.0v rail enable */
GPIO_EN_PP3300, /* 3.3v rail enable */
GPIO_PMIC_PWRON_L, /* 5v rail ready */
GPIO_EC_ENTERING_RW, /* EC is R/W mode for the kbc mux */
GPIO_CHARGER_EN,
GPIO_EC_INT,
GPIO_CODEC_INT, /* To audio codec (KB noise cancellation) */
GPIO_KB_OUT00,
GPIO_KB_OUT01,
GPIO_KB_OUT02,

10
chip/stm32/registers.h
View File

@@ -235,13 +235,9 @@
#define STM32_AFIO_BASE 0x40010000
#define STM32_AFIO_EXTICR(n) REG32(STM32_AFIO_BASE + 8 + 4 * (n))
#define STM32_GPIO_AFIO_EVCR_OFF(b) REG16((b) + 0x00)
#define STM32_GPIO_AFIO_MAPR_OFF(b) REG32((b) + 0x04)
#define STM32_GPIO_AFIO_EXTICR1(b) REG16((b) + 0x08)
#define STM32_GPIO_AFIO_EXTICR2(b) REG16((b) + 0x0c)
#define STM32_GPIO_AFIO_EXTICR3(b) REG16((b) + 0x10)
#define STM32_GPIO_AFIO_EXTICR4(b) REG16((b) + 0x14)
#define STM32_GPIO_AFIO_MAPR2(b) REG16((b) + 0x1c)
#define STM32_GPIO_AFIO_EVCR REG32(STM32_AFIO_BASE + 0x00)
#define STM32_GPIO_AFIO_MAPR REG32(STM32_AFIO_BASE + 0x04)
#define STM32_GPIO_AFIO_MAPR2 REG32(STM32_AFIO_BASE + 0x1c)
#else
#error Unsupported chip variant