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stm32/spi: Reset peripheral after every packet

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RX DMA seems to get misaligned sometimes yielding to extra bytes before the
first byte on the wire.
in_msg=[00 00 00 03 f4 09 00 00 ...]
                ^ real first byte

To fix this we want to reset and reinit the SPI peripheral after every packet,
in the same place where setup_for_transaction() is called.

This bug applies to the STM32F0 line but resetting the peripheral on other STM32
ECs should not break anything.

BUG=chrome-os-partner:31390
TEST=On STM32F0:
ap# cd /sys/class/power_supply/sbs-20-000b/; while true; do grep "" * >/dev/null 2>&1; done
You should not see "SPI rx bad data" with in_msg packets that have extra bytes
in the beggining. Wait though, it might take up to a few minutes for stuff to
break.
BRANCH=None

Change-Id: If9ab93c5c9040a2c7bda33d7cc990603f1121f3f
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217527
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit is contained in:
Alexandru M Stan
2014-09-10 14:23:05 -07:00
committed by chrome-internal-fetch
parent 5e7c09ed3e
commit 68704fea5f
1 changed files with 11 additions and 2 deletions
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13
chip/stm32/spi.c
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@@ -318,6 +318,8 @@ static void setup_for_transaction(void)
tx_status(EC_SPI_OLD_READY);
}
/* Forward declaraction */
static void spi_init(void);
/*
* If a setup_for_transaction() was postponed, call it now.
@@ -326,7 +328,7 @@ static void setup_for_transaction(void)
static void check_setup_transaction_later(void)
{
if (setup_transaction_later) {
setup_for_transaction();
spi_init(); /* Fix for bug chrome-os-partner:31390 */
/*
* 'state' is set to SPI_STATE_READY_TO_RX. Somehow AP
* de-asserted the SPI NSS during the handler was running.
@@ -449,7 +451,7 @@ void spi_event(enum gpio_signal signal)
}
/* Set up for the next transaction */
setup_for_transaction();
spi_init(); /* Fix for bug chrome-os-partner:31390 */
return;
}
@@ -613,6 +615,13 @@ static void spi_init(void)
{
stm32_spi_regs_t *spi = STM32_SPI1_REGS;
/* Reset the SPI Peripheral to clear any existing weird states. */
/* Fix for bug chrome-os-partner:31390 */
enabled = 0;
state = SPI_STATE_DISABLED;
STM32_RCC_APB2RSTR |= (1 << 12);
STM32_RCC_APB2RSTR &= ~(1 << 12);
/* 40 MHz pin speed */
STM32_GPIO_OSPEEDR(GPIO_A) |= 0xff00;