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Merge pull request #157 from Telecominfraproject/clang_format_linter

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Clang format linter, closes #169
This commit is contained in:
mdlewisfb
2018-11-07 07:59:37 -08:00
committed by GitHub
parent abf58069ad 116d1b723a
commit 70db458f90
208 changed files with 8859 additions and 8664 deletions
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109
firmware/ec/.clang-format Normal file
View File

@@ -0,0 +1,109 @@
# clang-format configuration file. Intended for clang-format >= 4.
#
# Modified from linux kernel .clang-format file.
#
# For more information, see:
#
# Documentation/process/clang-format.rst
# https://clang.llvm.org/docs/ClangFormat.html
# https://clang.llvm.org/docs/ClangFormatStyleOptions.html
#
---
AccessModifierOffset: -4
AlignAfterOpenBracket: Align
AlignConsecutiveAssignments: false
AlignConsecutiveDeclarations: false
AlignEscapedNewlinesLeft: true
AlignOperands: true
AlignTrailingComments: true
AllowAllParametersOfDeclarationOnNextLine: false
AllowShortBlocksOnASingleLine: false
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: None
AllowShortIfStatementsOnASingleLine: false
AllowShortLoopsOnASingleLine: false
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: false
AlwaysBreakTemplateDeclarations: false
BinPackArguments: true
BinPackParameters: true
BraceWrapping:
AfterClass: false
AfterControlStatement: false
AfterEnum: false
AfterFunction: true
AfterNamespace: true
AfterObjCDeclaration: false
AfterStruct: false
AfterUnion: false
#AfterExternBlock: false # Unknown to clang-format-5.0
BeforeCatch: false
BeforeElse: false
IndentBraces: false
BreakBeforeBinaryOperators: None
BreakBeforeBraces: Custom
BreakBeforeTernaryOperators: false
BreakConstructorInitializersBeforeComma: false
BreakAfterJavaFieldAnnotations: false
BreakStringLiterals: false
ColumnLimit: 80
CommentPragmas: '^ IWYU pragma:'
ConstructorInitializerAllOnOneLineOrOnePerLine: false
ConstructorInitializerIndentWidth: 4
ContinuationIndentWidth: 4
Cpp11BracedListStyle: false
DerivePointerAlignment: false
DisableFormat: false
ExperimentalAutoDetectBinPacking: false
# Taken from:
# git grep -h '^#define [^[:space:]]*for_each[^[:space:]]*(' include/ \
# | sed "s,^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$, - '\1'," \
# | sort | uniq
#ForEachMacros: #None match yet
IncludeCategories:
- Regex: '^<.*'
Priority: 1
- Regex: '^<.*\.h>'
Priority: 1
- Regex: '"ti.*'
Priority: 3
- Regex: '"inc/*'
Priority: 4
IncludeIsMainRegex: '(Test)?$'
IndentCaseLabels: true
IndentPPDirectives: AfterHash
IndentWidth: 4
IndentWrappedFunctionNames: false
JavaScriptQuotes: Leave
JavaScriptWrapImports: true
KeepEmptyLinesAtTheStartOfBlocks: false
MacroBlockBegin: ''
MacroBlockEnd: ''
MaxEmptyLinesToKeep: 1
NamespaceIndentation: Inner
#ObjCBinPackProtocolList: Auto # Unknown to clang-format-5.0
ObjCBlockIndentWidth: 4
ObjCSpaceAfterProperty: true
ObjCSpaceBeforeProtocolList: true
PointerAlignment: Right
ReflowComments: true
SortIncludes: false
SpaceAfterCStyleCast: false
SpaceAfterTemplateKeyword: true
SpaceBeforeAssignmentOperators: true
SpaceBeforeParens: ControlStatements
SpaceInEmptyParentheses: false
SpacesBeforeTrailingComments: 1
SpacesInAngles: false
SpacesInContainerLiterals: false
SpacesInCStyleCastParentheses: false
SpacesInParentheses: false
SpacesInSquareBrackets: false
Standard: Cpp03
TabWidth: 4
UseTab: Never
...

8
firmware/ec/Makefile
View File

@@ -78,6 +78,11 @@ LLIBS += -Wl,--end-group
.PRECIOUS: $(OUT)%/compiler.opt $(OUT)%/linker.cmd
OBJCOPY = $(TOOLCHAIN)/bin/arm-none-eabi-objcopy
ALL_FILE = $(shell find . -name '*.c' -o -name '*.h')
LINT = clang-format
LINT_FLAGS = -i -style=file -fallback-style=none
.PRECIOUS: %/compiler.opt %/linker.cmd
all: oc_connect1
oc_connect1: $(OUT)/OpenCellular.bin
@@ -95,6 +100,9 @@ $(OUT)/OpenCellular.out: $(OUT)/$(CONFIG)/linker.cmd $(MAIN_OBJS)
$(OUT)/OpenCellular.bin: $(OUT)/OpenCellular.out
$(OBJCOPY) -S -O binary $< $@
lint:
$(LINT) $(LINT_FLAGS) $(ALL_FILE)
clean:
-rm -rf *.o *.out *.d *.rov.xs $(OUT) $(MAIN_OBJS) $(COVERAGE_OBJS)

84
firmware/ec/common/inc/global/Framework.h
View File

@@ -16,19 +16,21 @@
#include <stdbool.h>
#include <stdlib.h>
#define POST_ENABLED 0
#define POST_DISABLED 1
#define POST_ENABLED 0
#define POST_DISABLED 1
/* For enabling schema sharing between host and firmware we need to import the
* factory config and driver config to schema.c as weak attribute from
* OC_CONNECT1.C. This helps host compilation as it doesn't need to know symbol definition for the configs
* and schema sharing can be achived with limited common files.
* OC_CONNECT1.C. This helps host compilation as it doesn't need to know symbol
* definition for the configs and schema sharing can be achived with limited
* common files.
*/
#define SCHEMA_IMPORT extern __attribute__((weak))
/* DriverStruct acts as a generic datatype.
* In schema we are more intreseted in the address of structure so we use this datatype DriverStruct
* to avoid the include header for the devices in the system.
* In schema we are more intreseted in the address of structure so we use this
* datatype DriverStruct to avoid the include header for the devices in the
* system.
*/
typedef char DriverStruct;
@@ -63,7 +65,7 @@ typedef struct Parameter {
};
} Parameter;
typedef bool (*CB_Command) (void *driver, void *params);
typedef bool (*CB_Command)(void *driver, void *params);
typedef struct Command {
const char *name;
@@ -71,37 +73,38 @@ typedef struct Command {
const CB_Command cb_cmd;
} Command;
typedef bool (*CB_POST) (void **params);
typedef bool (*CB_POST)(void **params);
typedef struct Post {
const char *name;
const CB_POST cb_postCmd;
}Post;
} Post;
// To avoid the awkward situation of not knowing how much to allocate for the return value (think
// string returns), we instead rely on the 'get' and 'set' functions to allocate and return a
// pointer to the value it wants to return via OCMP
typedef bool (*StatusGet_Cb) (void *driver, unsigned int param_id,
void *return_buf);
typedef bool (*ConfigGet_Cb) (void *driver, unsigned int param_id,
void *return_buf);
typedef bool (*ConfigSet_Cb) (void *driver, unsigned int param_id,
const void *data);
// To avoid the awkward situation of not knowing how much to allocate for the
// return value (think string returns), we instead rely on the 'get' and 'set'
// functions to allocate and return a pointer to the value it wants to return
// via OCMP
typedef bool (*StatusGet_Cb)(void *driver, unsigned int param_id,
void *return_buf);
typedef bool (*ConfigGet_Cb)(void *driver, unsigned int param_id,
void *return_buf);
typedef bool (*ConfigSet_Cb)(void *driver, unsigned int param_id,
const void *data);
typedef ePostCode (*CB_Probe) (void *driver, POSTData* postData);
typedef ePostCode (*CB_Init) (void *driver, const void *config,
const void *alert_token);
typedef ePostCode (*CB_Probe)(void *driver, POSTData *postData);
typedef ePostCode (*CB_Init)(void *driver, const void *config,
const void *alert_token);
typedef bool (*ssHook_Cb) (void *driver, void *return_buf);
typedef bool (*ssHook_Cb)(void *driver, void *return_buf);
typedef struct Driver_fxnTable {
// TODO: These callbacks are a bit rough. They'll get the job done, but we should revisit other
// options (per-parameter callbacks for example)
StatusGet_Cb cb_get_status;
ConfigGet_Cb cb_get_config;
ConfigSet_Cb cb_set_config;
CB_Probe cb_probe;
CB_Init cb_init;
// TODO: These callbacks are a bit rough. They'll get the job done, but we
// should revisit other options (per-parameter callbacks for example)
StatusGet_Cb cb_get_status;
ConfigGet_Cb cb_get_config;
ConfigSet_Cb cb_set_config;
CB_Probe cb_probe;
CB_Init cb_init;
} Driver_fxnTable;
typedef struct Driver {
@@ -111,29 +114,31 @@ typedef struct Driver {
const Parameter *alerts;
const Parameter *argList;
const Command *commands;
const Driver_fxnTable* fxnTable;
const Driver_fxnTable *fxnTable;
const Post *post;
bool payload_fmt_union; /* TODO: hack to account for OBC/Testmodule payload
being packed as a union instead of a struct */
} Driver;
typedef struct SSHookSet {
ssHook_Cb preInitFxn ;/* Function will run before post is executed */
ssHook_Cb postInitFxn; /* Function will run after post is executed */
}SSHookSet;
ssHook_Cb preInitFxn; /* Function will run before post is executed */
ssHook_Cb postInitFxn; /* Function will run after post is executed */
} SSHookSet;
typedef void (*Component_InitCb) (void);
typedef void (*Component_InitCb)(void);
typedef struct Component {
const char *name;
const struct Component *components;
const Driver *driver;
void *driver_cfg; // TODO: this could be turned into a standard polymorphism struct to hold the
// driver, hw config & driver object data (like we did for GPIO)
void *driver_cfg; // TODO: this could be turned into a standard polymorphism
// struct to hold the driver, hw config & driver object data (like we did
// for GPIO)
const void *factory_config; /* Factory defaults for the device */
const Command *commands; /* TODO: super gross hack to fit into current CLI */
const Command
*commands; /* TODO: super gross hack to fit into current CLI */
const SSHookSet *ssHookSet;
bool postDisabled; //Flag for POST execution.
bool postDisabled; // Flag for POST execution.
void *ss;
} Component;
@@ -144,8 +149,7 @@ typedef struct AlertData {
uint8_t deviceId;
} AlertData;
void OCMP_GenerateAlert(const AlertData *alert_data,
unsigned int alert_id,
void OCMP_GenerateAlert(const AlertData *alert_data, unsigned int alert_id,
const void *data);
#endif /* _SYS_CFG_FRAMEWORK_H */

107
firmware/ec/common/inc/global/OC_CONNECT1.h
View File

@@ -13,41 +13,44 @@
extern "C" {
#endif
#define OC_PMIC_ENABLE (1)
#define OC_PMIC_DISABLE (0)
#define OC_SDR_ENABLE (1)
#define OC_SDR_DISABLE (0)
#define OC_SDR_FE_IO_ENABLE (1)
#define OC_SDR_FE_IO_DISABLE (0)
#define OC_FE_ENABLE (1)
#define OC_FE_DISABLE (0)
#define OC_PWR_LION_BATT (1)
#define OC_PWR_LEAD_BATT (0)
#define OC_PWR_PSE_RESET_STATE (1)
#define OC_PWR_PSE_ON_STATE (0)
#define OC_GBC_PROC_ENABLE (1)
#define OC_GBC_PROC_RESET (0)
#define OC_SYNC_IOEXP_ENABLE (1)
#define OC_SYNC_IOEXP_RESET (0)
#define OC_HCI_LED_ENABLE (1)
#define OC_HCI_LED_DISABLE (0)
#define OC_ETH_SW_ENABLE (1)
#define OC_ETH_SW_DISABLE (0)
#define CAT24C256 { .page_size = 64, .mem_size = (256 / 8) }
#define OC_PMIC_ENABLE (1)
#define OC_PMIC_DISABLE (0)
#define OC_SDR_ENABLE (1)
#define OC_SDR_DISABLE (0)
#define OC_SDR_FE_IO_ENABLE (1)
#define OC_SDR_FE_IO_DISABLE (0)
#define OC_FE_ENABLE (1)
#define OC_FE_DISABLE (0)
#define OC_PWR_LION_BATT (1)
#define OC_PWR_LEAD_BATT (0)
#define OC_PWR_PSE_RESET_STATE (1)
#define OC_PWR_PSE_ON_STATE (0)
#define OC_GBC_PROC_ENABLE (1)
#define OC_GBC_PROC_RESET (0)
#define OC_SYNC_IOEXP_ENABLE (1)
#define OC_SYNC_IOEXP_RESET (0)
#define OC_HCI_LED_ENABLE (1)
#define OC_HCI_LED_DISABLE (0)
#define OC_ETH_SW_ENABLE (1)
#define OC_ETH_SW_DISABLE (0)
#define CAT24C256 \
{ \
.page_size = 64, .mem_size = (256 / 8) \
}
/* GBC IO expander Slave address */
#define BIGBROTHER_IOEXP0_ADDRESS 0x71
#define BIGBROTHER_IOEXP1_ADDRESS 0x70
#define BIGBROTHER_IOEXP0_ADDRESS 0x71
#define BIGBROTHER_IOEXP1_ADDRESS 0x70
/* SYNC IO expander Slave address */
#define SYNC_IO_DEVICE_ADDR 0x71
#define SYNC_IO_DEVICE_ADDR 0x71
/* SDR IO expander Slave address */
#define SDR_FX3_IOEXP_ADDRESS 0x1E
#define SDR_FX3_IOEXP_ADDRESS 0x1E
/* RFFE IO expander Slave address */
#define RFFE_CHANNEL1_IO_TX_ATTEN_ADDR 0x18
#define RFFE_CHANNEL1_IO_RX_ATTEN_ADDR 0x1A
#define RFFE_CHANNEL2_IO_TX_ATTEN_ADDR 0x1C
#define RFFE_CHANNEL2_IO_RX_ATTEN_ADDR 0x1D
#define RFFE_IO_REVPOWER_ALERT_ADDR 0x1B
#define RFFE_CHANNEL1_IO_TX_ATTEN_ADDR 0x18
#define RFFE_CHANNEL1_IO_RX_ATTEN_ADDR 0x1A
#define RFFE_CHANNEL2_IO_TX_ATTEN_ADDR 0x1C
#define RFFE_CHANNEL2_IO_RX_ATTEN_ADDR 0x1D
#define RFFE_IO_REVPOWER_ALERT_ADDR 0x1B
/*!
* @def OC_CONNECT1_EMACName
@@ -79,10 +82,10 @@ typedef enum OC_EC_PORTGroupName {
PN,
PP,
PQ
}OC_EC_PORTGroupName;
} OC_EC_PORTGroupName;
typedef enum OC_CONNECT1_GPIOName {
//PA
// PA
OC_EC_DEBUG_UART_RX = 0,
OC_EC_DEBUG_UART_TX,
OC_EC_PSE_I2C6_SCLK,
@@ -91,12 +94,12 @@ typedef enum OC_CONNECT1_GPIOName {
OC_EC_SOC_UART3_TX,
OC_EC_PWRMNTR_I2C6_SCLK,
OC_EC_PWRMNTR_I2C6_SDA,
//PB
// PB
OC_EC_LT4015_I2C0_SCLK = 8,
OC_EC_LT40515I2C0_SDA,
OC_EC_FLASH_nCS,
OC_EC_FLASH_CLK,
//PC
// PC
OC_EC_JTAG_TCK = 16,
OC_EC_JTAG_TMS,
OC_EC_JTAG_TDI,
@@ -105,7 +108,7 @@ typedef enum OC_CONNECT1_GPIOName {
OC_EC_SYNCCONN_UART_TX,
OC_EC_ETHSW_MDC,
OC_EC_ETHSW_MDIO,
//PD
// PD
OC_EC_SYNCCONN_I2C7_SCLK = 24,
OC_EC_SYNCCONN_I2C7_SDA,
OC_EC_SDR_INA_ALERT,
@@ -114,31 +117,31 @@ typedef enum OC_CONNECT1_GPIOName {
OC_NOC_2,
OC_EC_PWR_PRSNT_SOLAR_AUX,
OC_EC_SYNC_IOEXP_ALERT,
//PE
// PE
OC_EC_GBC_IOEXP71_ALERT = 32,
OC_EC_FE_CONTROL,//OC_CONNECT1_GBC_TEMP_ALERT2,
OC_EC_FE_CONTROL, // OC_CONNECT1_GBC_TEMP_ALERT2,
OC_EC_AP_GPIO1,
OC_EC_GPP_AP_BM_1,
OC_EC_FLASH_MOSI,
OC_EC_FLASH_MISO,
//PF
// PF
OC_EC_JTAG_TRD2 = 40,
OC_EC_JTAG_TRD1,
OC_EC_JTAG_TRD0,
OC_EC_JTAG_TRCLK,
OC_EC_JTAG_TRD3,
//PG
// PG
OC_EC_TEMPSEN_I2C1_SCLK = 48,
OC_EC_TEMPSEN_I2C1_SDA,
//PH
// PH
OC_EC_GPP_PMIC_CORE_PWR = 56,
OC_EC_GPP_SOC_PLTRST, //OC_CONNECT1_PLT_RST_STATUS,//OC_GPP_SOC_PLTRST,OC_CONNECT1_PLT_RST_STATUS
OC_EC_GPP_SOC_PLTRST, // OC_CONNECT1_PLT_RST_STATUS,//OC_GPP_SOC_PLTRST,OC_CONNECT1_PLT_RST_STATUS
OC_EC_GPP_PMIC_CTRL,
OC_EC_GBC_INA_ALERT,
//PJ
// PJ
OC_EC_PWR_PD_NT2P = 64,
OC_EC_GBC_AP_INA_ALERT,
//PK
// PK
OC_EC_UART4_RXD = 72,
OC_EC_UART4_CTS,
OC_EC_UART4_RTS,
@@ -147,7 +150,7 @@ typedef enum OC_CONNECT1_GPIOName {
OC_EC_TRXFECONN_I2C3_SDA,
OC_EC_TRXFECONN_I2C4_SCLK,
OC_EC_TRXFECONN_I2C4_SDA,
//PL
// PL
OC_EC_TRXFECONN_I2C2_SCLK = 80,
OC_EC_TRXFECONN_I2C2_SDA,
OC_EC_GBC_PSE_ALERT,
@@ -156,7 +159,7 @@ typedef enum OC_CONNECT1_GPIOName {
OC_EC_PWR_PRSNT_POE,
OC_EC_USB_DP3,
OC_EC_USB_DN3,
//PM
// PM
OC_EC_PWR_LION_ALERT = 88,
OC_EC_HCI_LED_RESET,
OC_EC_PWR_MPPT_LION,
@@ -165,21 +168,22 @@ typedef enum OC_CONNECT1_GPIOName {
OC_EC_ETH_SW_RESET,
OC_EC_GBC_IOEXP70_INT,
OC_EC_PWR_BATT_SELECT,
//PN
// PN
OC_EC_PD_PWRGD_ALERT = 96,
OC_EC_SDR_FPGA_TEMP_INA_ALERT,
OC_EC_SDR_DEVICE_CONTROL,
OC_EC_SDR_PWR_GD,
OC_EC_FE_PWR_GD,
OC_EC_MODULE_UART1_RIN,
//PP
OC_EC_SDR_FE_IO_RESET_CTRL = 104,//OC_EC_MPPT_LACID = 104, //OC_SDR_FE_IO_RESET_CTRL
// PP
OC_EC_SDR_FE_IO_RESET_CTRL =
104, // OC_EC_MPPT_LACID = 104, //OC_SDR_FE_IO_RESET_CTRL
OC_EC_FE_RESET_OUT,
OC_EC_SDR_PWR_CNTRL,
OC_EC_GPP_PWRGD_PROTECTION,
OC_EC_RFFE_RESET,
OC_EC_GBC_DEBUG,
//PQ
// PQ
OC_EC_FE_TRXFE_CONN_RESET = 112,
OC_EC_GPP_MSATA_DAS,
OC_EC_POE_OVERRIDE,
@@ -209,11 +213,10 @@ typedef enum OC_CONNECT1_I2CName {
* @brief Enum of SPI names on the DK_TM4C129X dev board
*/
typedef enum DK_TM4C129X_SPIName {
OC_CONNECT1_SPI0 = 0,
OC_CONNECT1_SPICOUNT
OC_CONNECT1_SPI0 = 0,
OC_CONNECT1_SPICOUNT
} OC_CONNECT1_SPIName;
/*!
* @def OC_CONNECT1_debugMdioName
* @brief Enum of debug MDIO names for Ethernet components

79
firmware/ec/common/inc/global/ocmp_frame.h
View File

@@ -18,18 +18,19 @@
* MACRO DEFINITIONS
*****************************************************************************/
/* Start Of Frame & Message Lengths */
#define OCMP_MSG_SOF 0x55
#define OCMP_FRAME_TOTAL_LENGTH 64
#define OCMP_MSG_SOF 0x55
#define OCMP_FRAME_TOTAL_LENGTH 64
#define OCMP_FRAME_HEADER_LENGTH 17
#define OCMP_FRAME_MSG_LENGTH (OCMP_FRAME_TOTAL_LENGTH - OCMP_FRAME_HEADER_LENGTH)
#define OCMP_FRAME_MSG_LENGTH \
(OCMP_FRAME_TOTAL_LENGTH - OCMP_FRAME_HEADER_LENGTH)
/*****************************************************************************
* STRUCT/ENUM DEFINITIONS
*****************************************************************************/
typedef enum {
OC_SS_BB = -1, //Hack around the fact that IPC reuses OCMP to allow us
// to split BB (internal) and SYS (CLI) message handling
OC_SS_BB = -1, // Hack around the fact that IPC reuses OCMP to allow us
// to split BB (internal) and SYS (CLI) message handling
OC_SS_SYS = 0,
OC_SS_PWR,
OC_SS_BMS,
@@ -42,28 +43,32 @@ typedef enum {
OC_SS_SYNC,
OC_SS_TEST_MODULE,
OC_SS_DEBUG,
OC_SS_MAX_LIMIT,//TODO:REV C Change
OC_SS_MAX_LIMIT, // TODO:REV C Change
OC_SS_WD
//OC_SS_ALERT_MNGR,
//OC_SS_MAX_LIMIT
// OC_SS_ALERT_MNGR,
// OC_SS_MAX_LIMIT
} OCMPSubsystem;
typedef enum {
OCMP_COMM_IFACE_UART = 1, // Uart - 1
OCMP_COMM_IFACE_ETHERNET, // Ethernet - 2
OCMP_COMM_IFACE_SBD, // SBD(Satellite) - 3
OCMP_COMM_IFACE_USB // Usb - 4
OCMP_COMM_IFACE_UART = 1, // Uart - 1
OCMP_COMM_IFACE_ETHERNET, // Ethernet - 2
OCMP_COMM_IFACE_SBD, // SBD(Satellite) - 3
OCMP_COMM_IFACE_USB // Usb - 4
} OCMPInterface;
/*
* OCMPMsgType - msg type specifies what is the communication all about.
* It can be Configuration, Status, Alert, Command, Watchdog, Debug
* OCMPMsgType 1 byte message.
* |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
* || 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 ||
* |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|| Message Type ||
* |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
*
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
* || 7 || 6 || 5 || 4 || 3 ||
2 || 1 || 0 ||
*
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|| Message Type ||
*
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
*/
typedef enum {
OCMP_MSG_TYPE_CONFIG = 1,
@@ -122,29 +127,26 @@ typedef enum {
* communication with EC from External entity (e.g. AP over UART, Ethernet
* or SBD)
*/
typedef enum {
OCMP_DEBUG_READ = 1,
OCMP_DEBUG_WRITE
} eOCMPDebugOperation;
typedef enum { OCMP_DEBUG_READ = 1, OCMP_DEBUG_WRITE } eOCMPDebugOperation;
/* TODO::This OCWARE_HOST has to be removed with OCMP cleanUp*/
#ifndef OCWARE_HOST
#define OC_SS OCMPSubsystem
#define OC_MSG_TYP OCMPMsgType
#define OC_AXN_TYP OCMPActionType
# define OC_SS OCMPSubsystem
# define OC_MSG_TYP OCMPMsgType
# define OC_AXN_TYP OCMPActionType
#else
#define OC_SS uint8_t
#define OC_MSG_TYP uint8_t
#define OC_AXN_TYP uint8_t
#define OC_IFACE_TYP uint8_t
# define OC_SS uint8_t
# define OC_MSG_TYP uint8_t
# define OC_AXN_TYP uint8_t
# define OC_IFACE_TYP uint8_t
#endif
/*
* Header is the field which will be containing SOF, Framelen,
* Source Interface, Sequence number, and timestamp.
*/
typedef struct __attribute__((packed, aligned(1))) {
uint8_t ocmpSof; // SOF - It must be 0x55
uint8_t ocmpFrameLen; // Framelen - tells about the configuration size ONLY.
typedef struct __attribute__((packed, aligned(1))) {
uint8_t ocmpSof; // SOF - It must be 0x55
uint8_t ocmpFrameLen; // Framelen - tells about the configuration size ONLY.
OCMPInterface ocmpInterface; // Interface - UART/Ethernet/SBD
uint32_t ocmpSeqNumber; // SeqNo - Don't know!!!
uint32_t ocmpTimestamp; // Timestamp - When AP sent the command?
@@ -154,15 +156,16 @@ typedef struct __attribute__((packed, aligned(1))) {
* This is the Message structure for Subsystem level information
*/
typedef struct __attribute__((packed, aligned(1))) {
OC_SS subsystem; // RF/GPP/BMS/Watchdog etc..
uint8_t componentID; // Compononent ID. Different for different subsystem.
OCMPMsgType msgtype; // Msg type is Config/Status/Alert/Command/Watchdog/Debug
uint8_t action; // Action is - Get/Set/Reply.
uint16_t parameters; // List of Parameters to be set or get.
OC_SS subsystem; // RF/GPP/BMS/Watchdog etc..
uint8_t componentID; // Compononent ID. Different for different subsystem.
OCMPMsgType
msgtype; // Msg type is Config/Status/Alert/Command/Watchdog/Debug
uint8_t action; // Action is - Get/Set/Reply.
uint16_t parameters; // List of Parameters to be set or get.
#ifndef OCWARE_HOST
uint8_t ocmp_data[]; // The data payload.
uint8_t ocmp_data[]; // The data payload.
#else
int8_t* info;
int8_t *info;
#endif
} OCMPMessage;

6
firmware/ec/common/inc/global/post_frame.h
View File

@@ -41,9 +41,9 @@ typedef struct __attribute__((packed, aligned(1))) {
} POSTData;
/*****************************************************************************
* FUNCTION PROTOTYPES
* FUNCTION PROTOTYPES
*****************************************************************************/
void post_update_POSTData(POSTData *pData, uint8_t I2CBus, uint8_t devAddress,
uint16_t manId, uint16_t devId);
void post_update_POSTData(POSTData *pData, uint8_t I2CBus, uint8_t devAddress,
uint16_t manId, uint16_t devId);
#endif /* POST_FRAME_H_ */

44
firmware/ec/common/inc/ocmp_wrappers/ocmp_adt7481.h
View File

@@ -1,11 +1,11 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
#ifndef _OCMP_ADT7481_H
#define _OCMP_ADT7481_H
@@ -21,29 +21,23 @@ typedef union ADT7481_Config {
} ADT7481_Config;
#ifdef UT_FRAMEWORK
extern const Driver_fxnTable ADT7481_fxnTable;
extern const Driver_fxnTable ADT7481_fxnTable;
#else
SCHEMA_IMPORT const Driver_fxnTable ADT7481_fxnTable;
SCHEMA_IMPORT const Driver_fxnTable ADT7481_fxnTable;
#endif
static const Driver ADT7481 = {
.name = "ADT7481",
.status = (Parameter[]){
{ .name = "temperature", .type = TYPE_UINT8 },
{}
},
.config = (Parameter[]){
{ .name = "lowlimit", .type = TYPE_INT8 },
{ .name = "highlimit", .type = TYPE_UINT8 },
{ .name = "critlimit", .type = TYPE_UINT8 },
{}
},
.alerts = (Parameter[]){
{ .name = "BAW", .type = TYPE_UINT8 },
{ .name = "AAW", .type = TYPE_UINT8 },
{ .name = "ACW", .type = TYPE_UINT8 },
{}
},
.status =
(Parameter[]){ { .name = "temperature", .type = TYPE_UINT8 }, {} },
.config = (Parameter[]){ { .name = "lowlimit", .type = TYPE_INT8 },
{ .name = "highlimit", .type = TYPE_UINT8 },
{ .name = "critlimit", .type = TYPE_UINT8 },
{} },
.alerts = (Parameter[]){ { .name = "BAW", .type = TYPE_UINT8 },
{ .name = "AAW", .type = TYPE_UINT8 },
{ .name = "ACW", .type = TYPE_UINT8 },
{} },
.fxnTable = &ADT7481_fxnTable,
};

24
firmware/ec/common/inc/ocmp_wrappers/ocmp_at45db.h
View File

@@ -1,19 +1,19 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
#ifndef COMMON_INC_OCMP_WRAPPERS_OCMP_FLASH_H_
#define COMMON_INC_OCMP_WRAPPERS_OCMP_FLASH_H_
#define FRAME_SIZE 64
#define LAST_MSG_FLAG 0
#define NEXT_MSG_FLAG_POS 17
#define NEXT_MSG_FLAG 1
#define PAYLOAD_SIZE 47
#define FRAME_SIZE 64
#define LAST_MSG_FLAG 0
#define NEXT_MSG_FLAG_POS 17
#define NEXT_MSG_FLAG 1
#define PAYLOAD_SIZE 47
#endif /* COMMON_INC_OCMP_WRAPPERS_OCMP_FLASH_H_ */

19
firmware/ec/common/inc/ocmp_wrappers/ocmp_dat-xxr5a-pp.h
View File

@@ -1,11 +1,11 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
#ifndef _OCMP_DATXXR5APP_H
#define _OCMP_DATXXR5APP_H
@@ -16,10 +16,7 @@ SCHEMA_IMPORT const Driver_fxnTable DATXXR5APP_fxnTable;
static const Driver DATXXR5APP = {
.name = "DAT-XXR5A-PP+",
.status = NULL,
.config = (Parameter[]){
{ .name = "atten", .type = TYPE_INT16 },
{}
},
.config = (Parameter[]){ { .name = "atten", .type = TYPE_INT16 }, {} },
.alerts = NULL,
.fxnTable = &DATXXR5APP_fxnTable,
};

32
firmware/ec/common/inc/ocmp_wrappers/ocmp_debugi2c.h
View File

@@ -16,24 +16,20 @@ SCHEMA_IMPORT bool i2c_write(void *driver, void *data);
static const Driver OC_I2C = {
.name = "OC_I2C",
.argList = (Parameter[]){
{ .name = "slave_address", .type = TYPE_UINT8 },
{ .name = "no_of_bytes", .type = TYPE_UINT8 },
{ .name = "reg_address", .type = TYPE_UINT8 },
{ .name = "reg_values", .type = TYPE_UINT16 },
{}
},
.commands = (Command[]){
{
.name = "get",
.cb_cmd = i2c_read,
},
{
.name = "set",
.cb_cmd = i2c_write,
},
{}
},
.argList = (Parameter[]){ { .name = "slave_address", .type = TYPE_UINT8 },
{ .name = "no_of_bytes", .type = TYPE_UINT8 },
{ .name = "reg_address", .type = TYPE_UINT8 },
{ .name = "reg_values", .type = TYPE_UINT16 },
{} },
.commands = (Command[]){ {
.name = "get",
.cb_cmd = i2c_read,
},
{
.name = "set",
.cb_cmd = i2c_write,
},
{} },
};
#endif /* INC_DEVICES_OCMP_WRAPPERS_OCMP_I2C_H_ */

28
firmware/ec/common/inc/ocmp_wrappers/ocmp_debugmdio.h
View File

@@ -16,22 +16,18 @@ SCHEMA_IMPORT bool mdio_write(void *driver, void *data);
static const Driver OC_MDIO = {
.name = "OC_MDIO",
.argList = (Parameter[]){
{ .name = "reg_address", .type = TYPE_UINT16 },
{ .name = "reg_values", .type = TYPE_UINT16 },
{}
},
.commands = (Command[]){
{
.name = "get",
.cb_cmd = mdio_read,
},
{
.name = "set",
.cb_cmd = mdio_write,
},
{}
},
.argList = (Parameter[]){ { .name = "reg_address", .type = TYPE_UINT16 },
{ .name = "reg_values", .type = TYPE_UINT16 },
{} },
.commands = (Command[]){ {
.name = "get",
.cb_cmd = mdio_read,
},
{
.name = "set",
.cb_cmd = mdio_write,
},
{} },
};
#endif /* INC_DEVICES_OCMP_WRAPPERS_OCMP_MDIO_H_ */

30
firmware/ec/common/inc/ocmp_wrappers/ocmp_debugocgpio.h
View File

@@ -14,26 +14,22 @@
SCHEMA_IMPORT bool ocgpio_get(void *driver, void *data);
SCHEMA_IMPORT bool ocgpio_set(void *driver, void *data);
SCHEMA_IMPORT const Driver_fxnTable DEBUG_OCGPIO_fxnTable;
SCHEMA_IMPORT const Driver_fxnTable DEBUG_OCGPIO_fxnTable;
static const Driver OC_GPIO = {
.name = "OC_GPIO",
.argList = (Parameter[]){
{ .name = "pin", .type = TYPE_UINT8 },
{ .name = "value", .type = TYPE_UINT8 },
{}
},
.commands = (Command[]){
{
.name = "get",
.cb_cmd = ocgpio_get,
},
{
.name = "set",
.cb_cmd = ocgpio_set,
},
{}
},
.argList = (Parameter[]){ { .name = "pin", .type = TYPE_UINT8 },
{ .name = "value", .type = TYPE_UINT8 },
{} },
.commands = (Command[]){ {
.name = "get",
.cb_cmd = ocgpio_get,
},
{
.name = "set",
.cb_cmd = ocgpio_set,
},
{} },
.fxnTable = &DEBUG_OCGPIO_fxnTable,
};

68
firmware/ec/common/inc/ocmp_wrappers/ocmp_eeprom_cat24c04.h
View File

@@ -21,10 +21,11 @@ SCHEMA_IMPORT const Driver_fxnTable CAT24C04_fe_inv_fxnTable;
static const Driver CAT24C04_gbc_sid = {
.name = "EEPROM",
.status = (Parameter[]){
{ .name = "ocserialinfo", .type = TYPE_STR, .size = 21 },
{ .name = "gbcboardinfo", .type = TYPE_STR, .size = 21 },
},
.status =
(Parameter[]){
{ .name = "ocserialinfo", .type = TYPE_STR, .size = 21 },
{ .name = "gbcboardinfo", .type = TYPE_STR, .size = 21 },
},
.fxnTable = &CAT24C04_gbc_sid_fxnTable,
};
@@ -33,48 +34,33 @@ static const Driver CAT24C04_gbc_inv = {
.fxnTable = &CAT24C04_gbc_inv_fxnTable,
};
static const Driver CAT24C04_sdr_inv = {
.name = "Inventory",
.status = (Parameter[]){
{ .name = "dev_id", .type = TYPE_STR,
.size = 19 },
{}
},
.fxnTable = &CAT24C04_sdr_inv_fxnTable,
.name = "Inventory",
.status =
(Parameter[]){ { .name = "dev_id", .type = TYPE_STR, .size = 19 }, {} },
.fxnTable = &CAT24C04_sdr_inv_fxnTable,
};
static const Driver CAT24C04_fe_inv = {
.name = "Inventory",
.status = (Parameter[]){
{ .name = "dev_id", .type = TYPE_STR,
.size = 18 },
{}
},
.fxnTable = &CAT24C04_fe_inv_fxnTable,
.name = "Inventory",
.status =
(Parameter[]){ { .name = "dev_id", .type = TYPE_STR, .size = 18 }, {} },
.fxnTable = &CAT24C04_fe_inv_fxnTable,
};
static const Driver SYSTEMDRV = {
.name = "SYSTEMDRV",
.status = (Parameter[]){
{}
},
.config = (Parameter[]){
{}
},
.alerts = (Parameter[]){
{}
},
.post = (Post[]){
{
.name = "results",
.cb_postCmd = SYS_post_get_results,
},
{
.name = "enable",
.cb_postCmd = SYS_post_enable,
},
{}
}
};
static const Driver SYSTEMDRV = { .name = "SYSTEMDRV",
.status = (Parameter[]){ {} },
.config = (Parameter[]){ {} },
.alerts = (Parameter[]){ {} },
.post = (Post[]){
{
.name = "results",
.cb_postCmd = SYS_post_get_results,
},
{
.name = "enable",
.cb_postCmd = SYS_post_enable,
},
{} } };
static const Driver FLASHDRV = {
.name = "FLASHDRV",

118
firmware/ec/common/inc/ocmp_wrappers/ocmp_eth_sw.h
View File

@@ -1,11 +1,11 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
#ifndef OCMP_ETH_SW_H_
#define OCMP_ETH_SW_H_
#include "common/inc/global/Framework.h"
@@ -20,62 +20,54 @@ SCHEMA_IMPORT bool ETHERNET_tivaClient(void *driver, void *params);
static const Driver ETH_SW = {
.name = "Marvel_88E6071",
.status = (Parameter[]){
{ .name = "speed", .type = TYPE_UINT8 },
{ .name = "duplex", .type = TYPE_UINT8 },
{ .name = "autoneg_on", .type = TYPE_UINT8 },
{ .name = "sleep_mode_en", .type = TYPE_UINT8 },
{ .name = "autoneg_complete", .type = TYPE_UINT8 },
{ .name = "link_up", .type = TYPE_UINT8 },
{}
},
.config = (Parameter[]){
{ .name = "speed", .type = TYPE_UINT8 },
{ .name = "duplex", .type = TYPE_UINT8 },
{ .name = "powerDown", .type = TYPE_UINT8 },
{ .name = "enable_sleepMode", .type = TYPE_UINT8 },
{ .name = "enable_interrupt", .type = TYPE_UINT8 },
{ .name = "switch_reset", .type = TYPE_UINT8 },
{ .name = "restart_autoneg", .type = TYPE_UINT8 },
{}
},
.alerts = (Parameter[]){
{ .name = "speed", .type = TYPE_UINT8 },
{ .name = "duplex", .type = TYPE_UINT8 },
{ .name = "autoneg_complete", .type = TYPE_UINT8 },
{ .name = "crossover_det", .type = TYPE_UINT8 },
{ .name = "energy_det", .type = TYPE_UINT8 },
{ .name = "polarity_change", .type = TYPE_UINT8 },
{ .name = "jabber_det", .type = TYPE_UINT8 },
{}
},
.commands = (Command[]){
{
.name = "reset",
.cb_cmd = ETHERNET_reset,
},
{
.name = "en_loopBk",
.cb_cmd = ETHERNET_enLoopBk,
},
{
.name = "dis_loopBk",
.cb_cmd = ETHERNET_disLoopBk,
},
{
.name = "en_pktGen",
.cb_cmd = ETHERNET_enPktGen,
},
{
.name = "dis_pktGen",
.cb_cmd = ETHERNET_disPktGen,
},
{
.name = "en_tivaClient",
.cb_cmd = ETHERNET_tivaClient,
},
{}
},
.status = (Parameter[]){ { .name = "speed", .type = TYPE_UINT8 },
{ .name = "duplex", .type = TYPE_UINT8 },
{ .name = "autoneg_on", .type = TYPE_UINT8 },
{ .name = "sleep_mode_en", .type = TYPE_UINT8 },
{ .name = "autoneg_complete", .type = TYPE_UINT8 },
{ .name = "link_up", .type = TYPE_UINT8 },
{} },
.config = (Parameter[]){ { .name = "speed", .type = TYPE_UINT8 },
{ .name = "duplex", .type = TYPE_UINT8 },
{ .name = "powerDown", .type = TYPE_UINT8 },
{ .name = "enable_sleepMode", .type = TYPE_UINT8 },
{ .name = "enable_interrupt", .type = TYPE_UINT8 },
{ .name = "switch_reset", .type = TYPE_UINT8 },
{ .name = "restart_autoneg", .type = TYPE_UINT8 },
{} },
.alerts = (Parameter[]){ { .name = "speed", .type = TYPE_UINT8 },
{ .name = "duplex", .type = TYPE_UINT8 },
{ .name = "autoneg_complete", .type = TYPE_UINT8 },
{ .name = "crossover_det", .type = TYPE_UINT8 },
{ .name = "energy_det", .type = TYPE_UINT8 },
{ .name = "polarity_change", .type = TYPE_UINT8 },
{ .name = "jabber_det", .type = TYPE_UINT8 },
{} },
.commands = (Command[]){ {
.name = "reset",
.cb_cmd = ETHERNET_reset,
},
{
.name = "en_loopBk",
.cb_cmd = ETHERNET_enLoopBk,
},
{
.name = "dis_loopBk",
.cb_cmd = ETHERNET_disLoopBk,
},
{
.name = "en_pktGen",
.cb_cmd = ETHERNET_enPktGen,
},
{
.name = "dis_pktGen",
.cb_cmd = ETHERNET_disPktGen,
},
{
.name = "en_tivaClient",
.cb_cmd = ETHERNET_tivaClient,
},
{} },
.fxnTable = &eth_fxnTable,
};

8
firmware/ec/common/inc/ocmp_wrappers/ocmp_fe-param.h
View File

@@ -15,11 +15,9 @@ SCHEMA_IMPORT const Driver_fxnTable FE_PARAM_fxnTable;
static const Driver FE_Param = {
.name = "FE_parametrs",
.config = (Parameter[]){
{ .name = "band", .type = TYPE_UINT16 },
{ .name = "arfcn", .type = TYPE_UINT16 },
{}
},
.config = (Parameter[]){ { .name = "band", .type = TYPE_UINT16 },
{ .name = "arfcn", .type = TYPE_UINT16 },
{} },
.fxnTable = &FE_PARAM_fxnTable,
};

39
firmware/ec/common/inc/ocmp_wrappers/ocmp_ina226.h
View File

@@ -1,11 +1,11 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
#ifndef _OCMP_INA226_H
#define _OCMP_INA226_H
@@ -15,25 +15,18 @@ typedef struct INA226_Config {
uint16_t current_lim;
} INA226_Config;
SCHEMA_IMPORT const Driver_fxnTable INA226_fxnTable;
SCHEMA_IMPORT const Driver_fxnTable INA226_fxnTable;
static const Driver INA226 = {
.name = "INA226",
.status = (Parameter[]){
{ .name = "busvoltage", .type = TYPE_UINT16 },
{ .name = "shuntvoltage", .type = TYPE_UINT16 },
{ .name = "current", .type = TYPE_UINT16 },
{ .name = "power", .type = TYPE_UINT16 },
{}
},
.config = (Parameter[]){
{ .name = "currlimit", .type = TYPE_UINT16 },
{}
},
.alerts = (Parameter[]){
{ .name = "Overcurrent", .type = TYPE_UINT16 },
{}
},
.status = (Parameter[]){ { .name = "busvoltage", .type = TYPE_UINT16 },
{ .name = "shuntvoltage", .type = TYPE_UINT16 },
{ .name = "current", .type = TYPE_UINT16 },
{ .name = "power", .type = TYPE_UINT16 },
{} },
.config = (Parameter[]){ { .name = "currlimit", .type = TYPE_UINT16 }, {} },
.alerts =
(Parameter[]){ { .name = "Overcurrent", .type = TYPE_UINT16 }, {} },
.fxnTable = &INA226_fxnTable,
};

62
firmware/ec/common/inc/ocmp_wrappers/ocmp_iridium.h
View File

@@ -1,11 +1,11 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
#ifndef OCMP_IRIDIUM_H_
#define OCMP_IRIDIUM_H_
@@ -16,31 +16,31 @@ SCHEMA_IMPORT bool IRIDIUM_reset(void *driver, void *params);
static const Driver OBC_Iridium = {
.name = "Iridium 96xx",
.status = (Parameter[]){
{ .name = "imei", .type = TYPE_UINT64 },
{ .name = "mfg", .type = TYPE_STR, .size = 10 },
{ .name = "model", .type = TYPE_STR, .size = 4 },
{ .name = "signal_quality", .type = TYPE_UINT8 },
{ .name = "registration", .type = TYPE_ENUM,
.values = (Enum_Map[]){
{ 0, "Detached" },
{ 1, "None" },
{ 2, "Registered" },
{ 3, "Registration Denied" },
{}
.status =
(Parameter[]){
{ .name = "imei", .type = TYPE_UINT64 },
{ .name = "mfg", .type = TYPE_STR, .size = 10 },
{ .name = "model", .type = TYPE_STR, .size = 4 },
{ .name = "signal_quality", .type = TYPE_UINT8 },
{
.name = "registration",
.type = TYPE_ENUM,
.values = (Enum_Map[]){ { 0, "Detached" },
{ 1, "None" },
{ 2, "Registered" },
{ 3, "Registration Denied" },
{} },
},
},
{ .name = "numberofoutgoingmessage", .type = TYPE_UINT8 },
{ .name = "lasterror", .type = TYPE_UINT8, .size = 3 }, /* TODO: this is a complex type */
{}
},
.commands = (Command[]){
{
.name = "reset",
.cb_cmd = IRIDIUM_reset,
},
{}
},
{ .name = "numberofoutgoingmessage", .type = TYPE_UINT8 },
{ .name = "lasterror",
.type = TYPE_UINT8,
.size = 3 }, /* TODO: this is a complex type */
{} },
.commands = (Command[]){ {
.name = "reset",
.cb_cmd = IRIDIUM_reset,
},
{} },
.fxnTable = &OBC_fxnTable,
.payload_fmt_union = true, /* OBC breaks serialization pattern :( */
};

26
firmware/ec/common/inc/ocmp_wrappers/ocmp_led.h
View File

@@ -1,11 +1,11 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
#ifndef _OCMP_LED_H
#define _OCMP_LED_H
@@ -18,13 +18,11 @@ static const Driver HCI_LED = {
.status = NULL,
.config = NULL,
.alerts = NULL,
.commands = (Command[]){
{
.name = "set",
.cb_cmd = led_testpattern_control,
},
{}
},
.commands = (Command[]){ {
.name = "set",
.cb_cmd = led_testpattern_control,
},
{} },
.fxnTable = &LED_fxnTable,
};

71
firmware/ec/common/inc/ocmp_wrappers/ocmp_ltc4015.h
View File

@@ -1,11 +1,11 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
#ifndef _OCMP_LTC4015_H
#define _OCMP_LTC4015_H
@@ -26,37 +26,32 @@ SCHEMA_IMPORT const Driver_fxnTable LTC4015_fxnTable;
static const Driver LTC4015 = {
.name = "LTC4015",
.status = (Parameter[]){
{ .name = "batteryVoltage", .type = TYPE_INT16 },
{ .name = "batteryCurrent", .type = TYPE_INT16 },
{ .name = "systemVoltage", .type = TYPE_INT16 },
{ .name = "inputVoltage", .type = TYPE_INT16 },
{ .name = "inputCurrent", .type = TYPE_INT16 },
{ .name = "dieTemperature", .type = TYPE_INT16 },
{ .name = "ichargeDAC", .type = TYPE_INT16 },
{}
},
.config = (Parameter[]){
{ .name = "batteryVoltageLow", .type = TYPE_INT16 },
{ .name = "batteryVoltageHigh", .type = TYPE_INT16 },
{ .name = "batteryCurrentLow", .type = TYPE_INT16 },
{ .name = "inputVoltageLow", .type = TYPE_INT16 },
{ .name = "inputCurrentHigh", .type = TYPE_INT16 },
{ .name = "inputCurrentLimit", .type = TYPE_UINT16 },
{ .name = "icharge", .type = TYPE_UINT16 },
{ .name = "vcharge", .type = TYPE_UINT16 },
{ .name = "dieTemperature", .type = TYPE_INT16 },
{}
},
.alerts = (Parameter[]){
{ .name = "BVL", .type = TYPE_INT16 },
{ .name = "BVH", .type = TYPE_INT16 },
{ .name = "BCL", .type = TYPE_INT16 },
{ .name = "IVL", .type = TYPE_INT16 },
{ .name = "ICH", .type = TYPE_INT16 },
{ .name = "DTH", .type = TYPE_INT16 },
{}
},
.status = (Parameter[]){ { .name = "batteryVoltage", .type = TYPE_INT16 },
{ .name = "batteryCurrent", .type = TYPE_INT16 },
{ .name = "systemVoltage", .type = TYPE_INT16 },
{ .name = "inputVoltage", .type = TYPE_INT16 },
{ .name = "inputCurrent", .type = TYPE_INT16 },
{ .name = "dieTemperature", .type = TYPE_INT16 },
{ .name = "ichargeDAC", .type = TYPE_INT16 },
{} },
.config =
(Parameter[]){ { .name = "batteryVoltageLow", .type = TYPE_INT16 },
{ .name = "batteryVoltageHigh", .type = TYPE_INT16 },
{ .name = "batteryCurrentLow", .type = TYPE_INT16 },
{ .name = "inputVoltageLow", .type = TYPE_INT16 },
{ .name = "inputCurrentHigh", .type = TYPE_INT16 },
{ .name = "inputCurrentLimit", .type = TYPE_UINT16 },
{ .name = "icharge", .type = TYPE_UINT16 },
{ .name = "vcharge", .type = TYPE_UINT16 },
{ .name = "dieTemperature", .type = TYPE_INT16 },
{} },
.alerts = (Parameter[]){ { .name = "BVL", .type = TYPE_INT16 },
{ .name = "BVH", .type = TYPE_INT16 },
{ .name = "BCL", .type = TYPE_INT16 },
{ .name = "IVL", .type = TYPE_INT16 },
{ .name = "ICH", .type = TYPE_INT16 },
{ .name = "DTH", .type = TYPE_INT16 },
{} },
.fxnTable = &LTC4015_fxnTable,
};

72
firmware/ec/common/inc/ocmp_wrappers/ocmp_ltc4274.h
View File

@@ -1,11 +1,11 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
#ifndef _OCMP_LTC4274_H_
#define _OCMP_LTC4274_H_
@@ -30,39 +30,31 @@ SCHEMA_IMPORT bool LTC4274_reset(void *driver, void *params);
static const Driver LTC4274 = {
.name = "PSE",
.status = (Parameter[]){
{ .name = "detection", .type = TYPE_UINT16 },
{ .name = "class", .type = TYPE_UINT16 },
{ .name = "powerGood", .type = TYPE_UINT16 },
{}
},
.config = (Parameter[]){
{ .name = "operatingMode", .type = TYPE_UINT16 },
{ .name = "detectEnable", .type = TYPE_UINT16 },
{ .name = "interruptMask", .type = TYPE_UINT16 },
{ .name = "interruptEnable", .type = TYPE_UINT16 },
{ .name = "enableHighpower", .type = TYPE_UINT16 },
{}
},
.alerts = (Parameter[]){
{ .name = "NoAlert", .type = TYPE_UINT8 },
{ .name = "PowerEnable", .type = TYPE_UINT8 },
{ .name = "PowerGood", .type = TYPE_UINT8 },
{ .name = "DiconnectAlert", .type = TYPE_UINT8 },
{ .name = "DetectionAlert", .type = TYPE_UINT8 },
{ .name = "ClassAlert", .type = TYPE_UINT8 },
{ .name = "TCUTAler", .type = TYPE_UINT8 },
{ .name = "TStartAlert", .type = TYPE_UINT8 },
{ .name = "SupplyAlert", .type = TYPE_UINT8 },
{}
},
.commands = (Command[]){
{
.name = "reset",
.cb_cmd = LTC4274_reset,
},
{}
},
.status = (Parameter[]){ { .name = "detection", .type = TYPE_UINT16 },
{ .name = "class", .type = TYPE_UINT16 },
{ .name = "powerGood", .type = TYPE_UINT16 },
{} },
.config = (Parameter[]){ { .name = "operatingMode", .type = TYPE_UINT16 },
{ .name = "detectEnable", .type = TYPE_UINT16 },
{ .name = "interruptMask", .type = TYPE_UINT16 },
{ .name = "interruptEnable", .type = TYPE_UINT16 },
{ .name = "enableHighpower", .type = TYPE_UINT16 },
{} },
.alerts = (Parameter[]){ { .name = "NoAlert", .type = TYPE_UINT8 },
{ .name = "PowerEnable", .type = TYPE_UINT8 },
{ .name = "PowerGood", .type = TYPE_UINT8 },
{ .name = "DiconnectAlert", .type = TYPE_UINT8 },
{ .name = "DetectionAlert", .type = TYPE_UINT8 },
{ .name = "ClassAlert", .type = TYPE_UINT8 },
{ .name = "TCUTAler", .type = TYPE_UINT8 },
{ .name = "TStartAlert", .type = TYPE_UINT8 },
{ .name = "SupplyAlert", .type = TYPE_UINT8 },
{} },
.commands = (Command[]){ {
.name = "reset",
.cb_cmd = LTC4274_reset,
},
{} },
.fxnTable = &LTC4274_fxnTable,
};

32
firmware/ec/common/inc/ocmp_wrappers/ocmp_ltc4275.h
View File

@@ -1,11 +1,11 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
#ifndef COMMON_INC_OCMP_WRAPPERS_OCMP_LTC4275_H_
#define COMMON_INC_OCMP_WRAPPERS_OCMP_LTC4275_H_
@@ -15,17 +15,13 @@ SCHEMA_IMPORT const Driver_fxnTable LTC4275_fxnTable;
static const Driver LTC4275 = {
.name = "LTC4275",
.status = (Parameter[]){
{ .name = "class", .type = TYPE_ENUM },
{ .name = "powerGoodState", .type = TYPE_ENUM },
{}
},
.alerts = (Parameter[]){
{ .name = "INCOMPATIBLE", .type = TYPE_ENUM },
{ .name = "DISCONNECT", .type = TYPE_ENUM },
{ .name = "CONNECT", .type = TYPE_ENUM },
{}
},
.status = (Parameter[]){ { .name = "class", .type = TYPE_ENUM },
{ .name = "powerGoodState", .type = TYPE_ENUM },
{} },
.alerts = (Parameter[]){ { .name = "INCOMPATIBLE", .type = TYPE_ENUM },
{ .name = "DISCONNECT", .type = TYPE_ENUM },
{ .name = "CONNECT", .type = TYPE_ENUM },
{} },
.fxnTable = &LTC4275_fxnTable,
};

9
firmware/ec/common/inc/ocmp_wrappers/ocmp_mac.h
View File

@@ -11,16 +11,15 @@
#include "common/inc/global/Framework.h"
#define OC_MAC_ADDRESS_SIZE 13
#define OC_MAC_ADDRESS_SIZE 13
SCHEMA_IMPORT const Driver_fxnTable MAC_fxnTable;
static const Driver Driver_MAC = {
.name = "MAC",
.config = (Parameter[]){
{ .name = "address", .type = TYPE_STR,
.size = OC_MAC_ADDRESS_SIZE + 1 }
},
.config = (Parameter[]){ { .name = "address",
.type = TYPE_STR,
.size = OC_MAC_ADDRESS_SIZE + 1 } },
.fxnTable = &MAC_fxnTable,
};

35
firmware/ec/common/inc/ocmp_wrappers/ocmp_powersource.h
View File

@@ -1,11 +1,11 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
#ifndef _OCMP_POWERSOURCE_H_
#define _OCMP_POWERSOURCE_H_
@@ -15,17 +15,16 @@ SCHEMA_IMPORT const Driver_fxnTable PWRSRC_fxnTable;
static const Driver PWRSRC = {
.name = "powerSource",
.status = (Parameter[]){
{ .name = "poeAvailability", .type = TYPE_UINT8 },
{ .name = "poeAccessebility", .type = TYPE_UINT8 },
{ .name = "solarAvailability", .type = TYPE_UINT8 },
{ .name = "solarAccessebility", .type = TYPE_UINT8 },
{ .name = "extBattAvailability", .type = TYPE_UINT8 },
{ .name = "extBattAccessebility", .type = TYPE_UINT8 },
{ .name = "intBattAvailability", .type = TYPE_UINT8 },
{ .name = "intBattAccessebility", .type = TYPE_UINT8 },
{}
},
.status =
(Parameter[]){ { .name = "poeAvailability", .type = TYPE_UINT8 },
{ .name = "poeAccessebility", .type = TYPE_UINT8 },
{ .name = "solarAvailability", .type = TYPE_UINT8 },
{ .name = "solarAccessebility", .type = TYPE_UINT8 },
{ .name = "extBattAvailability", .type = TYPE_UINT8 },
{ .name = "extBattAccessebility", .type = TYPE_UINT8 },
{ .name = "intBattAvailability", .type = TYPE_UINT8 },
{ .name = "intBattAccessebility", .type = TYPE_UINT8 },
{} },
.fxnTable = &PWRSRC_fxnTable,
};
#endif /* _OCMP_POWERSOURCE_H_ */

22
firmware/ec/common/inc/ocmp_wrappers/ocmp_rfpowermonitor.h
View File

@@ -1,11 +1,11 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
#ifndef OCMP_RFPOWERMONITOR_H_
#define OCMP_RFPOWERMONITOR_H_
@@ -14,11 +14,9 @@
SCHEMA_IMPORT const Driver_fxnTable RFPowerMonitor_fxnTable;
static const Driver RFPowerMonitor = {
.status = (Parameter[]){
{ .name = "forward", .type = TYPE_UINT16 },
{ .name = "reverse", .type = TYPE_UINT16 },
{}
},
.status = (Parameter[]){ { .name = "forward", .type = TYPE_UINT16 },
{ .name = "reverse", .type = TYPE_UINT16 },
{} },
.fxnTable = &RFPowerMonitor_fxnTable,
};

7
firmware/ec/common/inc/ocmp_wrappers/ocmp_rfwatchdog.h
View File

@@ -15,11 +15,8 @@ SCHEMA_IMPORT const Driver_fxnTable RFFEWatchdogP_fxnTable;
static const Driver RFFEWatchdog = {
.name = "RFFE Watchdog",
.alerts = (Parameter[]){
{ .name = "LB_R_PWR" },
{ .name = "HB_R_PWR" },
{}
},
.alerts =
(Parameter[]){ { .name = "LB_R_PWR" }, { .name = "HB_R_PWR" }, {} },
.fxnTable = &RFFEWatchdogP_fxnTable,
};

42
firmware/ec/common/inc/ocmp_wrappers/ocmp_se98a.h
View File

@@ -1,11 +1,11 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
#ifndef _OCMP_SE98A_H
#define _OCMP_SE98A_H
@@ -20,26 +20,20 @@ typedef union SE98A_Config {
int8_t limits[3];
} SE98A_Config;
SCHEMA_IMPORT const Driver_fxnTable SE98_fxnTable;
SCHEMA_IMPORT const Driver_fxnTable SE98_fxnTable;
static const Driver SE98A = {
.name = "SE98A",
.status = (Parameter[]){
{ .name = "temperature", .type = TYPE_UINT8 },
{}
},
.config = (Parameter[]){
{ .name = "lowlimit", .type = TYPE_INT8 },
{ .name = "highlimit", .type = TYPE_UINT8 },
{ .name = "critlimit", .type = TYPE_UINT8 },
{}
},
.alerts = (Parameter[]){
{ .name = "BAW", .type = TYPE_UINT8 },
{ .name = "AAW", .type = TYPE_UINT8 },
{ .name = "ACW", .type = TYPE_UINT8 },
{}
},
.status =
(Parameter[]){ { .name = "temperature", .type = TYPE_UINT8 }, {} },
.config = (Parameter[]){ { .name = "lowlimit", .type = TYPE_INT8 },
{ .name = "highlimit", .type = TYPE_UINT8 },
{ .name = "critlimit", .type = TYPE_UINT8 },
{} },
.alerts = (Parameter[]){ { .name = "BAW", .type = TYPE_UINT8 },
{ .name = "AAW", .type = TYPE_UINT8 },
{ .name = "ACW", .type = TYPE_UINT8 },
{} },
.fxnTable = &SE98_fxnTable,
};

23
firmware/ec/common/inc/ocmp_wrappers/ocmp_syncio.h
View File

@@ -11,21 +11,18 @@
#include "common/inc/global/Framework.h"
SCHEMA_IMPORT const Driver_fxnTable SYNC_fxnTable;
SCHEMA_IMPORT const Driver_fxnTable SYNC_fxnTable;
static const Driver Sync_IO = {
.name = "sync_ioexp",
.status = (Parameter[]){
{
.name = "gps_lock",
.type = TYPE_ENUM,
.values = (Enum_Map[]){
{0, "Gps Not Locked" },
{1, "Gps Locked" },
{}
},
},
{}
},
.status =
(Parameter[]){ {
.name = "gps_lock",
.type = TYPE_ENUM,
.values = (Enum_Map[]){ { 0, "Gps Not Locked" },
{ 1, "Gps Locked" },
{} },
},
{} },
.fxnTable = &SYNC_fxnTable,
};

143
firmware/ec/common/inc/ocmp_wrappers/ocmp_testmodule.h
View File

@@ -1,11 +1,11 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
#ifndef OCMP_TESTMODULE_H_
#define OCMP_TESTMODULE_H_
@@ -24,77 +24,68 @@ SCHEMA_IMPORT bool TestMod_cmdReset(void *driver, void *params);
static const Driver Testmod_G510 = {
.name = "Fibocom G510",
.status = (Parameter[]){
{ .name = "imei", .type = TYPE_UINT64 },
{ .name = "imsi", .type = TYPE_UINT64 },
{ .name = "mfg", .type = TYPE_STR, .size = 10 },
{ .name = "model", .type = TYPE_STR, .size = 5 },
{ .name = "rssi", .type = TYPE_UINT8 },
{ .name = "ber", .type = TYPE_UINT8 },
{ .name = "registration", .type = TYPE_ENUM,
.values = (Enum_Map[]){
{ 0, "Not Registered, Not Searching" },
{ 1, "Registered, Home Network" },
{ 2, "Not Registered, Searching" },
{ 3, "Registration Denied" },
{ 4, "Status Unknown" },
{ 5, "Registered, Roaming" },
{}
.status =
(Parameter[]){
{ .name = "imei", .type = TYPE_UINT64 },
{ .name = "imsi", .type = TYPE_UINT64 },
{ .name = "mfg", .type = TYPE_STR, .size = 10 },
{ .name = "model", .type = TYPE_STR, .size = 5 },
{ .name = "rssi", .type = TYPE_UINT8 },
{ .name = "ber", .type = TYPE_UINT8 },
{
.name = "registration",
.type = TYPE_ENUM,
.values = (Enum_Map[]){ { 0, "Not Registered, Not Searching" },
{ 1, "Registered, Home Network" },
{ 2, "Not Registered, Searching" },
{ 3, "Registration Denied" },
{ 4, "Status Unknown" },
{ 5, "Registered, Roaming" },
{} },
},
},
{ .name = "network_operatorinfo", .type = TYPE_UINT8, .size = 3 }, /* TODO: this is a complex type */
{ .name = "cellid", .type = TYPE_UINT32 },
{ .name = "bsic", .type = TYPE_UINT8 },
{ .name = "lasterror",.type = TYPE_UINT8, .size = 3 }, /* TODO: this is a complex type */
{}
},
.alerts = (Parameter[]){
{ .name = "Call State Changed", .type = TYPE_ENUM,
.values = (Enum_Map[]){
{ 0, "Ringing" },
{ 1, "Call End" },
{}
{ .name = "network_operatorinfo",
.type = TYPE_UINT8,
.size = 3 }, /* TODO: this is a complex type */
{ .name = "cellid", .type = TYPE_UINT32 },
{ .name = "bsic", .type = TYPE_UINT8 },
{ .name = "lasterror",
.type = TYPE_UINT8,
.size = 3 }, /* TODO: this is a complex type */
{} },
.alerts =
(Parameter[]){
{
.name = "Call State Changed",
.type = TYPE_ENUM,
.values =
(Enum_Map[]){ { 0, "Ringing" }, { 1, "Call End" }, {} },
},
},
/* TODO: var len str */
{ .name = "Incoming SMS", .type = TYPE_STR, .size = 20 },
{}
},
.commands = (Command[]){
{
.name = "disconnect_nw",
.cb_cmd = TestMod_cmdDisconnect
},
{
.name = "connect_nw",
.cb_cmd = TestMod_cmdConnect
},
{
.name = "send",
.cb_cmd = TestMod_cmdSendSms
},
{
.name = "dial",
.cb_cmd = TestMod_cmdDial
},
{
.name = "answer",
.cb_cmd = TestMod_cmdAnswer,
},
{
.name = "hangup",
.cb_cmd = TestMod_cmdHangup,
},
{
.name = "enable",
.cb_cmd = TestMod_cmdEnable,
},
{
.name = "disable",
.cb_cmd = TestMod_cmdDisable,
},
{}
},
/* TODO: var len str */
{ .name = "Incoming SMS", .type = TYPE_STR, .size = 20 },
{} },
.commands =
(Command[]){
{ .name = "disconnect_nw", .cb_cmd = TestMod_cmdDisconnect },
{ .name = "connect_nw", .cb_cmd = TestMod_cmdConnect },
{ .name = "send", .cb_cmd = TestMod_cmdSendSms },
{ .name = "dial", .cb_cmd = TestMod_cmdDial },
{
.name = "answer",
.cb_cmd = TestMod_cmdAnswer,
},
{
.name = "hangup",
.cb_cmd = TestMod_cmdHangup,
},
{
.name = "enable",
.cb_cmd = TestMod_cmdEnable,
},
{
.name = "disable",
.cb_cmd = TestMod_cmdDisable,
},
{} },
.fxnTable = &G510_fxnTable,
.payload_fmt_union = true, /* Testmodule breaks serialization pattern :( */
};

6
firmware/ec/inc/common/bigbrother.h
View File

@@ -19,13 +19,13 @@
/*****************************************************************************
* MACRO DEFINITIONS
*****************************************************************************/
#define BIGBROTHER_TASK_PRIORITY 5
#define BIGBROTHER_TASK_STACK_SIZE 8096
#define BIGBROTHER_TASK_PRIORITY 5
#define BIGBROTHER_TASK_STACK_SIZE 8096
typedef enum {
OC_SYS_S_ID_EEPROM = 1,
OC_SYS_INVEN_EEPROM = 2,
OC_SYS_FLASH= 3,
OC_SYS_FLASH = 3,
} eSysDeviceSno;
/* Semaphore and Queue Handles for Big Brother */

57
firmware/ec/inc/common/byteorder.h
View File

@@ -12,44 +12,45 @@
/* Detect endianness if using TI compiler */
#ifndef __BYTE_ORDER__
#define __ORDER_LITTLE_ENDIAN__ 1234
#define __ORDER_BIG_ENDIAN__ 4321
#ifdef __little_endian__
#define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
#else
#ifdef __big_endian__
#define __BYTE_ORDER__ __ORDER_BIG_ENDIAN__
#else
#error Unable to detect byte order!
#endif
#endif
# define __ORDER_LITTLE_ENDIAN__ 1234
# define __ORDER_BIG_ENDIAN__ 4321
# ifdef __little_endian__
# define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
# else
# ifdef __big_endian__
# define __BYTE_ORDER__ __ORDER_BIG_ENDIAN__
# else
# error Unable to detect byte order!
# endif
# endif
#endif
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
/* Little endian host functions here */
#define htobe16(a) ( (((a)>>8)&0xff) + (((a)<<8)&0xff00) )
#define betoh16(a) htobe16(a)
/* Little endian host functions here */
# define htobe16(a) ((((a) >> 8) & 0xff) + (((a) << 8) & 0xff00))
# define betoh16(a) htobe16(a)
#define htobe32(a) ((((a) & 0xff000000) >> 24) | (((a) & 0x00ff0000) >> 8) | \
(((a) & 0x0000ff00) << 8) | (((a) & 0x000000ff) << 24) )
#define betoh32(a) htobe32(a)
# define htobe32(a) \
((((a)&0xff000000) >> 24) | (((a)&0x00ff0000) >> 8) | \
(((a)&0x0000ff00) << 8) | (((a)&0x000000ff) << 24))
# define betoh32(a) htobe32(a)
#define htole16(a) a; // Host is a little endian.
#define letoh16(a) htole16(a)
# define htole16(a) a; // Host is a little endian.
# define letoh16(a) htole16(a)
#else
/* Big endian host functions here */
#define htole16(a) ( (((a)>>8)&0xff) + (((a)<<8)&0xff00) )
#define letoh16(a) htobe16(a)
/* Big endian host functions here */
# define htole16(a) ((((a) >> 8) & 0xff) + (((a) << 8) & 0xff00))
# define letoh16(a) htobe16(a)
#define htole32(a) ((((a) & 0xff000000) >> 24) | (((a) & 0x00ff0000) >> 8) | \
(((a) & 0x0000ff00) << 8) | (((a) & 0x000000ff) << 24) )
#define letoh32(a) htobe32(a)
# define htole32(a) \
((((a)&0xff000000) >> 24) | (((a)&0x00ff0000) >> 8) | \
(((a)&0x0000ff00) << 8) | (((a)&0x000000ff) << 24))
# define letoh32(a) htobe32(a)
#define htobe16(a) a; // Host is a little endian.
#define betoh16(a) htole16(a)
# define htobe16(a) a; // Host is a little endian.
# define betoh16(a) htole16(a)
#endif
#endif /* INC_COMMON_BYTEORDER_H_ */

110
firmware/ec/inc/common/global_header.h
View File

@@ -9,8 +9,8 @@
#ifndef GLOBAL_HEADER_H_
#define GLOBAL_HEADER_H_
#define _FW_REV_MAJOR_ 0
#define _FW_REV_MINOR_ 4
#define _FW_REV_MAJOR_ 0
#define _FW_REV_MINOR_ 4
#define _FW_REV_BUGFIX_ 0
#define _FW_REV_TAG_ __COMMIT_HASH__
@@ -21,54 +21,78 @@
#include <xdc/runtime/System.h> /* For System_printf */
#if 1
#define DEBUG(...) {System_printf(__VA_ARGS__); System_flush();}
# define DEBUG(...) \
{ \
System_printf(__VA_ARGS__); \
System_flush(); \
}
#define LOGGER(...) {System_printf(__VA_ARGS__); System_flush();}
#define LOGGER_WARNING(...) {System_printf(__VA_ARGS__); System_flush();}
#define LOGGER_ERROR(...) {System_printf(__VA_ARGS__); System_flush();}
#ifdef DEBUG_LOGS
#define LOGGER_DEBUG(...) {System_printf(__VA_ARGS__); System_flush();}
# define LOGGER(...) \
{ \
System_printf(__VA_ARGS__); \
System_flush(); \
}
# define LOGGER_WARNING(...) \
{ \
System_printf(__VA_ARGS__); \
System_flush(); \
}
# define LOGGER_ERROR(...) \
{ \
System_printf(__VA_ARGS__); \
System_flush(); \
}
# ifdef DEBUG_LOGS
# define LOGGER_DEBUG(...) \
{ \
System_printf(__VA_ARGS__); \
System_flush(); \
}
#define NOP_DELAY() { uint32_t delay =7000000;\
while (delay--) \
;\
}
# define NOP_DELAY() \
{ \
uint32_t delay = 7000000; \
while (delay--) \
; \
}
# else
# define LOGGER_DEBUG(...)
# define NOP_DELAY()
# endif
#else
#define LOGGER_DEBUG(...)
#define NOP_DELAY()
#endif
#else
#define DEBUG(...) //
# define DEBUG(...) //
#define LOGGER(...) //
#define LOGGER_WARNING(...) //
#define LOGGER_ERROR(...) //
#ifdef DEBUG_LOGS
#define LOGGER_DEBUG(...) //
# define LOGGER(...) //
# define LOGGER_WARNING(...) //
# define LOGGER_ERROR(...) //
# ifdef DEBUG_LOGS
# define LOGGER_DEBUG(...) //
# endif
# define NOP_DELAY() \
{ \
uint32_t delay = 7000000; \
while (delay--) \
; \
}
#endif
#define NOP_DELAY() { uint32_t delay =7000000;\
while (delay--) \
;\
}
#endif
#define RET_OK 0
#define RET_NOT_OK 1
#define RET_OK 0
#define RET_NOT_OK 1
typedef enum {
RETURN_OK = 0x00,
RETURN_NOTOK = 0x01,
RETURN_OCMP_INVALID_SS_TYPE = 0x02,
RETURN_OCMP_INVALID_MSG_TYPE = 0x03,
RETURN_OCMP_INVALID_COMP_TYPE = 0x04,
RETURN_OCMP_INVALID_AXN_TYPE = 0x05,
RETURN_OCMP_INVALID_PARAM_INFO = 0x06,
RETURN_OCMP_INVALID_CMD_INFO = 0x07,
RETURN_OCMP_INVALID_IFACE_TYPE = 0x08,
RETURN_DEV_VALUE_TOO_LOW = 0x09,
RETURN_DEV_VALUE_TOO_HIGH = 0x0A,
RETURN_DEV_I2C_BUS_FAILURE = 0x0B,
RETURN_SS_NOT_READY = 0x0C,
RETURN_SS_NOT_RESET_STATE = 0x0D
RETURN_OK = 0x00,
RETURN_NOTOK = 0x01,
RETURN_OCMP_INVALID_SS_TYPE = 0x02,
RETURN_OCMP_INVALID_MSG_TYPE = 0x03,
RETURN_OCMP_INVALID_COMP_TYPE = 0x04,
RETURN_OCMP_INVALID_AXN_TYPE = 0x05,
RETURN_OCMP_INVALID_PARAM_INFO = 0x06,
RETURN_OCMP_INVALID_CMD_INFO = 0x07,
RETURN_OCMP_INVALID_IFACE_TYPE = 0x08,
RETURN_DEV_VALUE_TOO_LOW = 0x09,
RETURN_DEV_VALUE_TOO_HIGH = 0x0A,
RETURN_DEV_I2C_BUS_FAILURE = 0x0B,
RETURN_SS_NOT_READY = 0x0C,
RETURN_SS_NOT_RESET_STATE = 0x0D
} ReturnStatus;
#endif /* GLOBAL_HEADER_H_ */

18
firmware/ec/inc/common/i2cbus.h
View File

@@ -33,16 +33,12 @@ I2C_Handle i2c_open_bus(unsigned int index);
/* Wrapper to ease migration */
#define i2c_get_handle i2c_open_bus
void i2c_close_bus(I2C_Handle* i2cHandle);
ReturnStatus i2c_reg_write( I2C_Handle i2cHandle,
uint8_t deviceAddress,
uint8_t regAddress,
uint16_t value,
uint8_t numofBytes);
ReturnStatus i2c_reg_read( I2C_Handle i2cHandle,
uint8_t deviceAddress,
uint8_t regAddress,
uint16_t *value,
uint8_t numofBytes);
void i2c_close_bus(I2C_Handle *i2cHandle);
ReturnStatus i2c_reg_write(I2C_Handle i2cHandle, uint8_t deviceAddress,
uint8_t regAddress, uint16_t value,
uint8_t numofBytes);
ReturnStatus i2c_reg_read(I2C_Handle i2cHandle, uint8_t deviceAddress,
uint8_t regAddress, uint16_t *value,
uint8_t numofBytes);
#endif /* I2CBUS_H_ */

5
firmware/ec/inc/common/post.h
View File

@@ -24,9 +24,8 @@
*****************************************************************************/
#define POST_RECORDS 55
#define OC_POST_TASKPRIORITY 3
#define POST_TASK_STACK_SIZE 4096
#define OC_POST_TASKPRIORITY 3
#define POST_TASK_STACK_SIZE 4096
/*****************************************************************************
* HANDLE DECLARATIONS

3
firmware/ec/inc/common/post_util.h
View File

@@ -12,7 +12,6 @@
#include "common/inc/global/Framework.h"
#include "inc/common/post.h"
ReturnStatus _execPost(OCMPMessageFrame *pMsg,
unsigned int subsystem_id);
ReturnStatus _execPost(OCMPMessageFrame *pMsg, unsigned int subsystem_id);
#endif /* INC_COMMON_POST_UTIL_H_ */

36
firmware/ec/inc/common/spibus.h
View File

@@ -1,15 +1,14 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
#ifndef INC_COMMON_SPIBUS_H_
#define INC_COMMON_SPIBUS_H_
/*****************************************************************************
* HEADER FILES
*****************************************************************************/
@@ -30,21 +29,12 @@ typedef struct SPI_Dev {
*****************************************************************************/
SPI_Handle spi_get_handle(unsigned int index);
ReturnStatus spi_reg_read(SPI_Handle spiHandle,
OcGpio_Pin *chip_select,
void *regAddress,
uint8_t *data,
uint32_t data_size,
uint32_t byte,
uint8_t numofBytes);
ReturnStatus spi_reg_write(SPI_Handle spiHandle,
OcGpio_Pin *chip_select,
void *regAddress,
uint8_t *data,
uint32_t data_size,
uint32_t byte,
uint8_t numofBytes);
ReturnStatus spi_reg_read(SPI_Handle spiHandle, OcGpio_Pin *chip_select,
void *regAddress, uint8_t *data, uint32_t data_size,
uint32_t byte, uint8_t numofBytes);
ReturnStatus spi_reg_write(SPI_Handle spiHandle, OcGpio_Pin *chip_select,
void *regAddress, uint8_t *data, uint32_t data_size,
uint32_t byte, uint8_t numofBytes);
#endif /* INC_COMMON_SPIBUS_H_ */

354
firmware/ec/inc/devices/88E6071_registers.h
View File

@@ -10,214 +10,214 @@
#define _88E6071_REGISTERS_H_
/* SMI Device IDs */
#define PHY_PORT_0 0
#define PHY_PORT_1 1
#define PHY_PORT_2 2
#define PHY_PORT_3 3
#define PHY_PORT_4 4
#define GLOBAL_2 7
#define SW_PORT_0 8
#define SW_PORT_1 9
#define SW_PORT_2 10
#define SW_PORT_3 11
#define SW_PORT_4 12
#define SW_PORT_5 13
#define SW_PORT_6 14
#define GLOBAL_1 15
#define PHY_PORT_0 0
#define PHY_PORT_1 1
#define PHY_PORT_2 2
#define PHY_PORT_3 3
#define PHY_PORT_4 4
#define GLOBAL_2 7
#define SW_PORT_0 8
#define SW_PORT_1 9
#define SW_PORT_2 10
#define SW_PORT_3 11
#define SW_PORT_4 12
#define SW_PORT_5 13
#define SW_PORT_6 14
#define GLOBAL_1 15
/* PHY Specific Register set */
#define REG_PHY_CONTROL 0x0
#define REG_PHY_STATUS 0x1
#define REG_PHY_ID_1 0x2
#define REG_PHY_ID_2 0x3
#define REG_AUTONEG_ADV 0x4
#define REG_LINK_PARTNER_ABILITY 0x5
#define REG_AUTO_NEG_EXPANSION 0x6
#define REG_NXT_PAGE_TRANSMIT 0x7
#define REG_LINK_PARTNER_NXT_PAGE 0x8
#define REG_MMD_ACCESS_CNTRL 0xD
#define REG_MMD_ADDR_DATA 0xC
#define REG_PHY_SPEC_CONTROL 0x10
#define REG_PHY_SPEC_STATUS 0x11
#define REG_PHY_INTERRUPT_EN 0x12
#define REG_PHY_INTERRUPT_STATUS 0x13
#define REG_RCV_ERR_COUNTER 0x15
#define REG_PHY_CONTROL 0x0
#define REG_PHY_STATUS 0x1
#define REG_PHY_ID_1 0x2
#define REG_PHY_ID_2 0x3
#define REG_AUTONEG_ADV 0x4
#define REG_LINK_PARTNER_ABILITY 0x5
#define REG_AUTO_NEG_EXPANSION 0x6
#define REG_NXT_PAGE_TRANSMIT 0x7
#define REG_LINK_PARTNER_NXT_PAGE 0x8
#define REG_MMD_ACCESS_CNTRL 0xD
#define REG_MMD_ADDR_DATA 0xC
#define REG_PHY_SPEC_CONTROL 0x10
#define REG_PHY_SPEC_STATUS 0x11
#define REG_PHY_INTERRUPT_EN 0x12
#define REG_PHY_INTERRUPT_STATUS 0x13
#define REG_RCV_ERR_COUNTER 0x15
/* GLOBAL - 1 */
#define REG_GLOBAL_STATUS 0x0
#define REG_GLOBAL_CONTROL 0x4
#define REG_VTU_CONTROL 0x5
#define REG_VTU_VID 0x6
#define REG_VTU_DATA_PORT_3_0 0x7
#define REG_VTU_DATA_PORT_6_4 0x8
#define REG_ATU_CONTROL 0xA
#define REG_ATU_OPERATION 0xB
#define REG_ATU_DATA 0xC
#define REG_GLOBAL_STATUS 0x0
#define REG_GLOBAL_CONTROL 0x4
#define REG_VTU_CONTROL 0x5
#define REG_VTU_VID 0x6
#define REG_VTU_DATA_PORT_3_0 0x7
#define REG_VTU_DATA_PORT_6_4 0x8
#define REG_ATU_CONTROL 0xA
#define REG_ATU_OPERATION 0xB
#define REG_ATU_DATA 0xC
/* GLOBAL - 2 */
#define REG_INTERRUPT_SOURCE 0x0
#define REG_INTERRUPT_MASK 0x1
#define REG_MGMT_EN_2X 0x2
#define REG_MGMT_EN_0X 0x3
#define REG_MANAGEMENT 0x5
#define REG_TRUNK_MASK 0x7
#define REG_INGRESS_RATE_CMD 0x9
#define REG_INGRESS_RATE_DATA 0xA
#define REG_SWITCH_MAC 0xD
#define REG_ATU_STATS 0xE
#define REG_PRIORITY_OVERRIDES 0xF
#define REG_EEPROM_CMD 0x14
#define REG_EEPROM_DATA 0x15
#define REG_AVB_CMD 0x16
#define REG_AVB_DATA 0x17
#define REG_SMI_CMD 0x18
#define REG_SMI_DATA 0x19
#define REG_SCRATCH_MISC 0x1A
#define REG_WATCHDOG 0x1B
#define REG_INTERRUPT_SOURCE 0x0
#define REG_INTERRUPT_MASK 0x1
#define REG_MGMT_EN_2X 0x2
#define REG_MGMT_EN_0X 0x3
#define REG_MANAGEMENT 0x5
#define REG_TRUNK_MASK 0x7
#define REG_INGRESS_RATE_CMD 0x9
#define REG_INGRESS_RATE_DATA 0xA
#define REG_SWITCH_MAC 0xD
#define REG_ATU_STATS 0xE
#define REG_PRIORITY_OVERRIDES 0xF
#define REG_EEPROM_CMD 0x14
#define REG_EEPROM_DATA 0x15
#define REG_AVB_CMD 0x16
#define REG_AVB_DATA 0x17
#define REG_SMI_CMD 0x18
#define REG_SMI_DATA 0x19
#define REG_SCRATCH_MISC 0x1A
#define REG_WATCHDOG 0x1B
/* Switch Ports registers */
#define REG_PORT_STATUS 0x0
#define REG_MAC_CONTROL 0x1
#define REG_JAMING_CONTROL 0x2
#define REG_SW_IDENTIFIER 0x3
#define REG_PORT_CONTROL 0x4
#define REG_PORT_CONTROL_1 0x5
#define REG_VLAN_MAP 0x6
#define REG_VLAN_ID_PRIORITY 0x7
#define REG_PORT_ID_2 0x8
#define REG_EGRESS_RATE_CONTROL 0x9
#define REG_EGRESS_RATE_CONTROL_2 0xA
#define REG_PORT_ASSOCITATION_VECTOR 0xB
#define REG_PRIORITY_OVERRIDE 0xD
#define REG_POLICY_CONTROL 0xE
#define REG_PORT_ETYPE 0xF
#define REG_RX_FRAME_COUNTER 0x10
#define REG_TX_FRAME_COUNTER 0x11
#define REG_INDISCARD_COUNTER 0x12
#define REG_INFILTERED_COUNTER 0x13
#define REG_LED_CONTROL 0x16
#define REG_TAG_REMAP_3_0 0x18
#define REG_TAG_REMAP_7_4 0x19
#define REG_QUEUE_COUNTER 0x1B
#define REG_PORT_STATUS 0x0
#define REG_MAC_CONTROL 0x1
#define REG_JAMING_CONTROL 0x2
#define REG_SW_IDENTIFIER 0x3
#define REG_PORT_CONTROL 0x4
#define REG_PORT_CONTROL_1 0x5
#define REG_VLAN_MAP 0x6
#define REG_VLAN_ID_PRIORITY 0x7
#define REG_PORT_ID_2 0x8
#define REG_EGRESS_RATE_CONTROL 0x9
#define REG_EGRESS_RATE_CONTROL_2 0xA
#define REG_PORT_ASSOCITATION_VECTOR 0xB
#define REG_PRIORITY_OVERRIDE 0xD
#define REG_POLICY_CONTROL 0xE
#define REG_PORT_ETYPE 0xF
#define REG_RX_FRAME_COUNTER 0x10
#define REG_TX_FRAME_COUNTER 0x11
#define REG_INDISCARD_COUNTER 0x12
#define REG_INFILTERED_COUNTER 0x13
#define REG_LED_CONTROL 0x16
#define REG_TAG_REMAP_3_0 0x18
#define REG_TAG_REMAP_7_4 0x19
#define REG_QUEUE_COUNTER 0x1B
#define REG_C45_PACKET_GEN 0x8030
#define REG_C45_CRC_ERROR_COUNTER 0x8031
#define REG_C45_PACKET_GEN 0x8030
#define REG_C45_CRC_ERROR_COUNTER 0x8031
/*
* PHY Register fields SMI Device address 0x0 to 0x4
*/
//REG_PHY_CONTROL - 0x0
#define SOFT_RESET (1 << 0xF)
#define LOOPBACK_EN (1 << 0xE)
#define SPEED (1 << 0xD)
#define AUTONEG_EN (1 << 0xC)
#define PWR_DOWN (1 << 0xB)
#define RESTART_AUTONEG (1 << 0xA)
#define DUPLEX (1 << 0x8)
// REG_PHY_CONTROL - 0x0
#define SOFT_RESET (1 << 0xF)
#define LOOPBACK_EN (1 << 0xE)
#define SPEED (1 << 0xD)
#define AUTONEG_EN (1 << 0xC)
#define PWR_DOWN (1 << 0xB)
#define RESTART_AUTONEG (1 << 0xA)
#define DUPLEX (1 << 0x8)
//REG_PHY_STATUS - 0x1
#define AUTONEG_DONE (1 << 0x5)
#define LINK_UP (1 << 0x2)
// REG_PHY_STATUS - 0x1
#define AUTONEG_DONE (1 << 0x5)
#define LINK_UP (1 << 0x2)
//REG_MMD_ACCESS_CNTRL - 0xD
#define DEVADDR (0x1F << 0x0)
#define FUNCTION (0x03 << 0xD)
// REG_MMD_ACCESS_CNTRL - 0xD
#define DEVADDR (0x1F << 0x0)
#define FUNCTION (0x03 << 0xD)
//REG_PHY_SPEC_CONTROL - 0x10
#define ENERGY_DET (1 << 0xE)
#define DIS_NLP_CHECK (1 << 0xD)
#define EXT_DISTANCE (1 << 0x7)
#define SIGDET_POL (1 << 0x6)
#define AUTOMDI_CROSSOVER (0x03 << 0x4)
#define AUTOPOL_REVERSE (1 << 0x1)
// REG_PHY_SPEC_CONTROL - 0x10
#define ENERGY_DET (1 << 0xE)
#define DIS_NLP_CHECK (1 << 0xD)
#define EXT_DISTANCE (1 << 0x7)
#define SIGDET_POL (1 << 0x6)
#define AUTOMDI_CROSSOVER (0x03 << 0x4)
#define AUTOPOL_REVERSE (1 << 0x1)
//REG_PHY_SPEC_STATUS - 0x11
#define RES_SPEED (1 << 0xE)
#define RES_DUPLEX (1 << 0xD)
#define RT_LINK (1 << 0xA)
#define MDI_CROSSOVER_STATUS (1 << 0x6)
#define SLEEP_MODE (1 << 0x4)
#define POLARITY (1 << 0x1)
#define JABBER_DET (1 << 0x0)
// REG_PHY_SPEC_STATUS - 0x11
#define RES_SPEED (1 << 0xE)
#define RES_DUPLEX (1 << 0xD)
#define RT_LINK (1 << 0xA)
#define MDI_CROSSOVER_STATUS (1 << 0x6)
#define SLEEP_MODE (1 << 0x4)
#define POLARITY (1 << 0x1)
#define JABBER_DET (1 << 0x0)
//REG_PHY_INTERRUPT_EN - 0x12
#define SPEED_INT_EN (1 << 0xE)
#define DUPLEX_INT_EN (1 << 0xD)
#define PAGE_RX_INT_STATUS_EN (1 << 0xC)
#define AUTONEG_COMPLETE_INT_EN (1 << 0xB)
#define LINK_CHANGE_INT_EN (1 << 0xA)
#define MDI_CROSSOVER_INT_EN (1 << 0x6)
#define ENERGY_DET_INT_EN (1 << 0x4)
#define POLARITY_INT_EN (1 << 0x1)
#define JABBER_INT_EN (1 << 0x0)
// REG_PHY_INTERRUPT_EN - 0x12
#define SPEED_INT_EN (1 << 0xE)
#define DUPLEX_INT_EN (1 << 0xD)
#define PAGE_RX_INT_STATUS_EN (1 << 0xC)
#define AUTONEG_COMPLETE_INT_EN (1 << 0xB)
#define LINK_CHANGE_INT_EN (1 << 0xA)
#define MDI_CROSSOVER_INT_EN (1 << 0x6)
#define ENERGY_DET_INT_EN (1 << 0x4)
#define POLARITY_INT_EN (1 << 0x1)
#define JABBER_INT_EN (1 << 0x0)
//REG_PHY_INTERRUPT_STATUS - 0x13
#define SPEED_INT_STATUS (1 << 0xE)
#define DUPLEX_INT_STATUS (1 << 0xD)
#define PAGE_RX_INT_STATUS (1 << 0xC)
// REG_PHY_INTERRUPT_STATUS - 0x13
#define SPEED_INT_STATUS (1 << 0xE)
#define DUPLEX_INT_STATUS (1 << 0xD)
#define PAGE_RX_INT_STATUS (1 << 0xC)
#define AUTONEG_COMPLETE_INT_STATUS (1 << 0xB)
#define LINK_CHANGE_INT_STATUS (1 << 0xA)
#define MDI_CROSSOVER_INT_STATUS (1 << 0x6)
#define ENERGY_DET_INT_STATUS (1 << 0x4)
#define POLARITY_INT_STATUS (1 << 0x1)
#define JABBER_INT_STATUS (1 << 0x0)
#define LINK_CHANGE_INT_STATUS (1 << 0xA)
#define MDI_CROSSOVER_INT_STATUS (1 << 0x6)
#define ENERGY_DET_INT_STATUS (1 << 0x4)
#define POLARITY_INT_STATUS (1 << 0x1)
#define JABBER_INT_STATUS (1 << 0x0)
/*
* GLOBAL -1 Register fields (SMI Device address 0xF)
*/
// REG_GLOBAL_STATUS 0x1
#define INIT_RDY (1 << 11)
#define AVB_INT (1 << 8)
#define DEV_INT (1 << 7)
#define STATS_DONE (1 << 6)
#define VLAN_PROB (1 << 5)
#define VLAN_DONE (1 << 4)
#define ATU_PROB (1 << 3)
#define ATU_DONE (1 << 2)
#define EE_INT (1 << 0)
#define INIT_RDY (1 << 11)
#define AVB_INT (1 << 8)
#define DEV_INT (1 << 7)
#define STATS_DONE (1 << 6)
#define VLAN_PROB (1 << 5)
#define VLAN_DONE (1 << 4)
#define ATU_PROB (1 << 3)
#define ATU_DONE (1 << 2)
#define EE_INT (1 << 0)
// REG_GLOBAL_CONTROL 0x4
#define SW_RESET (1 << 15)
#define DISCARD_EXCESSIVE (1 << 13)
#define ARP_WO_BROADCAST (1 << 12)
#define MAX_FRAME_SIZE (1 << 10)
#define RELOAD (1 << 9)
#define AVB_INT_EN (1 << 8)
#define DEV_INT_EN (1 << 7)
#define STATS_DONE_INT_EN (1 << 6)
#define VTU_PROB_INT_EN (1 << 5)
#define ATU_DONE_INT_EN (1 << 4)
#define EE_INT_EN (1 << 0)
#define SW_RESET (1 << 15)
#define DISCARD_EXCESSIVE (1 << 13)
#define ARP_WO_BROADCAST (1 << 12)
#define MAX_FRAME_SIZE (1 << 10)
#define RELOAD (1 << 9)
#define AVB_INT_EN (1 << 8)
#define DEV_INT_EN (1 << 7)
#define STATS_DONE_INT_EN (1 << 6)
#define VTU_PROB_INT_EN (1 << 5)
#define ATU_DONE_INT_EN (1 << 4)
#define EE_INT_EN (1 << 0)
/*
* GLOBAL - 2 Register fields (SMI Device address 0x7)
*/
//REG_INTERRUPT_SOURCE 0x0
#define WATCHDOG_INT (1 << 15)
#define JAM_INT (1 << 14)
#define WAKE_EVENT_INT (1 << 12)
#define PHY_4_INT (1 << 4)
#define PHY_3_INT (1 << 3)
#define PHY_2_INT (1 << 2)
#define PHY_1_INT (1 << 1)
#define PHY_0_INT (1 << 0)
// REG_INTERRUPT_SOURCE 0x0
#define WATCHDOG_INT (1 << 15)
#define JAM_INT (1 << 14)
#define WAKE_EVENT_INT (1 << 12)
#define PHY_4_INT (1 << 4)
#define PHY_3_INT (1 << 3)
#define PHY_2_INT (1 << 2)
#define PHY_1_INT (1 << 1)
#define PHY_0_INT (1 << 0)
//REG_INTERRUPT_MASK 0x1
#define WATCHDOG_INT_EN (1 << 15)
#define JAM_INT_EN (1 << 14)
#define WAKE_EVENT_INT_EN (1 << 12)
#define PHY_4_INT_EN (1 << 4)
#define PHY_3_INT_EN (1 << 3)
#define PHY_2_INT_EN (1 << 2)
#define PHY_1_INT_EN (1 << 1)
#define PHY_0_INT_EN (1 << 0)
// REG_INTERRUPT_MASK 0x1
#define WATCHDOG_INT_EN (1 << 15)
#define JAM_INT_EN (1 << 14)
#define WAKE_EVENT_INT_EN (1 << 12)
#define PHY_4_INT_EN (1 << 4)
#define PHY_3_INT_EN (1 << 3)
#define PHY_2_INT_EN (1 << 2)
#define PHY_1_INT_EN (1 << 1)
#define PHY_0_INT_EN (1 << 0)
//REG_C45_PACKET_GEN 0x8030
#define CRC_ENABLE (1 << 6)
#define FRAME_COUNT_EN (1 << 5)
#define FORCE_BURST_STOP (1 << 4)
#define PACKET_GEN_EN (1 << 3)
#define PAYLOAD_TYPE (1 << 2)
#define PACKET_LENGTH (1 << 1)
#define ERROR_PACKET_INJECTION (1 << 0)
// REG_C45_PACKET_GEN 0x8030
#define CRC_ENABLE (1 << 6)
#define FRAME_COUNT_EN (1 << 5)
#define FORCE_BURST_STOP (1 << 4)
#define PACKET_GEN_EN (1 << 3)
#define PAYLOAD_TYPE (1 << 2)
#define PACKET_LENGTH (1 << 1)
#define ERROR_PACKET_INJECTION (1 << 0)
#endif /* _88E6071_REGISTERS_H_ */

105
firmware/ec/inc/devices/adt7481.h
View File

@@ -25,7 +25,7 @@
* to be in extended region(-64<36>C to +191<39>C) otherwise 0 if temperature region
* is in normal range(0<>C to +127<32>C).
*/
#define ADT7481_EXTENDED_FLAG 1
#define ADT7481_EXTENDED_FLAG 1
/*
* 7 - (Mask) - Setting this bit to 1 masks all ALERTs on the ALERT pin.
@@ -41,17 +41,17 @@
* Setting this bit to 1 configures Pin 8 as the THERM2 pin.
* 4 - (Reserved) - Reserved for future use.
* 3 - (Remote 1/2)- Setting this bit to 1 enables the user to read the Remote 2
* values from the Remote 1 registers. When default = 0, Remote 1 temperature
* values and limits are read from these registers.
* 2 - (Temp Range) - Setting this bit to 1 enables the extended temperature
* measurement range of -64<36>C to +191<39>C. When using the default = 0, the
* temperature range is 0<>C to +127<32>C.
* 1 - (Mask R1) - 1 - Setting this bit to 1 masks ALERTs due to the Remote 1
* temperature exceeding a programmed limit. Default = 0.
* 0 - (Mask R2) - 0 - Setting this bit to 1 masks ALERTs due to the Remote 2
* temperature exceeding a programmed limit. Default = 0.
* values from the Remote 1 registers. When default = 0, Remote 1
* temperature values and limits are read from these registers. 2 - (Temp Range)
* - Setting this bit to 1 enables the extended temperature measurement range of
* -64<36>C to +191<39>C. When using the default = 0, the temperature range is 0<>C to
* +127<32>C. 1 - (Mask R1) - 1 - Setting this bit to 1 masks ALERTs due to the
* Remote 1 temperature exceeding a programmed limit. Default = 0. 0 - (Mask R2)
* - 0 - Setting this bit to 1 masks ALERTs due to the Remote 2 temperature
* exceeding a programmed limit. Default = 0.
*/
#define ADT7481_CONFIGURATION_REG_VALUE (ADT7481_EXTENDED_FLAG << 2) /* Set/Clear Only Temp Range bit */
#define ADT7481_CONFIGURATION_REG_VALUE \
(ADT7481_EXTENDED_FLAG << 2) /* Set/Clear Only Temp Range bit */
/*
* 7 - (Averaging) - Setting this bit to 1 disables averaging of the
@@ -81,11 +81,12 @@
* 1010 = 64 15.5 m
* 1011 = Continuous Measurements 73 m (Averaging Enabled)
*/
#define ADT7481_CONVERSION_RATE_REG_VALUE 0x07 /* Set conversion rate to 125ms(default) */
#define ADT7481_CONVERSION_RATE_REG_VALUE \
0x07 /* Set conversion rate to 125ms(default) */
/* ADT7481 Manufacturer Id and Device Id */
#define TEMP_ADT7481_MANF_ID 0x41
#define TEMP_ADT7481_DEV_ID 0x81
#define TEMP_ADT7481_MANF_ID 0x41
#define TEMP_ADT7481_DEV_ID 0x81
/*
* Enumeration of Temperature limit registers
@@ -99,71 +100,71 @@ typedef enum {
/*****************************************************************************
* FUNCTION DECLARATIONS
*****************************************************************************/
ReturnStatus adt7481_get_dev_id(const I2C_Dev *i2c_dev,
uint8_t *devID);
ReturnStatus adt7481_get_mfg_id(const I2C_Dev *i2c_dev,
uint8_t *mfgID);
ePostCode adt7481_probe(const I2C_Dev *i2c_dev,
POSTData *postData);
ReturnStatus adt7481_get_config1(const I2C_Dev *i2c_dev,
uint8_t *configValue);
ReturnStatus adt7481_set_config1(const I2C_Dev *i2c_dev,
uint8_t configValue);
ReturnStatus adt7481_get_dev_id(const I2C_Dev *i2c_dev, uint8_t *devID);
ReturnStatus adt7481_get_mfg_id(const I2C_Dev *i2c_dev, uint8_t *mfgID);
ePostCode adt7481_probe(const I2C_Dev *i2c_dev, POSTData *postData);
ReturnStatus adt7481_get_config1(const I2C_Dev *i2c_dev, uint8_t *configValue);
ReturnStatus adt7481_set_config1(const I2C_Dev *i2c_dev, uint8_t configValue);
ReturnStatus adt7481_get_conv_rate(const I2C_Dev *i2c_dev,
uint8_t *convRateValue);
ReturnStatus adt7481_set_conv_rate(const I2C_Dev *i2c_dev,
uint8_t convRateValue);
ReturnStatus adt7481_get_status1(const I2C_Dev *i2c_dev,
uint8_t *statusValue);
ReturnStatus adt7481_get_status2(const I2C_Dev *i2c_dev,
uint8_t *statusValue);
ReturnStatus adt7481_get_status1(const I2C_Dev *i2c_dev, uint8_t *statusValue);
ReturnStatus adt7481_get_status2(const I2C_Dev *i2c_dev, uint8_t *statusValue);
ReturnStatus adt7481_get_local_temp_val(const I2C_Dev *i2c_dev,
int16_t *tempValue);
ReturnStatus adt7481_get_remote1_temp_val(const I2C_Dev *i2c_dev,
int16_t *tempValue);
ReturnStatus adt7481_get_remote2_temp_val(const I2C_Dev *i2c_dev,
int8_t *tempValue);
ReturnStatus adt7481_get_local_temp_limit(const I2C_Dev *i2c_dev,
eTempSensorADT7481ConfigParamsId limitToConfig,
int16_t* tempLimitValue);
ReturnStatus adt7481_set_local_temp_limit(const I2C_Dev *i2c_dev,
eTempSensorADT7481ConfigParamsId limitToConfig,
int16_t tempLimitValue);
ReturnStatus
adt7481_get_local_temp_limit(const I2C_Dev *i2c_dev,
eTempSensorADT7481ConfigParamsId limitToConfig,
int16_t *tempLimitValue);
ReturnStatus
adt7481_set_local_temp_limit(const I2C_Dev *i2c_dev,
eTempSensorADT7481ConfigParamsId limitToConfig,
int16_t tempLimitValue);
ReturnStatus adt7481_get_remote2_temp_low_limit(const I2C_Dev *i2c_dev,
int8_t* tempLimitValue);
int8_t *tempLimitValue);
ReturnStatus adt7481_get_remote2_temp_high_limit(const I2C_Dev *i2c_dev,
int8_t* tempLimitValue);
int8_t *tempLimitValue);
ReturnStatus adt7481_get_remote2_temp_therm_limit(const I2C_Dev *i2c_dev,
int8_t* tempLimitValue);
ReturnStatus adt7481_get_remote1_temp_limit(const I2C_Dev *i2c_dev,
eTempSensorADT7481ConfigParamsId limitToConfig,
int8_t* tempLimitValue);
int8_t *tempLimitValue);
ReturnStatus
adt7481_get_remote1_temp_limit(const I2C_Dev *i2c_dev,
eTempSensorADT7481ConfigParamsId limitToConfig,
int8_t *tempLimitValue);
ReturnStatus adt7481_set_remote2_temp_low_limit(const I2C_Dev *i2c_dev,
int8_t tempLimitValue);
ReturnStatus adt7481_set_remote2_temp_high_limit(const I2C_Dev *i2c_dev,
int8_t tempLimitValue);
ReturnStatus adt7481_set_remote2_temp_therm_limit(const I2C_Dev *i2c_dev,
int8_t tempLimitValue);
ReturnStatus adt7481_set_remote1_temp_limit(const I2C_Dev *i2c_dev,
eTempSensorADT7481ConfigParamsId limitToConfig,
int8_t tempLimitValue);
ReturnStatus adt7481_get_remote2_temp_limit(const I2C_Dev *i2c_dev,
eTempSensorADT7481ConfigParamsId limitToConfig,
int8_t* tempLimitValue);
ReturnStatus adt7481_set_remote2_temp_limit(const I2C_Dev *i2c_dev,
eTempSensorADT7481ConfigParamsId limitToConfig,
int8_t tempLimitValue);
ReturnStatus
adt7481_set_remote1_temp_limit(const I2C_Dev *i2c_dev,
eTempSensorADT7481ConfigParamsId limitToConfig,
int8_t tempLimitValue);
ReturnStatus
adt7481_get_remote2_temp_limit(const I2C_Dev *i2c_dev,
eTempSensorADT7481ConfigParamsId limitToConfig,
int8_t *tempLimitValue);
ReturnStatus
adt7481_set_remote2_temp_limit(const I2C_Dev *i2c_dev,
eTempSensorADT7481ConfigParamsId limitToConfig,
int8_t tempLimitValue);
ReturnStatus adt7481_get_remote1_temp_offset(const I2C_Dev *i2c_dev,
int16_t* tempOffsetValue);
int16_t *tempOffsetValue);
ReturnStatus adt7481_set_remote1_temp_offset(const I2C_Dev *i2c_dev,
int16_t tempOffsetValue);
ReturnStatus adt7481_get_remote2_temp_offset(const I2C_Dev *i2c_dev,
int16_t* tempOffsetValue);
int16_t *tempOffsetValue);
ReturnStatus adt7481_set_remote2_temp_offset(const I2C_Dev *i2c_dev,
int8_t tempOffsetValue);
ReturnStatus adt7481_get_therm_hysteresis(const I2C_Dev *i2c_dev,
int8_t* tempHysteresisValue);
int8_t *tempHysteresisValue);
ReturnStatus adt7481_set_therm_hysteresis(const I2C_Dev *i2c_dev,
int8_t tempHysteresisValue);

28
firmware/ec/inc/devices/at45db.h
View File

@@ -1,12 +1,12 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*
*/
#ifndef INC_DEVICES_AT45DB_H_
#define INC_DEVICES_AT45DB_H_
@@ -23,8 +23,8 @@ typedef enum AT45DB_Event {
AT45DB_READ_EVENT = 0,
} AT45DB_Event;
typedef void (*AT45DB_CallbackFn) (AT45DB_Event evt, uint16_t value,
void *context);
typedef void (*AT45DB_CallbackFn)(AT45DB_Event evt, uint16_t value,
void *context);
typedef struct AT45DB_Cfg {
SPI_Dev dev;
@@ -43,10 +43,12 @@ typedef struct AT45DB_Dev {
} AT45DB_Dev;
ePostCode at45db_probe(AT45DB_Dev *dev, POSTData *postData);
ReturnStatus at45db_data_read(AT45DB_Dev *dev, uint8_t *data, uint32_t data_size, uint32_t byte, uint32_t page);
ReturnStatus at45db_data_write(AT45DB_Dev *dev, uint8_t *data, uint32_t data_size, uint32_t byte, uint32_t page);
ReturnStatus at45db_data_read(AT45DB_Dev *dev, uint8_t *data,
uint32_t data_size, uint32_t byte, uint32_t page);
ReturnStatus at45db_data_write(AT45DB_Dev *dev, uint8_t *data,
uint32_t data_size, uint32_t byte,
uint32_t page);
ReturnStatus at45db_erasePage(AT45DB_Dev *dev, uint32_t page);
uint8_t at45db_readStatusRegister(AT45DB_Dev *dev);
#endif /* INC_DEVICES_AT45DB_H_ */

2
firmware/ec/inc/devices/dat-xxr5a-pp.h
View File

@@ -27,7 +27,7 @@ typedef struct DATR5APP_Cfg {
OcGpio_Pin pin_4db;
OcGpio_Pin pin_8db;
OcGpio_Pin pin_16db; /* Optional */
//OcGpio_Pin pin_tx_attn_enb;
// OcGpio_Pin pin_tx_attn_enb;
};
OcGpio_Pin pin_group[DATR5APP_PIN_COUNT];
};

12
firmware/ec/inc/devices/debug_ocgpio.h
View File

@@ -11,14 +11,14 @@
#include "drivers/OcGpio.h"
typedef struct __attribute__ ((packed, aligned(1))) {
uint8_t pin;
uint8_t value;
}S_OCGPIO;
typedef struct __attribute__((packed, aligned(1))) {
uint8_t pin;
uint8_t value;
} S_OCGPIO;
typedef struct S_OCGPIO_Cfg {
OcGpio_Port* port;
OcGpio_Port *port;
unsigned int group;
}S_OCGPIO_Cfg;
} S_OCGPIO_Cfg;
#endif /* _OC_GPIO_H_ */

14
firmware/ec/inc/devices/debug_oci2c.h
View File

@@ -11,15 +11,15 @@
#include <stdint.h>
typedef struct __attribute__ ((packed, aligned(1))){
uint8_t slaveAddress;
uint8_t number_of_bytes;
uint8_t reg_address;
uint16_t reg_value;
}S_OCI2C;
typedef struct __attribute__((packed, aligned(1))) {
uint8_t slaveAddress;
uint8_t number_of_bytes;
uint8_t reg_address;
uint16_t reg_value;
} S_OCI2C;
typedef struct S_I2C_Cfg {
unsigned int bus;
}S_I2C_Cfg;
} S_I2C_Cfg;
#endif /* INC_DEVICES_OC_I2C_H_ */

10
firmware/ec/inc/devices/debug_ocmdio.h
View File

@@ -11,13 +11,13 @@
#include <stdint.h>
typedef struct __attribute__ ((packed, aligned(1))){
uint16_t reg_address;
uint16_t reg_value;
}S_OCMDIO;
typedef struct __attribute__((packed, aligned(1))) {
uint16_t reg_address;
uint16_t reg_value;
} S_OCMDIO;
typedef struct S_MDIO_Cfg {
unsigned int port;
}S_MDIO_Cfg;
} S_MDIO_Cfg;
#endif /* INC_DEVICES_OC_MDIO_H_ */

52
firmware/ec/inc/devices/eeprom.h
View File

@@ -19,19 +19,19 @@
/*****************************************************************************
* MACRO DEFINITIONS
*****************************************************************************/
#define OC_TEST_ADDRESS 0xFFFF
#define OC_CONNECT1_SERIAL_INFO 0x01C6
#define OC_CONNECT1_SERIAL_SIZE 0x12
#define OC_GBC_BOARD_INFO 0x01AC
#define OC_GBC_BOARD_INFO_SIZE 0x12
#define OC_GBC_DEVICE_INFO 0x0100 /*TODO: Update offsets*/
#define OC_SDR_BOARD_INFO 0x01AC
#define OC_SDR_BOARD_INFO_SIZE 0x12
#define OC_SDR_DEVICE_INFO 0x0100 /*TODO: Update offsets*/
#define OC_RFFE_BOARD_INFO 0x01AC
#define OC_RFFE_BOARD_INFO_SIZE 0x11
#define OC_RFFE_DEVICE_INFO 0x0100 /*TODO: Update offsets*/
#define OC_DEVICE_INFO_SIZE 0x0A
#define OC_TEST_ADDRESS 0xFFFF
#define OC_CONNECT1_SERIAL_INFO 0x01C6
#define OC_CONNECT1_SERIAL_SIZE 0x12
#define OC_GBC_BOARD_INFO 0x01AC
#define OC_GBC_BOARD_INFO_SIZE 0x12
#define OC_GBC_DEVICE_INFO 0x0100 /*TODO: Update offsets*/
#define OC_SDR_BOARD_INFO 0x01AC
#define OC_SDR_BOARD_INFO_SIZE 0x12
#define OC_SDR_DEVICE_INFO 0x0100 /*TODO: Update offsets*/
#define OC_RFFE_BOARD_INFO 0x01AC
#define OC_RFFE_BOARD_INFO_SIZE 0x11
#define OC_RFFE_DEVICE_INFO 0x0100 /*TODO: Update offsets*/
#define OC_DEVICE_INFO_SIZE 0x0A
/*****************************************************************************
* STRUCT DEFINITIONS
@@ -47,8 +47,8 @@ typedef struct Eeprom_Cfg {
I2C_Dev i2c_dev;
OcGpio_Pin *pin_wp;
EepromDev_Cfg type; /*!< Device specific config (page size, etc) */
OCMPSubsystem ss; /* TODO: The HW config need not know about the subsytem
to be fixed later */
OCMPSubsystem ss; /* TODO: The HW config need not know about the subsytem
to be fixed later */
} Eeprom_Cfg, *Eeprom_Handle;
typedef enum {
@@ -62,31 +62,25 @@ typedef enum {
*****************************************************************************/
bool eeprom_init(Eeprom_Cfg *cfg);
ReturnStatus eeprom_read(const Eeprom_Cfg *cfg,
uint16_t address,
void *buffer,
ReturnStatus eeprom_read(const Eeprom_Cfg *cfg, uint16_t address, void *buffer,
size_t size);
ReturnStatus eeprom_write(const Eeprom_Cfg *cfg,
uint16_t address,
const void *buffer,
size_t size);
ReturnStatus eeprom_write(const Eeprom_Cfg *cfg, uint16_t address,
const void *buffer, size_t size);
ReturnStatus eeprom_disable_write(Eeprom_Cfg *cfg);
ReturnStatus eeprom_enable_write(Eeprom_Cfg *cfg);
ReturnStatus eeprom_read_oc_info(uint8_t * oc_serial);
ReturnStatus eeprom_read_oc_info(uint8_t *oc_serial);
ReturnStatus eeprom_read_board_info(const Eeprom_Cfg *cfg,
uint8_t * rom_info);
ReturnStatus eeprom_read_board_info(const Eeprom_Cfg *cfg, uint8_t *rom_info);
ReturnStatus eeprom_read_device_info_record(const Eeprom_Cfg *cfg,
uint8_t recordNo,
char * device_info);
char *device_info);
ReturnStatus eeprom_write_device_info_record(Eeprom_Cfg *cfg,
uint8_t recordNo,
char * device_info);
ReturnStatus eeprom_write_device_info_record(Eeprom_Cfg *cfg, uint8_t recordNo,
char *device_info);
#endif /* EEPROM_H_ */

106
firmware/ec/inc/devices/eth_sw.h
View File

@@ -19,59 +19,52 @@
/*****************************************************************************
* MACRO DEFINITIONS
*****************************************************************************/
#define ETH_SW_PRODUCT_ID 0x0071
#define PHY_IDENTIFIER 0x0141
#define ETH_SW_PRODUCT_ID 0x0071
#define PHY_IDENTIFIER 0x0141
#define DEFAULT_PHY_INTS (PHY_4_INT_EN | PHY_3_INT_EN | PHY_2_INT_EN |PHY_1_INT_EN | PHY_0_INT_EN)
#define DEFUALT_INT (LINK_CHANGE_INT_EN)
#define DEFAULT_PHY_INTS \
(PHY_4_INT_EN | PHY_3_INT_EN | PHY_2_INT_EN | PHY_1_INT_EN | PHY_0_INT_EN)
#define DEFUALT_INT (LINK_CHANGE_INT_EN)
/*
* MDC MDIO definitions
*/
#define NO_CPU_MODE 1
#define CPU_MODE 0
#define NO_CPU_MODE 1
#define CPU_MODE 0
//#define ETH_SW_ADDR
#define MDIO_PORT GPIO_PORTC_BASE
#define MDC_PIN GPIO_PIN_6
#define MDIO_PIN GPIO_PIN_7
#define MDIO_PORT GPIO_PORTC_BASE
#define MDC_PIN GPIO_PIN_6
#define MDIO_PIN GPIO_PIN_7
#define LAN_MUX_SELECT_PORT GPIO_PORTN_BASE
#define LAN_MUX_SELECT_PIN GPIO_PIN_1
#define LAN_MUX_SELECT_PORT GPIO_PORTN_BASE
#define LAN_MUX_SELECT_PIN GPIO_PIN_1
#define ETH_SW_DEV_SERIAL_NO 1
#define IPPARAMS 4
#define ETH_SW_DEV_SERIAL_NO 1
#define IPPARAMS 4
/*
* Ethernet Components ID. This is the part of the OCMPMsg in componentID field.
*/
typedef enum {
ETH_COMP_ALL = 0x0,
PORT_0, // PORT# 0
ETH_COMP_ALL = 0x0,
PORT_0, // PORT# 0
PORT_1,
PORT_2,
PORT_3,
PORT_4,
ETH_COMPONENT_MAX // Limiter
ETH_COMPONENT_MAX // Limiter
} e_ethernet_component_ID;
typedef enum {
PORT0=0,
PORT0 = 0,
PORT1,
PORT2,
PORT3,
PORT4,
}Eth_Sw_Port;
} Eth_Sw_Port;
typedef enum {
SPEED_10M = 0,
SPEED_100M,
SPEED_AUTONEG
} port_speed;
typedef enum { SPEED_10M = 0, SPEED_100M, SPEED_AUTONEG } port_speed;
typedef enum {
HALF_DUPLEX = 0,
FULL_DUPLEX,
DUPLEX_AUTONEG
} port_duplex;
typedef enum { HALF_DUPLEX = 0, FULL_DUPLEX, DUPLEX_AUTONEG } port_duplex;
typedef enum Eth_Sw_Status {
ETH_SW_STATUS_SPEED = 0x00,
@@ -97,16 +90,16 @@ typedef enum Eth_Sw_Config {
typedef enum Eth_Sw_Alert {
ETH_ALERT_SPEED_CHANGE = 0x01,
ETH_ALERT_DUPLEX_CHANGE = 0x02,
ETH_ALERT_AUTONEG_DONE=0x04,
ETH_ALERT_LINK_CHANGE=0x08,
ETH_ALERT_CROSSOVER_DET=0x10,
ETH_ALERT_ENERGY_DET=0x20,
ETH_ALERT_POLARITY_DET=0x040,
ETH_ALERT_JABBER_DET=0x80
ETH_ALERT_AUTONEG_DONE = 0x04,
ETH_ALERT_LINK_CHANGE = 0x08,
ETH_ALERT_CROSSOVER_DET = 0x10,
ETH_ALERT_ENERGY_DET = 0x20,
ETH_ALERT_POLARITY_DET = 0x040,
ETH_ALERT_JABBER_DET = 0x80
} Eth_Sw_Alert;
typedef enum {
ETH_EVT_SPEED =0x00,
ETH_EVT_SPEED = 0x00,
ETH_EVT_DUPLEX,
ETH_EVT_AUTONEG,
ETH_EVT_LINK,
@@ -114,11 +107,10 @@ typedef enum {
ETH_EVT_ENERGY,
ETH_EVT_POLARITY,
ETH_EVT_JABBER,
}Eth_Sw_Events;
} Eth_Sw_Events;
typedef void (*Eth_Sw_CallbackFn) (Eth_Sw_Events evt, int16_t value,
void *context);
typedef void (*Eth_Sw_CallbackFn)(Eth_Sw_Events evt, int16_t value,
void *context);
typedef struct Eth_Sw_Obj {
Eth_Sw_CallbackFn alert_cb;
@@ -130,7 +122,7 @@ typedef struct Eth_Sw_Dev {
} Eth_Sw_Dev;
typedef struct Eth_Sw_Cfg {
OcGpio_Pin* pin_evt;
OcGpio_Pin *pin_evt;
Eth_Sw_Dev eth_switch;
OcGpio_Pin pin_ec_ethsw_reset;
} Eth_Sw_Cfg;
@@ -143,17 +135,17 @@ typedef struct Eth_cfg {
typedef struct Eth_LoopBack_Params {
uint8_t loopBackType;
}Eth_LoopBack_Params;
} Eth_LoopBack_Params;
typedef struct Eth_PacketGen_Params {
uint16_t reg_value;
}Eth_PacketGen_Params;
} Eth_PacketGen_Params;
typedef struct Eth_TcpClient_Params {
uint8_t ipAddress[IPPARAMS];
uint16_t tcpPort;
uint8_t repeat;
}Eth_TcpClient_Params;
} Eth_TcpClient_Params;
ePostCode eth_sw_probe();
ePostCode eth_sw_init();
@@ -162,28 +154,34 @@ ReturnStatus get_interrupt(uint8_t port);
ReturnStatus eth_sw_get_status_speed(uint8_t port, port_speed *speed);
ReturnStatus eth_sw_get_status_duplex(uint8_t port, port_duplex *duplex);
ReturnStatus eth_sw_get_status_auto_neg(uint8_t port, port_duplex *autoneg_on);
ReturnStatus eth_sw_get_status_sleep_mode(uint8_t port, port_duplex *sleep_mode_en);
ReturnStatus eth_sw_get_status_auto_neg_complete(uint8_t port, port_duplex *autoneg_complete);
ReturnStatus eth_sw_get_status_sleep_mode(uint8_t port,
port_duplex *sleep_mode_en);
ReturnStatus eth_sw_get_status_auto_neg_complete(uint8_t port,
port_duplex *autoneg_complete);
ReturnStatus eth_sw_get_status_link_up(uint8_t port, port_duplex *link_up);
ReturnStatus restart_autoneg(uint8_t port);
ReturnStatus eth_sw_set_config_speed(uint8_t port, port_speed speed);
ReturnStatus eth_sw_set_config_duplex(uint8_t port, port_duplex duplex);
ReturnStatus eth_sw_set_config_power_down(uint8_t port,uint8_t power_down);
ReturnStatus eth_sw_set_config_sleep_mode_enable(uint8_t port,uint8_t sleep_mode_en);
ReturnStatus eth_sw_set_config_power_down(uint8_t port, uint8_t power_down);
ReturnStatus eth_sw_set_config_sleep_mode_enable(uint8_t port,
uint8_t sleep_mode_en);
ReturnStatus eth_sw_set_config_restart_neg(uint8_t port);
ReturnStatus eth_sw_set_config_interrupt_enable(uint8_t port, uint8_t *interrupt_mask);
ReturnStatus eth_sw_set_config_interrupt_enable(uint8_t port,
uint8_t *interrupt_mask);
ReturnStatus eth_sw_set_config_soft_reset(uint8_t port);
ReturnStatus eth_sw_get_config_speed(uint8_t port, port_speed* speed);
ReturnStatus eth_sw_get_config_duplex(uint8_t port, port_duplex* duplex);
ReturnStatus eth_sw_get_config_power_down(uint8_t port, uint8_t* power_dwn);
ReturnStatus eth_sw_get_config_sleep_mode(uint8_t port, uint8_t* sleep_mode);
ReturnStatus eth_sw_get_config_interrupt_enable(uint8_t port, uint8_t* interrupt_enb);
ReturnStatus eth_sw_get_config_speed(uint8_t port, port_speed *speed);
ReturnStatus eth_sw_get_config_duplex(uint8_t port, port_duplex *duplex);
ReturnStatus eth_sw_get_config_power_down(uint8_t port, uint8_t *power_dwn);
ReturnStatus eth_sw_get_config_sleep_mode(uint8_t port, uint8_t *sleep_mode);
ReturnStatus eth_sw_get_config_interrupt_enable(uint8_t port,
uint8_t *interrupt_enb);
ReturnStatus eth_sw_enable_loopback(void *driver, void *params);
ReturnStatus eth_sw_disable_loopback(void *driver, void *params);
ReturnStatus eth_sw_enable_macloopback(uint8_t port);
ReturnStatus eth_sw_disable_macloopback(uint8_t port);
ReturnStatus eth_sw_enable_packet_gen(void *driver, void *params);
ReturnStatus eth_sw_disable_packet_gen(void *driver);
void eth_sw_setAlertHandler(Eth_cfg *ethCfg, Eth_Sw_CallbackFn alert_cb, void *cb_context);
void eth_sw_setAlertHandler(Eth_cfg *ethCfg, Eth_Sw_CallbackFn alert_cb,
void *cb_context);
#endif /* INC_DEVICES_ETH_SW_H_ */

33
firmware/ec/inc/devices/ext_battery.h
View File

@@ -12,27 +12,28 @@
/*****************************************************************************
* MACRO DEFINITIONS
*****************************************************************************/
#define PWR_LEAD_ACID_BATT_DEV_TEMP_SENS_ADDR 0x18
#define PWR_LEAD_ACID_BATT_DEV_TEMP_SENS_ADDR 0x18
#define PWR_EXT_BATT_RSNSB 3 //milli ohms
#define PWR_EXT_BATT_RSNSI 2 //milli ohms
#define PWR_EXT_BATT_RSNSB 3 // milli ohms
#define PWR_EXT_BATT_RSNSI 2 // milli ohms
/*
* External Battery Temperature sensors Low, High and Critical Temeprature Alert Limits
* External Battery Temperature sensors Low, High and Critical Temeprature Alert
* Limits
*/
#define PWR_EXT_BATT_TEMP_LOW_LIMIT -20 //(in Celcius)
#define PWR_EXT_BATT_TEMP_HIGH_LIMIT 75 //(in Celcius)
#define PWR_EXT_BATT_TEMP_CRITICAL_LIMIT 80 //(in Celcius)
#define PWR_EXT_BATT_DIE_TEMP_LIMIT 60
#define PWR_EXT_BATT_TEMP_LOW_LIMIT -20 //(in Celcius)
#define PWR_EXT_BATT_TEMP_HIGH_LIMIT 75 //(in Celcius)
#define PWR_EXT_BATT_TEMP_CRITICAL_LIMIT 80 //(in Celcius)
#define PWR_EXT_BATT_DIE_TEMP_LIMIT 60
/* Config parameters for External battery charger */
#define PWR_EXTBATT_ICHARGE_VAL 10660 //milliAmps
#define PWR_EXTBATT_VCHARGE_VAL 12000 //milliVolts
#define PWR_EXTBATT_UNDERVOLTAGE_VAL 9500 //milliVolts
#define PWR_EXTBATT_OVERVOLTAGE_VAL 13800 //milliVolts
#define PWR_EXTBATT_INPUTBATTUNDERVOLATGE_VAL 16200 //milliVolts
#define PWR_EXTBATT_INPUTHICURRENT_VAL 17000 //milliAmps
#define PWR_EXTBATT_LOWBATTCURRENT_VAL 100 //milliAmps
#define PWR_EXTBATT_INPUTCURRENTLIMIT_VAL 16500 //milliAmps
#define PWR_EXTBATT_ICHARGE_VAL 10660 // milliAmps
#define PWR_EXTBATT_VCHARGE_VAL 12000 // milliVolts
#define PWR_EXTBATT_UNDERVOLTAGE_VAL 9500 // milliVolts
#define PWR_EXTBATT_OVERVOLTAGE_VAL 13800 // milliVolts
#define PWR_EXTBATT_INPUTBATTUNDERVOLATGE_VAL 16200 // milliVolts
#define PWR_EXTBATT_INPUTHICURRENT_VAL 17000 // milliAmps
#define PWR_EXTBATT_LOWBATTCURRENT_VAL 100 // milliAmps
#define PWR_EXTBATT_INPUTCURRENTLIMIT_VAL 16500 // milliAmps
#endif /* EXT_BATTERY_H_ */

2
firmware/ec/inc/devices/fe_param.h
View File

@@ -9,6 +9,6 @@
#ifndef FE_PARAM_H_
#define FE_PARAM_H_
//TODO: As of now no declarations are present here
// TODO: As of now no declarations are present here
#endif /* INC_DEVICES_FE_PARAM_H_ */

54
firmware/ec/inc/devices/ina226.h
View File

@@ -21,25 +21,30 @@
*****************************************************************************/
/* Mask/Enable Register Bits */
#define INA_ALERT_EN_MASK 0xF800 /* Upper 5 bits are the enable bits */
#define INA_MSK_SOL (1 << 15) /* Shunt over-voltage */
#define INA_MSK_SUL (1 << 14) /* Shunt under-voltage */
#define INA_MSK_BOL (1 << 13) /* Bus over-voltage */
#define INA_MSK_BUL (1 << 12) /* Bus under-voltage */
#define INA_MSK_POL (1 << 11) /* Power over limit */
#define INA_MSK_CNVR (1 << 10) /* Conversion ready - enable alert when
* CVRF is set (ready for next conversion) */
#define INA_MSK_SOL (1 << 15) /* Shunt over-voltage */
#define INA_MSK_SUL (1 << 14) /* Shunt under-voltage */
#define INA_MSK_BOL (1 << 13) /* Bus over-voltage */
#define INA_MSK_BUL (1 << 12) /* Bus under-voltage */
#define INA_MSK_POL (1 << 11) /* Power over limit */
#define INA_MSK_CNVR \
(1 << 10) /* Conversion ready - enable alert when \
* CVRF is set (ready for next conversion) */
#define INA_MSK_AFF (1 << 4) /* Alert Function Flag (caused by alert)
* In latch mode, cleared on mask read */
#define INA_MSK_CVRF (1 << 3) /* Conversion Ready Flag, cleared when
* writing to cfg reg or mask read */
#define INA_MSK_OVF (1 << 2) /* Math Overflow Flag (data may be invalid) */
#define INA_MSK_APOL (1 << 1) /* Alert Polarity (1 = invert, active high) */
#define INA_MSK_LEN (1 << 0) /* Alert Latch Enable
* 1 Latch (alert only cleared by read to msk)
* 0 Transparent (auto-clear on fault clear) */
#define INA_MSK_AFF \
(1 << 4) /* Alert Function Flag (caused by alert) \
* In latch mode, cleared on mask read */
#define INA_MSK_CVRF \
(1 << 3) /* Conversion Ready Flag, cleared when \
* writing to cfg reg or mask read */
#define INA_MSK_OVF (1 << 2) /* Math Overflow Flag (data may be invalid) */
#define INA_MSK_APOL (1 << 1) /* Alert Polarity (1 = invert, active high) */
#define INA_MSK_LEN \
(1 << 0) /* Alert Latch Enable \
* 1 Latch (alert only cleared by read to msk) \
* 0 Transparent (auto-clear on fault clear) */
#define INA_HYSTERESIS 30 /* 30mA TODO: need to make more robust, maybe percentage based */
#define INA_HYSTERESIS \
30 /* 30mA TODO: need to make more robust, maybe percentage based */
/*****************************************************************************
* STRUCT/ENUM DEFINITIONS
@@ -56,8 +61,8 @@ typedef enum INA226_Event {
INA226_EVT_CUL, /* Current under limit - based on SUL */
} INA226_Event;
typedef void (*INA226_CallbackFn) (INA226_Event evt, uint16_t value,
void *context);
typedef void (*INA226_CallbackFn)(INA226_Event evt, uint16_t value,
void *context);
typedef struct INA226_Cfg {
I2C_Dev dev;
@@ -78,13 +83,12 @@ typedef struct INA226_Dev {
/*****************************************************************************
* FUNCTION DECLARATIONS
*****************************************************************************/
ReturnStatus ina226_readCurrentLim(INA226_Dev *dev, uint16_t* currLimit);
ReturnStatus ina226_readCurrentLim(INA226_Dev *dev, uint16_t *currLimit);
ReturnStatus ina226_setCurrentLim(INA226_Dev *dev, uint16_t currLimit);
ReturnStatus ina226_readBusVoltage(INA226_Dev *dev, uint16_t* busVoltValue);
ReturnStatus ina226_readShuntVoltage(INA226_Dev *dev,
uint16_t* shuntVoltValue);
ReturnStatus ina226_readCurrent(INA226_Dev *dev, uint16_t* currValue);
ReturnStatus ina226_readPower(INA226_Dev *dev, uint16_t* powValue);
ReturnStatus ina226_readBusVoltage(INA226_Dev *dev, uint16_t *busVoltValue);
ReturnStatus ina226_readShuntVoltage(INA226_Dev *dev, uint16_t *shuntVoltValue);
ReturnStatus ina226_readCurrent(INA226_Dev *dev, uint16_t *currValue);
ReturnStatus ina226_readPower(INA226_Dev *dev, uint16_t *powValue);
ReturnStatus ina226_init(INA226_Dev *dev);
void ina226_setAlertHandler(INA226_Dev *dev, INA226_CallbackFn alert_cb,
void *cb_context);

16
firmware/ec/inc/devices/int_battery.h
View File

@@ -12,15 +12,15 @@
/*****************************************************************************
* MACRO DEFINITIONS
*****************************************************************************/
#define PWR_INT_BATT_RSNSB 30 //milli ohms
#define PWR_INT_BATT_RSNSI 7 //milli ohms
#define PWR_INT_BATT_RSNSB 30 // milli ohms
#define PWR_INT_BATT_RSNSI 7 // milli ohms
/* Config parameters for Internal battery charger */
#define PWR_INTBATT_UNDERVOLTAGE_VAL 9000 //milliVolts
#define PWR_INTBATT_OVERVOLTAGE_VAL 12600 //milliVolts
#define PWR_INTBATT_INPUTUNDERVOLATGE_VAL 16200 //milliVolts
#define PWR_INTBATT_INPUTOVERCURRENT_VAL 5000 //milliAmps
#define PWR_INTBATT_LOWBATTERYCURRENT_VAL 100 //milliAmps
#define PWR_INTBATT_INPUTCURRENTLIMIT_VAL 5570 //milliAmps
#define PWR_INTBATT_UNDERVOLTAGE_VAL 9000 // milliVolts
#define PWR_INTBATT_OVERVOLTAGE_VAL 12600 // milliVolts
#define PWR_INTBATT_INPUTUNDERVOLATGE_VAL 16200 // milliVolts
#define PWR_INTBATT_INPUTOVERCURRENT_VAL 5000 // milliAmps
#define PWR_INTBATT_LOWBATTERYCURRENT_VAL 100 // milliAmps
#define PWR_INTBATT_INPUTCURRENTLIMIT_VAL 5570 // milliAmps
#endif /* INT_BATTERY_H_ */

18
firmware/ec/inc/devices/led.h
View File

@@ -22,34 +22,30 @@
/*****************************************************************************
* MACRO DEFINITIONS
*****************************************************************************/
#define LED_OFF 0xFF
#define LED_OFF 0xFF
/* ClkX = fOSC/(2^(RegMisc[6:4]-1); 0x50-125kHz, 0x40-250KHz, 0x30-500KHz,
* 0x20-1MHz, 0x10-2MHz; Fading - Linear */
#define REG_MISC_VALUE 0x24
#define REG_MISC_VALUE 0x24
/* 4:0 => ON Time of IO[X]; If 0 : TOnX = Infinite;
* 1 - 15 : TOnX = 64 * RegTOnX * (255/ClkX);
* 16 - 31 : TOnX = 512 * RegTOnX * (255/ClkX) */
#define REG_T_ON_VALUE 0x10
#define REG_T_ON_VALUE 0x10
/* 7:3 - OFF Time of IO[X]; If 0 : TOffX = Infinite;
* 1 - 15 : TOffX = 64 * RegOffX[7:3] * (255/ClkX);
* 16 - 31 : TOffX = 512 * RegOffX[ 7:3] * (255/ClkX) */
/* 2:0 - OFF Intensity of IO[X] = >Linear mode : IOffX = 4 x RegOff[2:0] */
#define REG_OFF_VALUE 0x80
#define REG_OFF_VALUE 0x80
#define HCI_LED_TOTAL_NOS 14
#define HCI_LED_TOTAL_NOS 14
/*****************************************************************************
* STRUCT/ENUM DEFINITIONS
*****************************************************************************/
/* LED Test Params */
typedef enum {
HCI_LED_OFF = 0,
HCI_LED_RED,
HCI_LED_GREEN
} ledTestParam;
typedef enum { HCI_LED_OFF = 0, HCI_LED_RED, HCI_LED_GREEN } ledTestParam;
typedef enum {
HCI_LED_1 = 0,
@@ -86,6 +82,6 @@ ReturnStatus hci_led_turnon_red(const HciLedCfg *driver);
ReturnStatus hci_led_turnoff_all(const HciLedCfg *driver);
ReturnStatus hci_led_system_boot(const HciLedCfg *driver);
ReturnStatus led_init(const HciLedCfg *driver);
ePostCode led_probe(const HciLedCfg *driver,POSTData* postData);
ePostCode led_probe(const HciLedCfg *driver, POSTData *postData);
#endif /* INA226_H_ */

73
firmware/ec/inc/devices/ltc4015.h
View File

@@ -22,24 +22,25 @@
*****************************************************************************/
/* Mask/Enable Register Bits */
#define LTC4015_ALERT_EN_MASK 0xFFFF /* Bits 15-0 are the enable bits(except bit 14) */
#define LTC4015_MSK_MSRV (1 << 15) /* Measurement system results valid */
#define LTC4015_MSK_QCL (1 << 13) /* QCOUNT Low alert */
#define LTC4015_MSK_QCH (1 << 12) /* QCOUNT High alert */
#define LTC4015_MSK_BVL (1 << 11) /* Battery voltage Low alert */
#define LTC4015_MSK_BVH (1 << 10) /* Battery voltage High alert */
#define LTC4015_MSK_IVL (1 << 9) /* Input voltage Low alert */
#define LTC4015_MSK_IVH (1 << 8) /* Input voltage High alert */
#define LTC4015_MSK_SVL (1 << 7) /* System voltage Low alert */
#define LTC4015_MSK_SVH (1 << 6) /* System voltage High alert */
#define LTC4015_MSK_ICH (1 << 5) /* Input current High alert */
#define LTC4015_MSK_BCL (1 << 4) /* Battery current Low alert */
#define LTC4015_MSK_DTH (1 << 3) /* Die temperature High alert */
#define LTC4015_MSK_BSRH (1 << 2) /* BSR High alert */
#define LTC4015_MSK_NTCH (1 << 1) /* NTC ratio High alert */
#define LTC4015_MSK_NTCL (1 << 0) /* NTC ratio Low alert */
#define LTC4015_ALERT_EN_MASK \
0xFFFF /* Bits 15-0 are the enable bits(except bit 14) */
#define LTC4015_MSK_MSRV (1 << 15) /* Measurement system results valid */
#define LTC4015_MSK_QCL (1 << 13) /* QCOUNT Low alert */
#define LTC4015_MSK_QCH (1 << 12) /* QCOUNT High alert */
#define LTC4015_MSK_BVL (1 << 11) /* Battery voltage Low alert */
#define LTC4015_MSK_BVH (1 << 10) /* Battery voltage High alert */
#define LTC4015_MSK_IVL (1 << 9) /* Input voltage Low alert */
#define LTC4015_MSK_IVH (1 << 8) /* Input voltage High alert */
#define LTC4015_MSK_SVL (1 << 7) /* System voltage Low alert */
#define LTC4015_MSK_SVH (1 << 6) /* System voltage High alert */
#define LTC4015_MSK_ICH (1 << 5) /* Input current High alert */
#define LTC4015_MSK_BCL (1 << 4) /* Battery current Low alert */
#define LTC4015_MSK_DTH (1 << 3) /* Die temperature High alert */
#define LTC4015_MSK_BSRH (1 << 2) /* BSR High alert */
#define LTC4015_MSK_NTCH (1 << 1) /* NTC ratio High alert */
#define LTC4015_MSK_NTCL (1 << 0) /* NTC ratio Low alert */
#define LTC4015_MSK_BMFA (1 << 1) /* Battery Missing Fault alert */
#define LTC4015_MSK_BMFA (1 << 1) /* Battery Missing Fault alert */
#define LTC4015_CHARGER_ENABLED (1 << 13)
@@ -76,14 +77,15 @@ typedef enum LTC4015_Event {
LTC4015_EVT_BMFA = LTC4015_MSK_BMFA, /* Battery Missing Fault alert */
} LTC4015_Event;
typedef void (*LTC4015_CallbackFn) (LTC4015_Event evt, int16_t value,
typedef void (*LTC4015_CallbackFn)(LTC4015_Event evt, int16_t value,
void *context);
typedef struct LTC4015_HWCfg {
I2C_Dev i2c_dev;
/* TODO: this can be read from the IC itself */
LTC4015_Chem chem; /* Battery chemistry we're controlling (verified during init) */
LTC4015_Chem
chem; /* Battery chemistry we're controlling (verified during init) */
uint8_t r_snsb; /* Value of SNSB resistor in milli-ohms */
uint8_t r_snsi; /* Value of SNSI resistor in milli-ohms */
@@ -108,8 +110,7 @@ typedef struct LTC4015_Dev {
/*****************************************************************************
* FUNCTION DECLARATIONS
*****************************************************************************/
ReturnStatus LTC4015_cfg_icharge(LTC4015_Dev *dev,
uint16_t max_chargeCurrent);
ReturnStatus LTC4015_cfg_icharge(LTC4015_Dev *dev, uint16_t max_chargeCurrent);
ReturnStatus LTC4015_get_cfg_icharge(LTC4015_Dev *dev,
uint16_t *max_chargeCurrent);
@@ -151,10 +152,10 @@ ReturnStatus LTC4015_get_cfg_battery_current_low(LTC4015_Dev *dev,
int16_t *lowbattCurrent);
ReturnStatus LTC4015_cfg_die_temperature_high(LTC4015_Dev *dev,
int16_t dieTemp);
int16_t dieTemp);
ReturnStatus LTC4015_get_cfg_die_temperature_high(LTC4015_Dev *dev,
int16_t *dieTemp);
int16_t *dieTemp);
ReturnStatus LTC4015_cfg_input_current_limit(LTC4015_Dev *dev,
uint16_t inputCurrentLimit);
@@ -162,34 +163,26 @@ ReturnStatus LTC4015_cfg_input_current_limit(LTC4015_Dev *dev,
ReturnStatus LTC4015_get_cfg_input_current_limit(LTC4015_Dev *dev,
uint16_t *currentLimit);
ReturnStatus LTC4015_get_die_temperature(LTC4015_Dev *dev,
int16_t *dieTemp);
ReturnStatus LTC4015_get_die_temperature(LTC4015_Dev *dev, int16_t *dieTemp);
ReturnStatus LTC4015_get_battery_current(LTC4015_Dev *dev,
int16_t *iBatt);
ReturnStatus LTC4015_get_battery_current(LTC4015_Dev *dev, int16_t *iBatt);
ReturnStatus LTC4015_get_input_current(LTC4015_Dev *dev,
int16_t *iIn);
ReturnStatus LTC4015_get_input_current(LTC4015_Dev *dev, int16_t *iIn);
ReturnStatus LTC4015_get_battery_voltage(LTC4015_Dev *dev,
int16_t *vbat);
ReturnStatus LTC4015_get_battery_voltage(LTC4015_Dev *dev, int16_t *vbat);
ReturnStatus LTC4015_get_input_voltage(LTC4015_Dev *dev,
int16_t *vIn);
ReturnStatus LTC4015_get_input_voltage(LTC4015_Dev *dev, int16_t *vIn);
ReturnStatus LTC4015_get_system_voltage(LTC4015_Dev *dev,
int16_t *vSys);
ReturnStatus LTC4015_get_system_voltage(LTC4015_Dev *dev, int16_t *vSys);
ReturnStatus LTC4015_get_icharge_dac(LTC4015_Dev *dev,
int16_t *ichargeDac);
ReturnStatus LTC4015_get_icharge_dac(LTC4015_Dev *dev, int16_t *ichargeDac);
ReturnStatus LTC4015_get_bat_presence(LTC4015_Dev *dev,
bool *present);
ReturnStatus LTC4015_get_bat_presence(LTC4015_Dev *dev, bool *present);
ReturnStatus LTC4015_init(LTC4015_Dev *dev);
void LTC4015_setAlertHandler(LTC4015_Dev *dev, LTC4015_CallbackFn alert_cb,
void *cb_context);
void *cb_context);
ReturnStatus LTC4015_enableLimitAlerts(LTC4015_Dev *dev, uint16_t alert_mask);

160
firmware/ec/inc/devices/ltc4274.h
View File

@@ -20,52 +20,50 @@
#include <ti/sysbios/gates/GateMutex.h>
/* PSE Configuration */
#define LTC4274_INTERRUPT_MASK 0x00
#define LTC4274_OPERATING_MODE_SET 0x03
#define LTC4274_DETCET_CLASS_ENABLE 0x11
#define LTC4274_MISC_CONF 0xD1
#define LTC4274_INTERRUPT_MASK 0x00
#define LTC4274_OPERATING_MODE_SET 0x03
#define LTC4274_DETCET_CLASS_ENABLE 0x11
#define LTC4274_MISC_CONF 0xD1
/* PSE operating modes */
#define LTC4274_SHUTDOWN_MODE 0x00
#define LTC4274_MANUAL_MODE 0x01
#define LTC4274_SEMIAUTO_MODE 0x02
#define LTC4274_AUTO_MODE 0x03
#define LTC4274_SHUTDOWN_MODE 0x00
#define LTC4274_MANUAL_MODE 0x01
#define LTC4274_SEMIAUTO_MODE 0x02
#define LTC4274_AUTO_MODE 0x03
#define LTC4274_INTERRUPT_ENABLE 0x80
#define LTC4274_DETECT_ENABLE 0x40
#define LTC4274_FAST_IV 0x20
#define LTC4274_MSD_MASK 0x01
#define LTC4274_INTERRUPT_ENABLE 0x80
#define LTC4274_DETECT_ENABLE 0x40
#define LTC4274_FAST_IV 0x20
#define LTC4274_MSD_MASK 0x01
#define LTC4274_HP_ENABLE 0x11
#define LTC4274_HP_ENABLE 0x11
/* POE Device Info */
#define LTC4274_DEV_ID 0x0C
#define LTC4274_ADDRESS 0x2F
#define LTC4274_LTEPOE_90W 0x0E
#define LTC4274_DEV_ID 0x0C
#define LTC4274_ADDRESS 0x2F
#define LTC4274_LTEPOE_90W 0x0E
#define LTC4274_DEVID(x) (x>>3)
#define LTC4274_PWRGD(x) ((x&0x10)>>4)
#define LTC4374_CLASS(x) ((x&0xF0)>>4) /*if MSB is set it specifies LTEPOE++ device*/
#define LTC4374_DETECT(x) ((x&0x07))
#define LTC4274_DETECTION_COMPLETE(x) (x&0x01)
#define LTC4274_CLASSIFICATION_COMPLETE(x) (x&0x10)
#define LTC4274_DEVID(x) (x >> 3)
#define LTC4274_PWRGD(x) ((x & 0x10) >> 4)
#define LTC4374_CLASS(x) \
((x & 0xF0) >> 4) /*if MSB is set it specifies LTEPOE++ device*/
#define LTC4374_DETECT(x) ((x & 0x07))
#define LTC4274_DETECTION_COMPLETE(x) (x & 0x01)
#define LTC4274_CLASSIFICATION_COMPLETE(x) (x & 0x10)
typedef enum LTC4274_Event {
LTC4274_EVT_SUPPLY = 1 << 7,
LTC4274_EVT_TSTART = 1 << 6,
LTC4274_EVT_TCUT = 1 << 5,
LTC4274_EVT_CLASS = 1 << 4,
LTC4274_EVT_DETECTION = 1 << 3,
LTC4274_EVT_DISCONNECT = 1 << 2,
LTC4274_EVT_POWERGOOD = 1 << 1,
LTC4274_EVT_SUPPLY = 1 << 7,
LTC4274_EVT_TSTART = 1 << 6,
LTC4274_EVT_TCUT = 1 << 5,
LTC4274_EVT_CLASS = 1 << 4,
LTC4274_EVT_DETECTION = 1 << 3,
LTC4274_EVT_DISCONNECT = 1 << 2,
LTC4274_EVT_POWERGOOD = 1 << 1,
LTC4274_EVT_POWER_ENABLE = 1 << 0,
LTC4274_EVT_NONE = 0,
LTC4274_EVT_NONE = 0,
} LTC4274_Event; // From LTC4274 Datasheet, Interrupts table
typedef enum {
LTC4274_POWERGOOD = 0,
LTC4274_POWERGOOD_NOTOK
} ePSEPowerState;
typedef enum { LTC4274_POWERGOOD = 0, LTC4274_POWERGOOD_NOTOK } ePSEPowerState;
typedef enum {
LTC4274_DETECT_UNKOWN = 0,
@@ -87,33 +85,29 @@ typedef enum {
LTC4274_CLASSTYPE_RESERVED,
LTC4274_CLASSTYPE_0,
LTC4274_OVERCURRENT,
LTC4274_LTEPOE_TYPE_52_7W =0x09,
LTC4274_LTEPOE_TYPE_70W =0x0a,
LTC4274_LTEPOE_TYPE_90W=0x0b,
LTC4274_LTEPOE_TYPE_38_7W=0xe,
LTC4274_LTEPOE_TYPE_52_7W = 0x09,
LTC4274_LTEPOE_TYPE_70W = 0x0a,
LTC4274_LTEPOE_TYPE_90W = 0x0b,
LTC4274_LTEPOE_TYPE_38_7W = 0xe,
LTC4274_LTEPOE_RESERVED,
LTC4274_CLASS_ERROR
} ePSEClassType;
typedef enum {
LTC4274_STATE_OK = 0,
LTC4274_STATE_NOTOK
} ePSEState;
typedef enum { LTC4274_STATE_OK = 0, LTC4274_STATE_NOTOK } ePSEState;
typedef enum {
LTC4274_NO_ACTIVE_ALERT = 0x00,
LTC4274_POWER_ENABLE_ALERT = 0x01,
LTC4274_POWERGOOD_ALERT = 0x02,
LTC4274_DISCONNECT_ALERT = 0x04,
LTC4274_DETECTION_ALERT = 0x08,
LTC4274_CLASS_ALERT = 0x10,
LTC4274_TCUT_ALERT = 0x20,
LTC4274_TSTART_ALERT = 0x40,
LTC4274_SUPPLY_ALERT = 0x80
LTC4274_NO_ACTIVE_ALERT = 0x00,
LTC4274_POWER_ENABLE_ALERT = 0x01,
LTC4274_POWERGOOD_ALERT = 0x02,
LTC4274_DISCONNECT_ALERT = 0x04,
LTC4274_DETECTION_ALERT = 0x08,
LTC4274_CLASS_ALERT = 0x10,
LTC4274_TCUT_ALERT = 0x20,
LTC4274_TSTART_ALERT = 0x40,
LTC4274_SUPPLY_ALERT = 0x80
} ePSEAlert;
typedef void (*LTC4274_CallbackFn) (LTC4274_Event evt,
void *context);
typedef void (*LTC4274_CallbackFn)(LTC4274_Event evt, void *context);
typedef struct LTC4274_Cfg {
I2C_Dev i2c_dev;
@@ -132,34 +126,44 @@ typedef struct LTC4274_Dev {
LTC4274_Obj obj;
} LTC4274_Dev;
ReturnStatus ltc4274_set_cfg_operation_mode(const I2C_Dev *i2c_dev, uint8_t operatingMode);
ReturnStatus ltc4274_get_operation_mode(const I2C_Dev *i2c_dev, uint8_t *operatingMode);
ReturnStatus ltc4274_set_cfg_detect_enable(const I2C_Dev *i2c_dev, uint8_t detectEnable);
ReturnStatus ltc4274_get_detect_enable(const I2C_Dev *i2c_dev, uint8_t *detectVal);
ReturnStatus ltc4274_set_interrupt_mask(const I2C_Dev *i2c_dev, uint8_t interruptMask);
ReturnStatus ltc4274_get_interrupt_mask(const I2C_Dev *i2c_dev, uint8_t *intrMask);
ReturnStatus ltc4274_set_cfg_operation_mode(const I2C_Dev *i2c_dev,
uint8_t operatingMode);
ReturnStatus ltc4274_get_operation_mode(const I2C_Dev *i2c_dev,
uint8_t *operatingMode);
ReturnStatus ltc4274_set_cfg_detect_enable(const I2C_Dev *i2c_dev,
uint8_t detectEnable);
ReturnStatus ltc4274_get_detect_enable(const I2C_Dev *i2c_dev,
uint8_t *detectVal);
ReturnStatus ltc4274_set_interrupt_mask(const I2C_Dev *i2c_dev,
uint8_t interruptMask);
ReturnStatus ltc4274_get_interrupt_mask(const I2C_Dev *i2c_dev,
uint8_t *intrMask);
ReturnStatus ltc4274_cfg_interrupt_enable(const I2C_Dev *i2c_dev, bool enable);
ReturnStatus ltc4274_get_interrupt_enable(const I2C_Dev *i2c_dev, uint8_t *interruptEnable);
ReturnStatus ltc4274_set_cfg_pshp_feature(const I2C_Dev *i2c_dev, uint8_t hpEnable);
ReturnStatus ltc4274_get_pshp_feature(const I2C_Dev *i2c_dev, uint8_t *hpEnable);
ReturnStatus ltc4274_get_detection_status(const I2C_Dev *i2c_dev, ePSEDetection *pseDetect);
ReturnStatus ltc4274_get_class_status(const I2C_Dev *i2c_dev, ePSEClassType *pseClass);
ReturnStatus ltc4274_get_powergood_status(const I2C_Dev *i2c_dev, uint8_t *psePwrGood);
void ltc4274_set_alert_handler(LTC4274_Dev *dev, LTC4274_CallbackFn alert_cb, void *cb_context);
ReturnStatus ltc4274_clear_interrupt( const I2C_Dev *i2c_dev,
uint8_t *pwrEvent,
uint8_t *overCurrent,
uint8_t *supply);
ReturnStatus ltc4274_get_interrupt_enable(const I2C_Dev *i2c_dev,
uint8_t *interruptEnable);
ReturnStatus ltc4274_set_cfg_pshp_feature(const I2C_Dev *i2c_dev,
uint8_t hpEnable);
ReturnStatus ltc4274_get_pshp_feature(const I2C_Dev *i2c_dev,
uint8_t *hpEnable);
ReturnStatus ltc4274_get_detection_status(const I2C_Dev *i2c_dev,
ePSEDetection *pseDetect);
ReturnStatus ltc4274_get_class_status(const I2C_Dev *i2c_dev,
ePSEClassType *pseClass);
ReturnStatus ltc4274_get_powergood_status(const I2C_Dev *i2c_dev,
uint8_t *psePwrGood);
void ltc4274_set_alert_handler(LTC4274_Dev *dev, LTC4274_CallbackFn alert_cb,
void *cb_context);
ReturnStatus ltc4274_clear_interrupt(const I2C_Dev *i2c_dev, uint8_t *pwrEvent,
uint8_t *overCurrent, uint8_t *supply);
ReturnStatus ltc4274_get_interrupt_status(const I2C_Dev *i2c_dev, uint8_t *val);
ReturnStatus ltc4274_debug_write(const I2C_Dev *i2c_dev,
uint8_t reg_address, uint8_t value);
ReturnStatus ltc4274_debug_read(const I2C_Dev *i2c_dev,
uint8_t reg_address, uint8_t *value);
ReturnStatus ltc4274_debug_write(const I2C_Dev *i2c_dev, uint8_t reg_address,
uint8_t value);
ReturnStatus ltc4274_debug_read(const I2C_Dev *i2c_dev, uint8_t reg_address,
uint8_t *value);
void ltc4274_enable(LTC4274_Dev *dev, uint8_t enableVal);
ReturnStatus ltc4274_get_devid(const I2C_Dev *i2c_dev,
uint8_t *devID);
ReturnStatus ltc4274_detect(const I2C_Dev *i2c_dev,
uint8_t *detect, uint8_t *val);
ReturnStatus ltc4274_get_devid(const I2C_Dev *i2c_dev, uint8_t *devID);
ReturnStatus ltc4274_detect(const I2C_Dev *i2c_dev, uint8_t *detect,
uint8_t *val);
void ltc4274_config(LTC4274_Dev *dev);
ePostCode ltc4274_probe(const LTC4274_Dev *i2c_dev, POSTData *postData);
void ltc4274_init(LTC4274_Dev *dev);

36
firmware/ec/inc/devices/ltc4275.h
View File

@@ -21,12 +21,9 @@
typedef enum {
LTC4275_STATUS_CLASS = 0x00,
LTC4275_STATUS_POWERGOOD = 0x01,
}eltc4275StatusParamId;
} eltc4275StatusParamId;
typedef enum {
LTC4275_POWERGOOD = 0,
LTC4275_POWERGOOD_NOTOK
} ePDPowerState;
typedef enum { LTC4275_POWERGOOD = 0, LTC4275_POWERGOOD_NOTOK } ePDPowerState;
typedef enum {
LTC4275_CLASSTYPE_UNKOWN = 0,
@@ -36,10 +33,7 @@ typedef enum {
LTC4275_CLASSTYPE_POEPP
} ePDClassType;
typedef enum {
LTC4275_STATE_OK = 0,
LTC4275_STATE_NOTOK
} ePDState;
typedef enum { LTC4275_STATE_OK = 0, LTC4275_STATE_NOTOK } ePDState;
typedef enum {
LTC4275_CONNECT_ALERT = 1,
@@ -48,29 +42,28 @@ typedef enum {
} ePDAlert;
typedef enum {
LTC4275_CONNECT_EVT = 1 << 2, /* PD device Connected. */
LTC4275_DISCONNECT_EVT = 1 << 1, /* PD device removed. */
LTC4275_INCOMPATIBLE_EVT = 1 << 0, /* Incomaptible device */
LTC4275_CONNECT_EVT = 1 << 2, /* PD device Connected. */
LTC4275_DISCONNECT_EVT = 1 << 1, /* PD device removed. */
LTC4275_INCOMPATIBLE_EVT = 1 << 0, /* Incomaptible device */
} LTC4275_Event;
typedef struct __attribute__((packed, aligned(1))) {
uint8_t classStatus;
uint8_t powerGoodStatus;
}tPower_PDStatus;
uint8_t classStatus;
uint8_t powerGoodStatus;
} tPower_PDStatus;
typedef struct __attribute__((packed, aligned(1))) {
tPower_PDStatus pdStatus;
ePDState state;
ePDAlert pdalert;
}tPower_PDStatus_Info;
ePDState state;
ePDAlert pdalert;
} tPower_PDStatus_Info;
typedef struct LTC4275_Cfg {
OcGpio_Pin *pin_evt;
OcGpio_Pin *pin_detect;
} LTC4275_Cfg;
typedef void (*LTC4275_CallbackFn) (LTC4275_Event evt,
void *context);
typedef void (*LTC4275_CallbackFn)(LTC4275_Event evt, void *context);
typedef struct LTC4275_Obj {
LTC4275_CallbackFn alert_cb;
void *cb_context;
@@ -88,7 +81,8 @@ typedef struct LTC4275A_Dev {
void ltc4275_config(const LTC4275_Dev *dev);
ePostCode ltc4275_probe(const LTC4275_Dev *dev, POSTData *postData);
ReturnStatus ltc4275_init(LTC4275_Dev *dev);
void ltc4275_set_alert_handler(LTC4275_Dev *dev, LTC4275_CallbackFn alert_cb, void *cb_context);
void ltc4275_set_alert_handler(LTC4275_Dev *dev, LTC4275_CallbackFn alert_cb,
void *cb_context);
ReturnStatus ltc4275_get_power_good(const LTC4275_Dev *dev, ePDPowerState *val);
ReturnStatus ltc4275_get_class(const LTC4275_Dev *dev, ePDClassType *val);
void ltc4275_update_status(const LTC4275_Dev *dev);

47
firmware/ec/inc/devices/powerSource.h
View File

@@ -27,40 +27,40 @@ typedef enum {
} ePowerSource;
typedef enum {
PWR_SRC_ACTIVE = 0, /* If source is primary source */
PWR_SRC_AVAILABLE, /* If source is available */
PWR_SRC_NON_AVAILABLE /* If source is not connected */
PWR_SRC_ACTIVE = 0, /* If source is primary source */
PWR_SRC_AVAILABLE, /* If source is available */
PWR_SRC_NON_AVAILABLE /* If source is not connected */
} ePowerSourceState;
typedef enum {
PWR_STAT_POE_AVAILABILITY = 0x00,
PWR_STAT_POE_ACCESSIBILITY = 0x01,
PWR_STAT_SOLAR_AVAILABILITY = 0x02,
PWR_STAT_SOLAR_ACCESSIBILITY = 0x03,
PWR_STAT_EXTBATT_AVAILABILITY = 0x04,
PWR_STAT_EXTBATT_ACCESSIBILITY = 0x05,
PWR_STAT_INTBATT_AVAILABILITY = 0x06,
PWR_STAT_INTBATT_ACCESSIBILITY = 0x07
}ePower_StatusParamId;
PWR_STAT_POE_AVAILABILITY = 0x00,
PWR_STAT_POE_ACCESSIBILITY = 0x01,
PWR_STAT_SOLAR_AVAILABILITY = 0x02,
PWR_STAT_SOLAR_ACCESSIBILITY = 0x03,
PWR_STAT_EXTBATT_AVAILABILITY = 0x04,
PWR_STAT_EXTBATT_ACCESSIBILITY = 0x05,
PWR_STAT_INTBATT_AVAILABILITY = 0x06,
PWR_STAT_INTBATT_ACCESSIBILITY = 0x07
} ePower_StatusParamId;
typedef enum {
PWR_STATUS_POE_AVAILABILITY = 0x01,
PWR_STATUS_POE_ACCESSIBILITY = 0x02,
PWR_STATUS_SOLAR_AVAILABILITY = 0x04,
PWR_STATUS_SOLAR_ACCESSIBILITY = 0x08,
PWR_STATUS_EXTBATT_AVAILABILITY = 0x10,
PWR_STATUS_POE_AVAILABILITY = 0x01,
PWR_STATUS_POE_ACCESSIBILITY = 0x02,
PWR_STATUS_SOLAR_AVAILABILITY = 0x04,
PWR_STATUS_SOLAR_ACCESSIBILITY = 0x08,
PWR_STATUS_EXTBATT_AVAILABILITY = 0x10,
PWR_STATUS_EXTBATT_ACCESSIBILITY = 0x20,
PWR_STATUS_INTBATT_AVAILABILITY = 0x40,
PWR_STATUS_INTBATT_AVAILABILITY = 0x40,
PWR_STATUS_INTBATT_ACCESSIBILITY = 0x80,
PWR_STATUS_PARAM_MAX = 0x100
}ePower_StatusParam;
PWR_STATUS_PARAM_MAX = 0x100
} ePower_StatusParam;
typedef struct {
ePowerSource powerSource;
ePowerSourceState state;
} tPowerSource;
typedef struct __attribute__((packed, aligned(1))) {
typedef struct __attribute__((packed, aligned(1))) {
uint8_t poeAvail;
uint8_t poeAccess;
uint8_t solarAvail;
@@ -89,7 +89,8 @@ typedef struct PWRSRC_Dev {
void pwr_source_init(void);
void pwr_get_source_info(PWRSRC_Dev *pwrSrcDev);
ReturnStatus pwr_process_get_status_parameters_data(
ePower_StatusParamId paramIndex, uint8_t *pPowerStatusData);
ReturnStatus
pwr_process_get_status_parameters_data(ePower_StatusParamId paramIndex,
uint8_t *pPowerStatusData);
#endif /* POWERSOURCE_H_ */

36
firmware/ec/inc/devices/sbd.h
View File

@@ -1,31 +1,31 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
#ifndef INC_DEVICES_SBD_H_
#define INC_DEVICES_SBD_H_
#include <stdint.h>
typedef enum {
IRIDIUM_IMEI = 0,
IRIDIUM_MFG = 1,
IRIDIUM_MODEL = 2,
IRIDIUM_SIG_QUALITY = 3,
IRIDIUM_REGSTATUS = 4,
IRIDIUM_NO_OUT_MSG = 5,
IRIDIUM_LASTERR = 6,
IRIDIUM_PARAM_MAX /* Limiter */
IRIDIUM_IMEI = 0,
IRIDIUM_MFG = 1,
IRIDIUM_MODEL = 2,
IRIDIUM_SIG_QUALITY = 3,
IRIDIUM_REGSTATUS = 4,
IRIDIUM_NO_OUT_MSG = 5,
IRIDIUM_LASTERR = 6,
IRIDIUM_PARAM_MAX /* Limiter */
} eOBC_StatusParam;
typedef enum {
ERR_RC_INTERNAL = 0,
ERR_SRC_CMS = 1,
ERR_SRC_CME = 2
ERR_RC_INTERNAL = 0,
ERR_SRC_CMS = 1,
ERR_SRC_CME = 2
} eOBC_ErrorSource;
typedef struct OBC_lastError {

13
firmware/ec/inc/devices/se98a.h
View File

@@ -28,15 +28,14 @@ typedef enum SE98A_Event {
SE98A_EVT_BAW = 1 << 0, /* Below alarm window */
} SE98A_Event;
typedef enum
{
typedef enum {
CONF_TEMP_SE98A_LOW_LIMIT_REG = 1,
CONF_TEMP_SE98A_HIGH_LIMIT_REG,
CONF_TEMP_SE98A_CRITICAL_LIMIT_REG
}eTempSensor_ConfigParamsId;
} eTempSensor_ConfigParamsId;
typedef void (*SE98A_CallbackFn) (SE98A_Event evt, int8_t temperature,
void *context);
typedef void (*SE98A_CallbackFn)(SE98A_Event evt, int8_t temperature,
void *context);
typedef struct SE98A_Cfg {
I2C_Dev dev;
@@ -84,7 +83,7 @@ ReturnStatus se98a_enable_alerts(SE98A_Dev *dev);
* @param dev Device struct pointer, Post data struct
* @return POST_DEV_FOUND on success, error code on failure
*/
ePostCode se98a_probe(SE98A_Dev *dev, POSTData *postData);
ePostCode se98a_probe(SE98A_Dev *dev, POSTData *postData);
/*! Sets one of the 3 alert thresholds on the device
* @param dev Device struct pointer
@@ -104,7 +103,7 @@ ReturnStatus se98a_set_limit(SE98A_Dev *dev,
*/
ReturnStatus se98a_get_limit(SE98A_Dev *dev,
eTempSensor_ConfigParamsId limitToConfig,
int8_t* tempLimitValue);
int8_t *tempLimitValue);
/*! Reads the current temperature from the sensor
* @param dev Device struct pointer

85
firmware/ec/inc/devices/sx1509.h
View File

@@ -19,40 +19,36 @@
* MACRO DEFINITIONS
*****************************************************************************/
/* Oscillator frequency source */
#define SX1509_EXTERNAL_CLOCK 1
#define SX1509_INTERNAL_CLOCK_2MHZ 2
#define SX1509_EXTERNAL_CLOCK 1
#define SX1509_INTERNAL_CLOCK_2MHZ 2
/* OSCIO pin function */
#define SX1509_CLOCK_OSC_IN 0
#define SX1509_CLOCK_OSC_OUT 1
#define SX1509_CLOCK_OSC_IN 0
#define SX1509_CLOCK_OSC_OUT 1
/* IO pin definitions */
#define SX1509_IO_PIN_0 0x0001
#define SX1509_IO_PIN_1 0x0002
#define SX1509_IO_PIN_2 0x0004
#define SX1509_IO_PIN_3 0x0008
#define SX1509_IO_PIN_4 0x0010
#define SX1509_IO_PIN_5 0x0020
#define SX1509_IO_PIN_6 0x0040
#define SX1509_IO_PIN_7 0x0080
#define SX1509_IO_PIN_8 0x0001
#define SX1509_IO_PIN_9 0x0002
#define SX1509_IO_PIN_10 0x0004
#define SX1509_IO_PIN_11 0x0008
#define SX1509_IO_PIN_12 0x0010
#define SX1509_IO_PIN_13 0x0020
#define SX1509_IO_PIN_14 0x0040
#define SX1509_IO_PIN_15 0x0080
#define SX1509_IO_PIN_0 0x0001
#define SX1509_IO_PIN_1 0x0002
#define SX1509_IO_PIN_2 0x0004
#define SX1509_IO_PIN_3 0x0008
#define SX1509_IO_PIN_4 0x0010
#define SX1509_IO_PIN_5 0x0020
#define SX1509_IO_PIN_6 0x0040
#define SX1509_IO_PIN_7 0x0080
#define SX1509_IO_PIN_8 0x0001
#define SX1509_IO_PIN_9 0x0002
#define SX1509_IO_PIN_10 0x0004
#define SX1509_IO_PIN_11 0x0008
#define SX1509_IO_PIN_12 0x0010
#define SX1509_IO_PIN_13 0x0020
#define SX1509_IO_PIN_14 0x0040
#define SX1509_IO_PIN_15 0x0080
/*****************************************************************************
* STRUCT/ENUM DEFINITIONS
*****************************************************************************/
/* Enumeration of SX1509 register types */
typedef enum {
SX1509_REG_A = 0,
SX1509_REG_B,
SX1509_REG_AB
} sx1509RegType;
typedef enum { SX1509_REG_A = 0, SX1509_REG_B, SX1509_REG_AB } sx1509RegType;
typedef enum {
SX1509_EDGE_SENSE_REG_LOW = 0,
@@ -63,18 +59,13 @@ typedef enum {
/*****************************************************************************
* FUNCTION DECLARATIONS
*****************************************************************************/
ReturnStatus ioexp_led_get_data(const I2C_Dev *i2c_dev,
sx1509RegType regType,
ReturnStatus ioexp_led_get_data(const I2C_Dev *i2c_dev, sx1509RegType regType,
uint8_t *regValue);
ReturnStatus ioexp_led_set_data(const I2C_Dev *i2c_dev,
sx1509RegType regType,
uint8_t regValue1,
uint8_t regValue2);
ReturnStatus ioexp_led_set_on_time(const I2C_Dev *i2c_dev,
uint8_t index,
ReturnStatus ioexp_led_set_data(const I2C_Dev *i2c_dev, sx1509RegType regType,
uint8_t regValue1, uint8_t regValue2);
ReturnStatus ioexp_led_set_on_time(const I2C_Dev *i2c_dev, uint8_t index,
uint8_t tOnRegValue);
ReturnStatus ioexp_led_set_off_time(const I2C_Dev *i2c_dev,
uint8_t index,
ReturnStatus ioexp_led_set_off_time(const I2C_Dev *i2c_dev, uint8_t index,
uint8_t tOffRegValue);
ReturnStatus ioexp_led_software_reset(const I2C_Dev *i2c_dev);
ReturnStatus ioexp_led_config_inputbuffer(const I2C_Dev *i2c_dev,
@@ -86,9 +77,9 @@ ReturnStatus ioexp_led_config_pullup(const I2C_Dev *i2c_dev,
uint8_t pullUpRegValue1,
uint8_t pullUpRegValue2);
ReturnStatus ioexp_led_config_pulldown(const I2C_Dev *i2c_dev,
sx1509RegType regType,
uint8_t pullDownRegValue1,
uint8_t pullDownRegValue2);
sx1509RegType regType,
uint8_t pullDownRegValue1,
uint8_t pullDownRegValue2);
ReturnStatus ioexp_led_config_opendrain(const I2C_Dev *i2c_dev,
sx1509RegType regType,
uint8_t openDrainRegValue1,
@@ -101,11 +92,9 @@ ReturnStatus ioexp_led_config_polarity(const I2C_Dev *i2c_dev,
sx1509RegType regType,
uint8_t polarityRegValue1,
uint8_t polarityRegValue2);
ReturnStatus ioexp_led_config_clock(const I2C_Dev *i2c_dev,
uint8_t oscSource,
ReturnStatus ioexp_led_config_clock(const I2C_Dev *i2c_dev, uint8_t oscSource,
uint8_t oscPin);
ReturnStatus ioexp_led_config_misc(const I2C_Dev *i2c_dev,
uint8_t regValue);
ReturnStatus ioexp_led_config_misc(const I2C_Dev *i2c_dev, uint8_t regValue);
ReturnStatus ioexp_led_enable_leddriver(const I2C_Dev *i2c_dev,
sx1509RegType regType,
uint8_t ledEnableRegValue1,
@@ -117,13 +106,13 @@ ReturnStatus ioexp_led_config_interrupt(const I2C_Dev *i2c_dev,
uint8_t interruptMaskRegValue1,
uint8_t interruptMaskRegValue2);
ReturnStatus ioexp_led_config_edge_sense_A(const I2C_Dev *i2c_dev,
sx1509EdgeSenseRegType regType,
uint8_t edgeSenseLowARegValue,
uint8_t edgeSenseHighARegValue);
sx1509EdgeSenseRegType regType,
uint8_t edgeSenseLowARegValue,
uint8_t edgeSenseHighARegValue);
ReturnStatus ioexp_led_config_edge_sense_A(const I2C_Dev *i2c_dev,
sx1509EdgeSenseRegType regType,
uint8_t edgeSenseLowBRegValue,
uint8_t edgeSenseHighBRegValue);
sx1509EdgeSenseRegType regType,
uint8_t edgeSenseLowBRegValue,
uint8_t edgeSenseHighBRegValue);
ReturnStatus ioexp_led_config_edge_sense_B(const I2C_Dev *i2c_dev,
sx1509EdgeSenseRegType regType,
uint8_t edgeSenseLowBRegValue,

12
firmware/ec/inc/interfaces/uartdma.h
View File

@@ -17,14 +17,14 @@
/*****************************************************************************
* MACROS DEFINITION
*****************************************************************************/
#define OCUARTDMA_TASK_PRIORITY 7
#define OCUARTDMA_TASK_STACK_SIZE 1024
#define OCUARTDMA_TASK_PRIORITY 7
#define OCUARTDMA_TASK_STACK_SIZE 1024
#define OCUARTDMATX_TASK_PRIORITY 7
#define OCUARTDMATX_TASK_STACK_SIZE 1024
#define OCUARTDMATX_TASK_PRIORITY 7
#define OCUARTDMATX_TASK_STACK_SIZE 1024
#define UART_TXBUF_SIZE OCMP_FRAME_TOTAL_LENGTH
#define UART_RXBUF_SIZE OCMP_FRAME_TOTAL_LENGTH
#define UART_TXBUF_SIZE OCMP_FRAME_TOTAL_LENGTH
#define UART_RXBUF_SIZE OCMP_FRAME_TOTAL_LENGTH
/*****************************************************************************
* HANDLE DECLARATIONS

3
firmware/ec/inc/interfaces/usbcdcd.h
View File

@@ -65,8 +65,7 @@ extern void USBCDCD_init(void);
* @return Number of bytes added to the USB Buffer for transmission
*/
extern unsigned int USBCDCD_sendData(const unsigned char *pStr,
unsigned int length,
unsigned int timeout);
unsigned int length, unsigned int timeout);
/*!
* ======== USBCDCD_receiveData ========

10
firmware/ec/inc/subsystem/bms/bms.h
View File

@@ -18,16 +18,16 @@
/*****************************************************************************
* MACRO DEFINITIONS
*****************************************************************************/
#define BMS_TASK_PRIORITY 2
#define BMS_TASK_STACK_SIZE 2048
#define BMS_TASK_PRIORITY 2
#define BMS_TASK_STACK_SIZE 2048
/*
* Define all the constant information of BMS subsystem here, like device
* addresses or Constant configuration values or NUMBER of sensors
*/
#define BMS_EC_TEMP_SENSOR_ADDR 0x19
#define BMS_EC_CURRENT_SENSOR_12V_ADDR 0x40
#define BMS_EC_CURRENT_SENSOR_3P3V_ADDR 0x45
#define BMS_EC_TEMP_SENSOR_ADDR 0x19
#define BMS_EC_CURRENT_SENSOR_12V_ADDR 0x40
#define BMS_EC_CURRENT_SENSOR_3P3V_ADDR 0x45
/*****************************************************************************
* STRUCT/ENUM DEFINITIONS

2
firmware/ec/inc/subsystem/ethernet/ethernetSS.h
View File

@@ -12,6 +12,6 @@
#include <stdbool.h>
void ethernet_switch_setup();
bool eth_sw_pre_init(void** driver, void *returnValue);
bool eth_sw_pre_init(void **driver, void *returnValue);
#endif /* ETHERNETSS_H_ */

13
firmware/ec/inc/subsystem/gpp/ebmp.h
View File

@@ -14,16 +14,15 @@
/*****************************************************************************
* MACRO DEFINITIONS
*****************************************************************************/
#define EBMP_TASK_STACK_SIZE 1024
#define EBMP_TASK_PRIORITY 2
#define EBMP_TASK_STACK_SIZE 1024
#define EBMP_TASK_PRIORITY 2
/*****************************************************************************
* STRUCT/ENUM DEFINITIONS
*****************************************************************************/
/*
* GPP states are define here. Where we define various states GPP or AP can be in.
* S0_SC[059] and S5[09] are the inputs
* T0: AP SOC under Reset. (0,0)
* GPP states are define here. Where we define various states GPP or AP can be
* in. S0_SC[059] and S5[09] are the inputs T0: AP SOC under Reset. (0,0)
* T1: AP starts the booting. (0,0)
* T2: AP starts DDR init. (0,1)
* T3: PCIe and SPC init. (1,1)
@@ -46,7 +45,7 @@ typedef enum {
} apStates;
typedef enum {
AP_RESET = 0,
AP_RESET = 0,
AP_BOOT_PROGRESS_MONITOR_1 = 1,
AP_BOOT_PROGRESS_MONITOR_2 = 2
} apBootMonitor;
@@ -54,6 +53,6 @@ typedef enum {
/*****************************************************************************
* FUNCTION DECLARATIONS
*****************************************************************************/
void ebmp_init(Gpp_gpioCfg* driver);
void ebmp_init(Gpp_gpioCfg *driver);
#endif /* EBMP_H_ */

16
firmware/ec/inc/subsystem/gpp/gpp.h
View File

@@ -20,23 +20,23 @@
/*****************************************************************************
* MACRO DEFINITIONS
*****************************************************************************/
#define GPP_TASK_PRIORITY 2
#define GPP_TASK_STACK_SIZE 2048
#define GPP_TASK_PRIORITY 2
#define GPP_TASK_STACK_SIZE 2048
/*
* Define all the constant information of GPP subsystem here, like device
* addresses or Constant configuration values or NUMBER of sensors.
*/
#define GPP_TEMP_SENSOR_NOS 3
#define GPP_TEMP_SENSOR_NOS 3
/*
* Device address of GPP sub system are as below.
*/
#define GPP_AP_TEMPSENS1_ADDR 0x1A
#define GPP_AP_TEMPSENS2_ADDR 0x1D
#define GPP_AP_TEMPSENS3_ADDR 0x1C
#define GPP_AP_CURRENT_SENSOR_ADDR 0x44
#define GPP_MSATA_CURRENT_SENSOR_ADDR 0x45
#define GPP_AP_TEMPSENS1_ADDR 0x1A
#define GPP_AP_TEMPSENS2_ADDR 0x1D
#define GPP_AP_TEMPSENS3_ADDR 0x1C
#define GPP_AP_CURRENT_SENSOR_ADDR 0x44
#define GPP_MSATA_CURRENT_SENSOR_ADDR 0x45
/*****************************************************************************
* STRUCT/ENUM DEFINITIONS

4
firmware/ec/inc/subsystem/hci/hci.h
View File

@@ -19,8 +19,8 @@
/*****************************************************************************
* MACRO DEFINITIONS
*****************************************************************************/
#define HCI_TASK_PRIORITY 6
#define HCI_TASK_STACK_SIZE 4096
#define HCI_TASK_PRIORITY 6
#define HCI_TASK_STACK_SIZE 4096
#define HCI_LED_TEMP_SENSOR_ADDR 0x1A

4
firmware/ec/inc/subsystem/hci/hci_led.h
View File

@@ -20,8 +20,8 @@
/*****************************************************************************
* MACRO DEFINITIONS
*****************************************************************************/
#define LED_SX1509_LEFT_ADDRESS 0x3E
#define LED_SX1509_RIGHT_ADDRESS 0x3F
#define LED_SX1509_LEFT_ADDRESS 0x3E
#define LED_SX1509_RIGHT_ADDRESS 0x3F
/*****************************************************************************
* STRUCT/ENUM DEFINITIONS

26
firmware/ec/inc/subsystem/rffe/rffe.h
View File

@@ -21,8 +21,8 @@
/*****************************************************************************
* MACRO DEFINITIONS
*****************************************************************************/
#define RFFE_TASK_PRIORITY 2
#define RFFE_TASK_STACK_SIZE 2048
#define RFFE_TASK_PRIORITY 2
#define RFFE_TASK_STACK_SIZE 2048
/*****************************************************************************
* STRUCT/ENUM DEFINITIONS
@@ -50,21 +50,21 @@ typedef struct Fe_Lna_Cfg {
} Fe_Lna_Cfg;
typedef struct Fe_Ch1_Gain_Cfg {
Fe_Gain_Cfg* fe_gain_cfg;
Fe_Gain_Cfg *fe_gain_cfg;
} Fe_Ch1_Gain_Cfg;
typedef struct Fe_Ch2_Gain_Cfg {
OcGpio_Pin pin_ch1_2g_lb_band_sel_l;
Fe_Gain_Cfg* fe_gain_cfg;
Fe_Gain_Cfg *fe_gain_cfg;
} Fe_Ch2_Gain_Cfg;
typedef struct Fe_Ch1_Lna_Cfg {
Fe_Lna_Cfg* fe_lna_cfg;
Fe_Lna_Cfg *fe_lna_cfg;
} Fe_Ch1_Lna_Cfg;
typedef struct Fe_Ch2_Lna_Cfg {
OcGpio_Pin pin_ch1_rf_pwr_off;
Fe_Lna_Cfg* fe_lna_cfg;
Fe_Lna_Cfg *fe_lna_cfg;
} Fe_Ch2_Lna_Cfg;
typedef struct Fe_Watchdog_Cfg {
@@ -82,15 +82,15 @@ typedef struct Fe_gpioCfg {
OcGpio_Pin pin_rf_pgood_ldo;
OcGpio_Pin pin_fe_12v_ctrl;
OcGpio_Pin pin_trxfe_conn_reset;
}Fe_gpioCfg;
} Fe_gpioCfg;
typedef struct Fe_Cfg {
Fe_gpioCfg* fe_gpio_cfg;
Fe_Ch1_Gain_Cfg* fe_ch1_gain_cfg;
Fe_Ch2_Gain_Cfg* fe_ch2_gain_cfg;
Fe_Ch1_Lna_Cfg* fe_ch1_lna_cfg;
Fe_Ch2_Lna_Cfg* fe_ch2_lna_cfg;
Fe_Watchdog_Cfg* fe_watchdog_cfg;
Fe_gpioCfg *fe_gpio_cfg;
Fe_Ch1_Gain_Cfg *fe_ch1_gain_cfg;
Fe_Ch2_Gain_Cfg *fe_ch2_gain_cfg;
Fe_Ch1_Lna_Cfg *fe_ch1_lna_cfg;
Fe_Ch2_Lna_Cfg *fe_ch2_lna_cfg;
Fe_Watchdog_Cfg *fe_watchdog_cfg;
} Fe_Cfg;
typedef struct __attribute__((packed, aligned(1))) {

6
firmware/ec/inc/subsystem/rffe/rffe_ctrl.h
View File

@@ -19,7 +19,7 @@
/*****************************************************************************
* MACRO DEFINITIONS
*****************************************************************************/
#define RFFE_IO_BOARD_CFG_ADDR 0x19
#define RFFE_IO_BOARD_CFG_ADDR 0x19
/*****************************************************************************
* STRUCT/ENUM DEFINITIONS
@@ -33,7 +33,7 @@ typedef enum rfChannel {
typedef struct FE_Ch_Band_cfg {
rffeChannel channel;
}FE_Ch_Band_cfg;
} FE_Ch_Band_cfg;
/* RFFE Band Type */
typedef enum {
@@ -49,7 +49,7 @@ typedef enum {
typedef struct FE_Band_Cfg {
rffeBand band;
}FE_Band_Cfg;
} FE_Band_Cfg;
/* Power Amplifier Control Type */
typedef enum rfPACtrl {

21
firmware/ec/inc/subsystem/rffe/rffe_powermonitor.h
View File

@@ -18,24 +18,21 @@
/*****************************************************************************
* MACRO DEFINITIONS
*****************************************************************************/
#define RFFEPOWERMONITOR_TASK_PRIORITY 2
#define RFFEPOWERMONITOR_TASK_STACK_SIZE 1024
#define RFFEPOWERMONITOR_TASK_PRIORITY 2
#define RFFEPOWERMONITOR_TASK_STACK_SIZE 1024
/* RF POWER Detector Device Addresses */
#define RFFE_CHANNEL1_ADC_ADDR 0x4A
#define RFFE_CHANNEL2_ADC_ADDR 0x48
#define RFFE_CHANNEL1_ADC_ADDR 0x4A
#define RFFE_CHANNEL2_ADC_ADDR 0x48
/*****************************************************************************
* STRUCT/ENUM DEFINITIONS
*****************************************************************************/
typedef enum {
RFFE_STAT_FW_POWER = 1,
RFFE_STAT_REV_POWER
} eRffeStatusParamId;
typedef enum { RFFE_STAT_FW_POWER = 1, RFFE_STAT_REV_POWER } eRffeStatusParamId;
typedef enum {
RFFE_STATUS_FW_POWER = 0x01,
RFFE_STATUS_REV_POWER = 0x02,
RFFE_STATUS_FW_POWER = 0x01,
RFFE_STATUS_REV_POWER = 0x02,
RFFE_STATUS_PARAMS_MAX = 0x04
} eRffeStatusParam;
@@ -71,8 +68,8 @@ typedef enum FePowerStatus {
* FUNCTION DECLARATIONS
*****************************************************************************/
ReturnStatus rffe_powermonitor_read_power(const I2C_Dev *i2c_dev,
eRffeStatusParamId rfPowerSelect,
uint16_t *rfpower);
eRffeStatusParamId rfPowerSelect,
uint16_t *rfpower);
void rffe_powermonitor_createtask(void);
#endif /* RFFE_POWERMONITOR_H_ */

8
firmware/ec/inc/subsystem/rffe/rffe_sensor.h
View File

@@ -13,11 +13,11 @@
* MACRO DEFINITIONS
*****************************************************************************/
/* RFFE Temperature Sensor Device Addresses */
#define RFFE_CH1_TEMP_SENSOR_ADDR 0x4B
#define RFFE_CH2_TEMP_SENSOR_ADDR 0x4C
#define RFFE_CH1_TEMP_SENSOR_ADDR 0x4B
#define RFFE_CH2_TEMP_SENSOR_ADDR 0x4C
/* RFFE INA226 Sensor Device Addresses */
#define RFFE_INA226_CH1_5_7V_ADDR 0x41
#define RFFE_INA226_CH2_5_7V_ADDR 0x40
#define RFFE_INA226_CH1_5_7V_ADDR 0x41
#define RFFE_INA226_CH2_5_7V_ADDR 0x40
#endif /* RFFE_SENSOR_H_ */

20
firmware/ec/inc/subsystem/sdr/sdr.h
View File

@@ -17,14 +17,13 @@
#include "inc/devices/eeprom.h"
#include "inc/devices/ina226.h"
#include <stdbool.h>
/*****************************************************************************
* MACRO DEFINITIONS
*****************************************************************************/
#define SDR_TASK_PRIORITY 2
#define SDR_TASK_STACK_SIZE 4096
#define SDR_TASK_PRIORITY 2
#define SDR_TASK_STACK_SIZE 4096
/*
* Define all the constant information of RF SDR subsystem here, like device
@@ -32,14 +31,14 @@
*/
/* SDR Temperature Sensor Device Addresses */
#define SDR_FPGA_TEMP_SENSOR_ADDR 0x4C
#define SDR_FPGA_TEMP_SENSOR_ADDR 0x4C
/* SDR INA226 Sensor Device Addresses */
#define SDR_FPGA_CURRENT_SENSOR_ADDR 0x44
#define SDR_CURRENT_SENSOR_ADDR 0x41
#define SDR_FPGA_CURRENT_SENSOR_ADDR 0x44
#define SDR_CURRENT_SENSOR_ADDR 0x41
/* FX3 IO Expander Device Address */
#define SDR_EEPROM_IOEXP_ADDRESS 0x1F
#define SDR_EEPROM_IOEXP_ADDRESS 0x1F
/*****************************************************************************
* STRUCT/ENUM DEFINITIONS
@@ -57,17 +56,18 @@ typedef struct Sdr_gpioCfg {
OcGpio_Pin pin_sdr_reset_in;
OcGpio_Pin pin_ec_trxfe_reset;
OcGpio_Pin pin_fx3_reset;
}Sdr_gpioCfg;
} Sdr_gpioCfg;
/*****************************************************************************
* FUNCTION DECLARATIONS
*****************************************************************************/
void sdr_pwr_control(Sdr_gpioCfg *driver, uint8_t control); /* TODO: hack to let OBC work */
void sdr_pwr_control(Sdr_gpioCfg *driver,
uint8_t control); /* TODO: hack to let OBC work */
/* Schema hooks */
bool SDR_Init(void *driver, void *return_buf);
bool Sdr_InventoryGetStatus(void *driver, unsigned int param_id,
void *return_buf);
void *return_buf);
bool SDR_fx3Reset(void *driver, void *params);
bool SDR_reset(void *driver, void *params);

15
firmware/ec/inc/subsystem/sync/sync.h
View File

@@ -21,14 +21,14 @@
/*****************************************************************************
* MACRO DEFINITIONS
*****************************************************************************/
#define SYNC_TASK_PRIORITY 2
#define SYNC_TASK_STACK_SIZE 1024
#define SYNC_TASK_PRIORITY 2
#define SYNC_TASK_STACK_SIZE 1024
/* Temporary fix */
#define SYNC_GPS_TASK_PRIORITY 2
#define SYNC_GPS_TASK_STACK_SIZE 1024
#define SYNC_GPS_TASK_PRIORITY 2
#define SYNC_GPS_TASK_STACK_SIZE 1024
#define SYNC_TEMP_SENSOR_ADDR 0x4C
#define SYNC_TEMP_SENSOR_ADDR 0x4C
/*****************************************************************************
* STRUCT/ENUM DEFINITIONS
@@ -47,10 +47,7 @@ typedef struct Sync_gpioCfg {
OcGpio_Pin pin_ec_sync_reset;
} Sync_gpioCfg;
typedef enum gpsStatus {
GPS_NOTLOCKED = 0,
GPS_LOCKED
} gpsStatus;
typedef enum gpsStatus { GPS_NOTLOCKED = 0, GPS_LOCKED } gpsStatus;
/*****************************************************************************
* FUNCTION DECLARATIONS

14
firmware/ec/inc/subsystem/sys/sys.h
View File

@@ -1,11 +1,11 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*/
#ifndef _SYS_H
#define _SYS_H
#include "common/inc/global/Framework.h"

7
firmware/ec/inc/subsystem/testModule/testModule.h
View File

@@ -16,7 +16,6 @@
#include "drivers/OcGpio.h"
#include "helpers/attribute.h"
/*****************************************************************************
* STRUCT/ENUM DEFINITIONS
*****************************************************************************/
@@ -53,9 +52,9 @@ typedef struct TestModule_opInfo {
} TestModule_opInfo;
typedef enum TestModule_errorSource {
TESTMOD_ERR_INTERNAL = 0,
TESTMOD_ERR_CMS = 1,
TESTMOD_ERR_CME = 2
TESTMOD_ERR_INTERNAL = 0,
TESTMOD_ERR_CMS = 1,
TESTMOD_ERR_CME = 2
} TestModule_errorSource;
typedef struct TestModule_lastError {

4
firmware/ec/inc/subsystem/watchdog/watchdog.h
View File

@@ -12,7 +12,7 @@
/*****************************************************************************
* MACRO DEFINITIONS
*****************************************************************************/
#define WATCHDOG_TASK_STACK_SIZE 1024
#define WATCHDOG_TASK_PRIORITY 2
#define WATCHDOG_TASK_STACK_SIZE 1024
#define WATCHDOG_TASK_PRIORITY 2
#endif /* WATCHDOG_H_ */

19
firmware/ec/inc/utils/ocmp_util.h
View File

@@ -26,7 +26,7 @@
**
*****************************************************************************/
OCMPMessageFrame * OCMP_mallocFrame(uint16_t len);
OCMPMessageFrame *OCMP_mallocFrame(uint16_t len);
/*****************************************************************************
** FUNCTION NAME : create_ocmp_msg_frame
@@ -38,13 +38,10 @@ OCMPMessageFrame * OCMP_mallocFrame(uint16_t len);
** RETURN TYPE : OCMPMessageFrame
**
*****************************************************************************/
OCMPMessageFrame* create_ocmp_msg_frame(OCMPSubsystem subSystem,
OCMPMsgType msgtype,
OCMPActionType actionType,
uint8_t componentId,
uint16_t parameters,
uint8_t payloadSize);
OCMPMessageFrame *
create_ocmp_msg_frame(OCMPSubsystem subSystem, OCMPMsgType msgtype,
OCMPActionType actionType, uint8_t componentId,
uint16_t parameters, uint8_t payloadSize);
/*****************************************************************************
** FUNCTION NAME : create_ocmp_alert_from_Evt
@@ -58,8 +55,8 @@ OCMPMessageFrame* create_ocmp_msg_frame(OCMPSubsystem subSystem,
** RETURN TYPE : OCMPMessageFrame
**
*****************************************************************************/
OCMPMessageFrame* create_ocmp_alert_from_Evt(OCMPMessageFrame* ocmpEventMsg,
uint8_t componentId,
uint16_t parameters );
OCMPMessageFrame *create_ocmp_alert_from_Evt(OCMPMessageFrame *ocmpEventMsg,
uint8_t componentId,
uint16_t parameters);
#endif /* INC_UTILS_OCMP_UTIL_H_ */

25
firmware/ec/inc/utils/util.h
View File

@@ -55,8 +55,8 @@ extern "C" {
#include <ti/sysbios/knl/Semaphore.h>
/*********************************************************************
* EXTERNAL VARIABLES
*/
* EXTERNAL VARIABLES
*/
/*********************************************************************
* CONSTANTS
@@ -66,11 +66,10 @@ extern "C" {
* TYPEDEFS
*/
typedef struct
{
uint16_t event; // Event type.
uint8_t state; // Event state;
}appEvtHdr_t;
typedef struct {
uint16_t event; // Event type.
uint8_t state; // Event state;
} appEvtHdr_t;
/*********************************************************************
* MACROS
@@ -95,12 +94,9 @@ typedef struct
*
* @return Clock_Handle - a handle to the clock instance.
*/
Clock_Handle Util_constructClock(Clock_Struct *pClock,
Clock_FuncPtr clockCB,
uint32_t clockDuration,
uint32_t clockPeriod,
uint8_t startFlag,
UArg arg);
Clock_Handle Util_constructClock(Clock_Struct *pClock, Clock_FuncPtr clockCB,
uint32_t clockDuration, uint32_t clockPeriod,
uint8_t startFlag, UArg arg);
/*********************************************************************
* @fn Util_startClock
@@ -184,7 +180,8 @@ Queue_Handle Util_constructQueue(Queue_Struct *pQueue);
*
* @return TRUE if message was queued, FALSE otherwise.
*/
uint8_t Util_enqueueMsg(Queue_Handle msgQueue, Semaphore_Handle sem, uint8_t *pMsg);
uint8_t Util_enqueueMsg(Queue_Handle msgQueue, Semaphore_Handle sem,
uint8_t *pMsg);
/*********************************************************************
* @fn Util_dequeueMsg

563
firmware/ec/platform/oc-sdr/cfg/OC_CONNECT1.c
View File

@@ -66,11 +66,11 @@
#include <driverlib/udma.h>
#ifndef TI_DRIVERS_UART_DMA
#define TI_DRIVERS_UART_DMA 0
# define TI_DRIVERS_UART_DMA 0
#endif
#ifndef TI_EXAMPLES_PPP
#define TI_EXAMPLES_PPP 0
# define TI_EXAMPLES_PPP 0
#else
/* prototype for NIMU init function */
extern int USBSerialPPP_NIMUInit();
@@ -80,11 +80,11 @@ extern int USBSerialPPP_NIMUInit();
* =============================== DMA ===============================
*/
#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_ALIGN(dmaControlTable, 1024)
# pragma DATA_ALIGN(dmaControlTable, 1024)
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma data_alignment=1024
# pragma data_alignment = 1024
#elif defined(__GNUC__)
__attribute__ ((aligned (1024)))
__attribute__((aligned(1024)))
#endif
static tDMAControlTable dmaControlTable[32];
static bool dmaInitialized = false;
@@ -155,9 +155,9 @@ void OC_CONNECT1_initGeneral(void)
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);
// TODO: why did we comment this out?
//SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOR);
//SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOS);
//SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOT);
// SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOR);
// SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOS);
// SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOT);
}
/*
@@ -165,9 +165,9 @@ void OC_CONNECT1_initGeneral(void)
*/
/* Place into subsections to allow the TI linker to remove items properly */
#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_SECTION(EMAC_config, ".const:EMAC_config")
#pragma DATA_SECTION(emacHWAttrs, ".const:emacHWAttrs")
#pragma DATA_SECTION(NIMUDeviceTable, ".data:NIMUDeviceTable")
# pragma DATA_SECTION(EMAC_config, ".const:EMAC_config")
# pragma DATA_SECTION(emacHWAttrs, ".const:emacHWAttrs")
# pragma DATA_SECTION(NIMUDeviceTable, ".data:NIMUDeviceTable")
#endif
#include <ti/drivers/EMAC.h>
@@ -203,20 +203,16 @@ EMACSnow_Object emacObjects[OC_CONNECT1_EMACCOUNT];
unsigned char macAddress[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
const EMACSnow_HWAttrs emacHWAttrs[OC_CONNECT1_EMACCOUNT] = {
[OC_CONNECT1_EMAC0] = {
.baseAddr = EMAC0_BASE,
.intNum = INT_EMAC0,
.intPriority = (~0),
.macAddress = macAddress
}
[OC_CONNECT1_EMAC0] = { .baseAddr = EMAC0_BASE,
.intNum = INT_EMAC0,
.intPriority = (~0),
.macAddress = macAddress }
};
const EMAC_Config EMAC_config[] = {
[OC_CONNECT1_EMAC0] = {
.fxnTablePtr = &EMACSnow_fxnTable,
.object = &emacObjects[OC_CONNECT1_EMAC0],
.hwAttrs = &emacHWAttrs[OC_CONNECT1_EMAC0]
},
[OC_CONNECT1_EMAC0] = { .fxnTablePtr = &EMACSnow_fxnTable,
.object = &emacObjects[OC_CONNECT1_EMAC0],
.hwAttrs = &emacHWAttrs[OC_CONNECT1_EMAC0] },
{ NULL, NULL, NULL }
};
@@ -242,15 +238,15 @@ void OC_CONNECT1_initEMAC(void)
macAddress[3] = ((ulUser1 >> 0) & 0xff);
macAddress[4] = ((ulUser1 >> 8) & 0xff);
macAddress[5] = ((ulUser1 >> 16) & 0xff);
} else if (macAddress[0] == 0xff && macAddress[1] == 0xff
&& macAddress[2] == 0xff && macAddress[3] == 0xff
&& macAddress[4] == 0xff && macAddress[5] == 0xff) {
} else if (macAddress[0] == 0xff && macAddress[1] == 0xff &&
macAddress[2] == 0xff && macAddress[3] == 0xff &&
macAddress[4] == 0xff && macAddress[5] == 0xff) {
System_printf("Change the macAddress variable to valid Mac address");
}
// GPIOPinConfigure(GPIO_PF0_EN0LED0); /* OC_CONNECT1_USR_D3 */
// GPIOPinConfigure(GPIO_PF4_EN0LED1); /* OC_CONNECT1_USR_D4 */
// GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_0 | GPIO_PIN_4);
// GPIOPinConfigure(GPIO_PF0_EN0LED0); /* OC_CONNECT1_USR_D3 */
// GPIOPinConfigure(GPIO_PF4_EN0LED1); /* OC_CONNECT1_USR_D4 */
// GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_0 | GPIO_PIN_4);
/* Once EMAC_init is called, EMAC_config cannot be changed */
EMAC_init();
@@ -261,7 +257,7 @@ void OC_CONNECT1_initEMAC(void)
*/
/* Place into subsections to allow the TI linker to remove items properly */
#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_SECTION(GPIOTiva_config, ".const:GPIOTiva_config")
# pragma DATA_SECTION(GPIOTiva_config, ".const:GPIOTiva_config")
#endif
#include <ti/drivers/GPIO.h>
@@ -278,78 +274,70 @@ extern GPIO_PinConfig gpioPinConfigs[];
GPIO_PinConfig gpioPinConfigs[OC_EC_GPIOCOUNT] = {
[OC_EC_SOC_UART3_TX] =
GPIOTiva_PA_5 | GPIO_CFG_IN_NOPULL | GPIO_CFG_IN_INT_BOTH_EDGES,
[OC_EC_FLASH_nCS] =
GPIOTiva_PB_4 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_HIGH,
[OC_EC_FLASH_nCS] = GPIOTiva_PB_4 | GPIO_CFG_OUT_STD |
GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_HIGH,
[OC_EC_SDR_INA_ALERT] =
GPIOTiva_PD_2 | GPIO_CFG_IN_NOPULL | GPIO_CFG_IN_INT_FALLING,
[OC_EC_PWR_PSE_RESET] =
GPIOTiva_PD_3 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_HIGH,
[OC_EC_PWR_PRSNT_SOLAR_AUX] =
GPIOTiva_PD_6 | GPIO_CFG_IN_PU ,
[OC_EC_PWR_PSE_RESET] = GPIOTiva_PD_3 | GPIO_CFG_OUT_STD |
GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_HIGH,
[OC_EC_PWR_PRSNT_SOLAR_AUX] = GPIOTiva_PD_6 | GPIO_CFG_IN_PU,
[OC_EC_SYNC_IOEXP_ALERT] =
GPIOTiva_PD_7 | GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING,
[OC_EC_GBC_IOEXP71_ALERT] =
GPIOTiva_PE_0 | GPIO_CFG_IN_NOPULL | GPIO_CFG_IN_INT_FALLING,
[OC_EC_FE_CONTROL] =
GPIOTiva_PE_1 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
[OC_EC_FE_CONTROL] = GPIOTiva_PE_1 | GPIO_CFG_OUT_STD |
GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
[OC_EC_GPP_AP_BM_1] =
GPIOTiva_PE_3 | GPIO_CFG_IN_NOPULL | GPIO_CFG_IN_INT_BOTH_EDGES,
[OC_EC_GPP_PMIC_CORE_PWR] =
GPIOTiva_PH_0 | GPIO_CFG_IN_PU ,
[OC_EC_GPP_PMIC_CORE_PWR] = GPIOTiva_PH_0 | GPIO_CFG_IN_PU,
[OC_EC_GPP_SOC_PLTRST] =
GPIOTiva_PH_1 | GPIO_CFG_IN_NOPULL | GPIO_CFG_IN_INT_BOTH_EDGES,
[OC_EC_GPP_PMIC_CTRL] =
GPIOTiva_PH_2 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
[OC_EC_GPP_PMIC_CTRL] = GPIOTiva_PH_2 | GPIO_CFG_OUT_STD |
GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
[OC_EC_GBC_INA_ALERT] =
GPIOTiva_PH_3 | GPIO_CFG_IN_NOPULL | GPIO_CFG_IN_INT_FALLING,
[OC_EC_PWR_PD_NT2P] =
GPIOTiva_PJ_0 | GPIO_CFG_IN_PU ,
[OC_EC_PWR_PD_NT2P] = GPIOTiva_PJ_0 | GPIO_CFG_IN_PU,
[OC_EC_GBC_AP_INA_ALERT] =
GPIOTiva_PJ_1 | GPIO_CFG_IN_NOPULL | GPIO_CFG_IN_INT_FALLING,
[OC_EC_GBC_PSE_ALERT] =
GPIOTiva_PL_2 | GPIO_CFG_IN_NOPULL | GPIO_CFG_IN_INT_FALLING,
[OC_EC_GPP_AP_BM_2] =
GPIOTiva_PL_3 | GPIO_CFG_IN_NOPULL | GPIO_CFG_IN_INT_BOTH_EDGES,
[OC_EC_PWR_PRSNT_POE] =
GPIOTiva_PL_5 | GPIO_CFG_IN_PU ,
[OC_EC_PWR_PRSNT_POE] = GPIOTiva_PL_5 | GPIO_CFG_IN_PU,
[OC_EC_PWR_LION_ALERT] =
GPIOTiva_PM_0 | GPIO_CFG_IN_NOPULL | GPIO_CFG_IN_INT_FALLING,
[OC_EC_HCI_LED_RESET] =
GPIOTiva_PM_1 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_HIGH,
[OC_EC_HCI_LED_RESET] = GPIOTiva_PM_1 | GPIO_CFG_OUT_STD |
GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_HIGH,
[OC_EC_PWR_LACID_ALERT] =
GPIOTiva_PM_3 | GPIO_CFG_IN_NOPULL | GPIO_CFG_IN_INT_FALLING,
[OC_EC_RFFE_TEMP_INA_ALERT] =
GPIOTiva_PM_4 | GPIO_CFG_IN_NOPULL | GPIO_CFG_IN_INT_FALLING,
[OC_EC_ETH_SW_RESET] =
GPIOTiva_PM_5 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_HIGH,
[OC_EC_PWR_BATT_SELECT] =
GPIOTiva_PM_7 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_HIGH,
[OC_EC_ETH_SW_RESET] = GPIOTiva_PM_5 | GPIO_CFG_OUT_STD |
GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_HIGH,
[OC_EC_PWR_BATT_SELECT] = GPIOTiva_PM_7 | GPIO_CFG_OUT_STD |
GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_HIGH,
[OC_EC_PD_PWRGD_ALERT] =
GPIOTiva_PN_0 | GPIO_CFG_IN_NOPULL | GPIO_CFG_IN_INT_BOTH_EDGES,
[OC_EC_SDR_FPGA_TEMP_INA_ALERT] =
GPIOTiva_PN_1 | GPIO_CFG_IN_NOPULL | GPIO_CFG_IN_INT_FALLING,
[OC_EC_SDR_PWR_GD] =
GPIOTiva_PN_3 | GPIO_CFG_IN_NOPULL,
[OC_EC_SDR_DEVICE_CONTROL] =
GPIOTiva_PN_2 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
[OC_EC_FE_PWR_GD] =
GPIOTiva_PN_4 | GPIO_CFG_IN_NOPULL,
[OC_EC_SDR_FE_IO_RESET_CTRL] =
GPIOTiva_PP_1 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
[OC_EC_SDR_PWR_CNTRL] =
GPIOTiva_PP_2 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
[OC_EC_GPP_PWRGD_PROTECTION] =
GPIOTiva_PP_3 | GPIO_CFG_IN_PU ,
[OC_EC_RFFE_RESET] =
GPIOTiva_PP_4 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
[OC_EC_SDR_PWR_GD] = GPIOTiva_PN_3 | GPIO_CFG_IN_NOPULL,
[OC_EC_SDR_DEVICE_CONTROL] = GPIOTiva_PN_2 | GPIO_CFG_OUT_STD |
GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
[OC_EC_FE_PWR_GD] = GPIOTiva_PN_4 | GPIO_CFG_IN_NOPULL,
[OC_EC_SDR_FE_IO_RESET_CTRL] = GPIOTiva_PP_1 | GPIO_CFG_OUT_STD |
GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
[OC_EC_SDR_PWR_CNTRL] = GPIOTiva_PP_2 | GPIO_CFG_OUT_STD |
GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
[OC_EC_GPP_PWRGD_PROTECTION] = GPIOTiva_PP_3 | GPIO_CFG_IN_PU,
[OC_EC_RFFE_RESET] = GPIOTiva_PP_4 | GPIO_CFG_OUT_STD |
GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
[OC_EC_FE_TRXFE_CONN_RESET] = /* Watchdog nAO pin */
GPIOTiva_PQ_0 | GPIO_CFG_IN_NOPULL,
[OC_EC_GPP_MSATA_DAS] =
GPIOTiva_PQ_1 | GPIO_CFG_IN_PU ,
[OC_EC_GPP_RST_TO_PROC] =
GPIOTiva_PQ_3 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_HIGH,
[OC_EC_SYNC_RESET] =
GPIOTiva_PQ_4 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_HIGH,
GPIOTiva_PQ_0 | GPIO_CFG_IN_NOPULL,
[OC_EC_GPP_MSATA_DAS] = GPIOTiva_PQ_1 | GPIO_CFG_IN_PU,
[OC_EC_GPP_RST_TO_PROC] = GPIOTiva_PQ_3 | GPIO_CFG_OUT_STD |
GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_HIGH,
[OC_EC_SYNC_RESET] = GPIOTiva_PQ_4 | GPIO_CFG_OUT_STD |
GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_HIGH,
};
/*
@@ -361,15 +349,15 @@ GPIO_PinConfig gpioPinConfigs[OC_EC_GPIOCOUNT] = {
* We have lots of RAM right now, so just set it to full size of
* GPIO array
*/
GPIO_CallbackFxn gpioCallbackFunctions[OC_EC_GPIOCOUNT] = { };
GPIO_CallbackFxn gpioCallbackFunctions[OC_EC_GPIOCOUNT] = {};
/* The device-specific GPIO_config structure */
const GPIOTiva_Config GPIOTiva_config = {
.pinConfigs = (GPIO_PinConfig *) gpioPinConfigs,
.callbacks = (GPIO_CallbackFxn *) gpioCallbackFunctions,
.pinConfigs = (GPIO_PinConfig *)gpioPinConfigs,
.callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions,
.numberOfPinConfigs = sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
.numberOfCallbacks = sizeof(gpioCallbackFunctions) /
sizeof(GPIO_CallbackFxn),
.numberOfCallbacks =
sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
.intPriority = (~0)
};
@@ -386,9 +374,9 @@ OcGpio_Port ec_io;
OcGpio_Port gbc_io_1;
OcGpio_Port gbc_io_0;
OcGpio_Port sdr_fx3_io;
//OcGpio_Port sdr_eeprom_wp_io;
// OcGpio_Port sdr_eeprom_wp_io;
OcGpio_Port fe_ch1_gain_io;
OcGpio_Port fe_ch2_gain_io ;
OcGpio_Port fe_ch2_gain_io;
OcGpio_Port fe_ch1_lna_io;
OcGpio_Port fe_ch2_lna_io;
OcGpio_Port fe_watchdog_io;
@@ -400,27 +388,30 @@ OcGpio_Port ec_io = {
OcGpio_Port gbc_io_0 = {
.fn_table = &GpioSX1509_fnTable,
.cfg = &(SX1509_Cfg) {
.i2c_dev = { OC_CONNECT1_I2C6, BIGBROTHER_IOEXP0_ADDRESS },
.pin_irq = &(OcGpio_Pin){ &ec_io, OC_EC_GBC_IOEXP71_ALERT },
},
.cfg =
&(SX1509_Cfg){
.i2c_dev = { OC_CONNECT1_I2C6, BIGBROTHER_IOEXP0_ADDRESS },
.pin_irq = &(OcGpio_Pin){ &ec_io, OC_EC_GBC_IOEXP71_ALERT },
},
.object_data = &(SX1509_Obj){},
};
OcGpio_Port gbc_io_1 = {
.fn_table = &GpioSX1509_fnTable,
.cfg = &(SX1509_Cfg) {
.i2c_dev = { OC_CONNECT1_I2C6, BIGBROTHER_IOEXP1_ADDRESS },
.pin_irq = NULL, /* This IO expander doesn't provide interrupts */
},
.cfg =
&(SX1509_Cfg){
.i2c_dev = { OC_CONNECT1_I2C6, BIGBROTHER_IOEXP1_ADDRESS },
.pin_irq = NULL, /* This IO expander doesn't provide interrupts */
},
.object_data = &(SX1509_Obj){},
};
OcGpio_Port sdr_fx3_io = {
.fn_table = &GpioPCA9557_fnTable,
.cfg = &(PCA9557_Cfg) {
.i2c_dev = { OC_CONNECT1_I2C3, SDR_FX3_IOEXP_ADDRESS },
},
.cfg =
&(PCA9557_Cfg){
.i2c_dev = { OC_CONNECT1_I2C3, SDR_FX3_IOEXP_ADDRESS },
},
.object_data = &(PCA9557_Obj){},
};
@@ -435,50 +426,56 @@ OcGpio_Port sdr_fx3_io = {
OcGpio_Port fe_ch1_gain_io = {
.fn_table = &GpioPCA9557_fnTable,
.cfg = &(PCA9557_Cfg) {
.i2c_dev = { OC_CONNECT1_I2C2, RFFE_CHANNEL1_IO_TX_ATTEN_ADDR },
},
.cfg =
&(PCA9557_Cfg){
.i2c_dev = { OC_CONNECT1_I2C2, RFFE_CHANNEL1_IO_TX_ATTEN_ADDR },
},
.object_data = &(PCA9557_Obj){},
};
OcGpio_Port fe_ch2_gain_io = {
.fn_table = &GpioPCA9557_fnTable,
.cfg = &(PCA9557_Cfg) {
.i2c_dev = { OC_CONNECT1_I2C2, RFFE_CHANNEL2_IO_TX_ATTEN_ADDR },
},
.cfg =
&(PCA9557_Cfg){
.i2c_dev = { OC_CONNECT1_I2C2, RFFE_CHANNEL2_IO_TX_ATTEN_ADDR },
},
.object_data = &(PCA9557_Obj){},
};
OcGpio_Port fe_ch1_lna_io = {
.fn_table = &GpioPCA9557_fnTable,
.cfg = &(PCA9557_Cfg) {
.i2c_dev = { OC_CONNECT1_I2C2, RFFE_CHANNEL1_IO_RX_ATTEN_ADDR },
},
.cfg =
&(PCA9557_Cfg){
.i2c_dev = { OC_CONNECT1_I2C2, RFFE_CHANNEL1_IO_RX_ATTEN_ADDR },
},
.object_data = &(PCA9557_Obj){},
};
OcGpio_Port fe_ch2_lna_io = {
.fn_table = &GpioPCA9557_fnTable,
.cfg = &(PCA9557_Cfg) {
.i2c_dev = { OC_CONNECT1_I2C2, RFFE_CHANNEL2_IO_RX_ATTEN_ADDR },
},
.cfg =
&(PCA9557_Cfg){
.i2c_dev = { OC_CONNECT1_I2C2, RFFE_CHANNEL2_IO_RX_ATTEN_ADDR },
},
.object_data = &(PCA9557_Obj){},
};
OcGpio_Port fe_watchdog_io = {
.fn_table = &GpioPCA9557_fnTable,
.cfg = &(PCA9557_Cfg) {
.i2c_dev = { OC_CONNECT1_I2C2, RFFE_IO_REVPOWER_ALERT_ADDR },
},
.cfg =
&(PCA9557_Cfg){
.i2c_dev = { OC_CONNECT1_I2C2, RFFE_IO_REVPOWER_ALERT_ADDR },
},
.object_data = &(PCA9557_Obj){},
};
OcGpio_Port sync_io = {
OcGpio_Port sync_io = {
.fn_table = &GpioSX1509_fnTable,
.cfg = &(SX1509_Cfg) {
.i2c_dev = { OC_CONNECT1_I2C7, SYNC_IO_DEVICE_ADDR },
.pin_irq = &(OcGpio_Pin){ &ec_io, OC_EC_SYNC_IOEXP_ALERT },
},
.cfg =
&(SX1509_Cfg){
.i2c_dev = { OC_CONNECT1_I2C7, SYNC_IO_DEVICE_ADDR },
.pin_irq = &(OcGpio_Pin){ &ec_io, OC_EC_SYNC_IOEXP_ALERT },
},
.object_data = &(SX1509_Obj){},
};
@@ -498,8 +495,8 @@ void OC_CONNECT1_initGPIO(void)
*/
/* Place into subsections to allow the TI linker to remove items properly */
#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_SECTION(I2C_config, ".const:I2C_config")
#pragma DATA_SECTION(i2cTivaHWAttrs, ".const:i2cTivaHWAttrs")
# pragma DATA_SECTION(I2C_config, ".const:I2C_config")
# pragma DATA_SECTION(i2cTivaHWAttrs, ".const:i2cTivaHWAttrs")
#endif
#include <ti/drivers/I2C.h>
@@ -508,89 +505,57 @@ void OC_CONNECT1_initGPIO(void)
I2CTiva_Object i2cTivaObjects[OC_CONNECT1_I2CCOUNT];
const I2CTiva_HWAttrs i2cTivaHWAttrs[OC_CONNECT1_I2CCOUNT] = {
[OC_CONNECT1_I2C0] = {
.baseAddr = I2C0_BASE,
.intNum = INT_I2C0,
.intPriority = (~0)
},
[OC_CONNECT1_I2C1] = {
.baseAddr = I2C1_BASE,
.intNum = INT_I2C1,
.intPriority = (~0)
},
[OC_CONNECT1_I2C2] = {
.baseAddr = I2C2_BASE,
.intNum = INT_I2C2,
.intPriority = (~0)
},
[OC_CONNECT1_I2C3] = {
.baseAddr = I2C3_BASE,
.intNum = INT_I2C3,
.intPriority = (~0)
},
[OC_CONNECT1_I2C4] = {
.baseAddr = I2C4_BASE,
.intNum = INT_I2C4,
.intPriority = (~0)
},
[OC_CONNECT1_I2C6] = {
.baseAddr = I2C6_BASE,
.intNum = INT_I2C6,
.intPriority = (~0)
},
[OC_CONNECT1_I2C7] = {
.baseAddr = I2C7_BASE,
.intNum = INT_I2C7,
.intPriority = (~0)
},
[OC_CONNECT1_I2C8] = {
.baseAddr = I2C8_BASE,
.intNum = INT_I2C8,
.intPriority = (~0)
},
[OC_CONNECT1_I2C0] = { .baseAddr = I2C0_BASE,
.intNum = INT_I2C0,
.intPriority = (~0) },
[OC_CONNECT1_I2C1] = { .baseAddr = I2C1_BASE,
.intNum = INT_I2C1,
.intPriority = (~0) },
[OC_CONNECT1_I2C2] = { .baseAddr = I2C2_BASE,
.intNum = INT_I2C2,
.intPriority = (~0) },
[OC_CONNECT1_I2C3] = { .baseAddr = I2C3_BASE,
.intNum = INT_I2C3,
.intPriority = (~0) },
[OC_CONNECT1_I2C4] = { .baseAddr = I2C4_BASE,
.intNum = INT_I2C4,
.intPriority = (~0) },
[OC_CONNECT1_I2C6] = { .baseAddr = I2C6_BASE,
.intNum = INT_I2C6,
.intPriority = (~0) },
[OC_CONNECT1_I2C7] = { .baseAddr = I2C7_BASE,
.intNum = INT_I2C7,
.intPriority = (~0) },
[OC_CONNECT1_I2C8] = { .baseAddr = I2C8_BASE,
.intNum = INT_I2C8,
.intPriority = (~0) },
};
const I2C_Config I2C_config[] = {
[OC_CONNECT1_I2C0] = {
.fxnTablePtr = &I2CTiva_fxnTable,
.object = &i2cTivaObjects[OC_CONNECT1_I2C0],
.hwAttrs = &i2cTivaHWAttrs[OC_CONNECT1_I2C0]
},
[OC_CONNECT1_I2C1] = {
.fxnTablePtr = &I2CTiva_fxnTable,
.object = &i2cTivaObjects[OC_CONNECT1_I2C1],
.hwAttrs = &i2cTivaHWAttrs[OC_CONNECT1_I2C1]
},
[OC_CONNECT1_I2C2] = {
.fxnTablePtr = &I2CTiva_fxnTable,
.object = &i2cTivaObjects[OC_CONNECT1_I2C2],
.hwAttrs = &i2cTivaHWAttrs[OC_CONNECT1_I2C2]
},
[OC_CONNECT1_I2C3] = {
.fxnTablePtr = &I2CTiva_fxnTable,
.object = &i2cTivaObjects[OC_CONNECT1_I2C3],
.hwAttrs = &i2cTivaHWAttrs[OC_CONNECT1_I2C3]
},
[OC_CONNECT1_I2C4] = {
.fxnTablePtr = &I2CTiva_fxnTable,
.object = &i2cTivaObjects[OC_CONNECT1_I2C4],
.hwAttrs = &i2cTivaHWAttrs[OC_CONNECT1_I2C4]
},
[OC_CONNECT1_I2C6] = {
.fxnTablePtr = &I2CTiva_fxnTable,
.object = &i2cTivaObjects[OC_CONNECT1_I2C6],
.hwAttrs = &i2cTivaHWAttrs[OC_CONNECT1_I2C6]
},
[OC_CONNECT1_I2C7] = {
.fxnTablePtr = &I2CTiva_fxnTable,
.object = &i2cTivaObjects[OC_CONNECT1_I2C7],
.hwAttrs = &i2cTivaHWAttrs[OC_CONNECT1_I2C7]
},
[OC_CONNECT1_I2C8] = {
.fxnTablePtr = &I2CTiva_fxnTable,
.object = &i2cTivaObjects[OC_CONNECT1_I2C8],
.hwAttrs = &i2cTivaHWAttrs[OC_CONNECT1_I2C8]
},
[OC_CONNECT1_I2C0] = { .fxnTablePtr = &I2CTiva_fxnTable,
.object = &i2cTivaObjects[OC_CONNECT1_I2C0],
.hwAttrs = &i2cTivaHWAttrs[OC_CONNECT1_I2C0] },
[OC_CONNECT1_I2C1] = { .fxnTablePtr = &I2CTiva_fxnTable,
.object = &i2cTivaObjects[OC_CONNECT1_I2C1],
.hwAttrs = &i2cTivaHWAttrs[OC_CONNECT1_I2C1] },
[OC_CONNECT1_I2C2] = { .fxnTablePtr = &I2CTiva_fxnTable,
.object = &i2cTivaObjects[OC_CONNECT1_I2C2],
.hwAttrs = &i2cTivaHWAttrs[OC_CONNECT1_I2C2] },
[OC_CONNECT1_I2C3] = { .fxnTablePtr = &I2CTiva_fxnTable,
.object = &i2cTivaObjects[OC_CONNECT1_I2C3],
.hwAttrs = &i2cTivaHWAttrs[OC_CONNECT1_I2C3] },
[OC_CONNECT1_I2C4] = { .fxnTablePtr = &I2CTiva_fxnTable,
.object = &i2cTivaObjects[OC_CONNECT1_I2C4],
.hwAttrs = &i2cTivaHWAttrs[OC_CONNECT1_I2C4] },
[OC_CONNECT1_I2C6] = { .fxnTablePtr = &I2CTiva_fxnTable,
.object = &i2cTivaObjects[OC_CONNECT1_I2C6],
.hwAttrs = &i2cTivaHWAttrs[OC_CONNECT1_I2C6] },
[OC_CONNECT1_I2C7] = { .fxnTablePtr = &I2CTiva_fxnTable,
.object = &i2cTivaObjects[OC_CONNECT1_I2C7],
.hwAttrs = &i2cTivaHWAttrs[OC_CONNECT1_I2C7] },
[OC_CONNECT1_I2C8] = { .fxnTablePtr = &I2CTiva_fxnTable,
.object = &i2cTivaObjects[OC_CONNECT1_I2C8],
.hwAttrs = &i2cTivaHWAttrs[OC_CONNECT1_I2C8] },
{ NULL, NULL, NULL }
};
@@ -693,8 +658,8 @@ void OC_CONNECT1_initI2C(void)
*/
/* Place into subsections to allow the TI linker to remove items properly */
#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_SECTION(SPI_config, ".const:SPI_config")
#pragma DATA_SECTION(spiTivaDMAHWAttrs, ".const:spiTivaDMAHWAttrs")
# pragma DATA_SECTION(SPI_config, ".const:SPI_config")
# pragma DATA_SECTION(spiTivaDMAHWAttrs, ".const:spiTivaDMAHWAttrs")
#endif
#include <ti/drivers/SPI.h>
@@ -703,36 +668,32 @@ void OC_CONNECT1_initI2C(void)
SPITivaDMA_Object spiTivaDMAObjects[OC_CONNECT1_SPICOUNT];
#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_ALIGN(spiTivaDMAscratchBuf, 32)
# pragma DATA_ALIGN(spiTivaDMAscratchBuf, 32)
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma data_alignment=32
# pragma data_alignment = 32
#elif defined(__GNUC__)
__attribute__ ((aligned (32)))
__attribute__((aligned(32)))
#endif
uint32_t spiTivaDMAscratchBuf[OC_CONNECT1_SPICOUNT];
const SPITivaDMA_HWAttrs spiTivaDMAHWAttrs[OC_CONNECT1_SPICOUNT] = {
{
.baseAddr = SSI1_BASE,
.intNum = INT_SSI1,
.intPriority = (~0),
.scratchBufPtr = &spiTivaDMAscratchBuf[0],
.defaultTxBufValue = 0,
.rxChannelIndex = UDMA_CHANNEL_SSI1RX,
.txChannelIndex = UDMA_CHANNEL_SSI1TX,
.channelMappingFxn = uDMAChannelAssign,
.rxChannelMappingFxnArg = UDMA_CH24_SSI1RX,
.txChannelMappingFxnArg = UDMA_CH25_SSI1TX
},
{ .baseAddr = SSI1_BASE,
.intNum = INT_SSI1,
.intPriority = (~0),
.scratchBufPtr = &spiTivaDMAscratchBuf[0],
.defaultTxBufValue = 0,
.rxChannelIndex = UDMA_CHANNEL_SSI1RX,
.txChannelIndex = UDMA_CHANNEL_SSI1TX,
.channelMappingFxn = uDMAChannelAssign,
.rxChannelMappingFxnArg = UDMA_CH24_SSI1RX,
.txChannelMappingFxnArg = UDMA_CH25_SSI1TX },
};
const SPI_Config SPI_config[] = {
[OC_CONNECT1_SPI0] = {
.fxnTablePtr = &SPITivaDMA_fxnTable,
.object = &spiTivaDMAObjects[OC_CONNECT1_SPI0],
.hwAttrs = &spiTivaDMAHWAttrs[OC_CONNECT1_SPI0]
},
{NULL, NULL, NULL},
[OC_CONNECT1_SPI0] = { .fxnTablePtr = &SPITivaDMA_fxnTable,
.object = &spiTivaDMAObjects[OC_CONNECT1_SPI0],
.hwAttrs = &spiTivaDMAHWAttrs[OC_CONNECT1_SPI0] },
{ NULL, NULL, NULL },
};
/*
* ======== OC_CONNECT1_initSPI ========
@@ -757,38 +718,35 @@ void OC_CONNECT1_initSPI(void)
*/
/* Place into subsections to allow the TI linker to remove items properly */
#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_SECTION(UART_config, ".const:UART_config")
#pragma DATA_SECTION(uartTivaHWAttrs, ".const:uartTivaHWAttrs")
# pragma DATA_SECTION(UART_config, ".const:UART_config")
# pragma DATA_SECTION(uartTivaHWAttrs, ".const:uartTivaHWAttrs")
#endif
#include <ti/drivers/UART.h>
#if TI_DRIVERS_UART_DMA
#include <ti/drivers/uart/UARTTivaDMA.h>
# include <ti/drivers/uart/UARTTivaDMA.h>
UARTTivaDMA_Object uartTivaObjects[OC_CONNECT1_UARTCOUNT];
const UARTTivaDMA_HWAttrs uartTivaHWAttrs[OC_CONNECT1_UARTCOUNT] = {
[OC_CONNECT1_UART3] = {
.baseAddr = UART0_BASE,
.intNum = INT_UART0,
.intPriority = (~0),
.rxChannelIndex = UDMA_CH8_UART0RX,
.txChannelIndex = UDMA_CH9_UART0TX,
}
};
const UARTTivaDMA_HWAttrs uartTivaHWAttrs[OC_CONNECT1_UARTCOUNT] =
{ [OC_CONNECT1_UART3] = {
.baseAddr = UART0_BASE,
.intNum = INT_UART0,
.intPriority = (~0),
.rxChannelIndex = UDMA_CH8_UART0RX,
.txChannelIndex = UDMA_CH9_UART0TX,
} };
const UART_Config UART_config[] = {
[OC_CONNECT1_UART3] = {
.fxnTablePtr = &UARTTivaDMA_fxnTable,
.object = &uartTivaObjects[0],
.hwAttrs = &uartTivaHWAttrs[0]
},
[OC_CONNECT1_UART3] = { .fxnTablePtr = &UARTTivaDMA_fxnTable,
.object = &uartTivaObjects[0],
.hwAttrs = &uartTivaHWAttrs[0] },
{ NULL, NULL, NULL }
};
#else
#include <ti/drivers/uart/UARTTiva.h>
#include "devices/i2c/XR20M1170.h" // TODO: is devices the right directory? also, is it confusing to have this in i2c?
#include "devices/uart/UartMon.h"
# include <ti/drivers/uart/UARTTiva.h>
# include "devices/i2c/XR20M1170.h" // TODO: is devices the right directory? also, is it confusing to have this in i2c?
# include "devices/uart/UartMon.h"
UARTTiva_Object uartTivaObjects[3];
unsigned char uartTivaRingBuffer[3][64];
@@ -798,30 +756,24 @@ unsigned char XR20M1170RingBuffer[1][64];
// TODO: probably more efficient to use DMA drivers
const UARTTiva_HWAttrs uartTivaHWAttrs[] = {
{
.baseAddr = UART0_BASE,
.intNum = INT_UART0,
.intPriority = (~0),
.flowControl = UART_FLOWCONTROL_NONE,
.ringBufPtr = uartTivaRingBuffer[0],
.ringBufSize = sizeof(uartTivaRingBuffer[0])
},
{
.baseAddr = UART3_BASE,
.intNum = INT_UART3,
.intPriority = (~0),
.flowControl = UART_FLOWCONTROL_NONE,
.ringBufPtr = uartTivaRingBuffer[1],
.ringBufSize = sizeof(uartTivaRingBuffer[1])
},
{
.baseAddr = UART4_BASE,
.intNum = INT_UART4,
.intPriority = (~0),
.flowControl = UART_FLOWCONTROL_RX | UART_FLOWCONTROL_TX,
.ringBufPtr = uartTivaRingBuffer[2],
.ringBufSize = sizeof(uartTivaRingBuffer[2])
},
{ .baseAddr = UART0_BASE,
.intNum = INT_UART0,
.intPriority = (~0),
.flowControl = UART_FLOWCONTROL_NONE,
.ringBufPtr = uartTivaRingBuffer[0],
.ringBufSize = sizeof(uartTivaRingBuffer[0]) },
{ .baseAddr = UART3_BASE,
.intNum = INT_UART3,
.intPriority = (~0),
.flowControl = UART_FLOWCONTROL_NONE,
.ringBufPtr = uartTivaRingBuffer[1],
.ringBufSize = sizeof(uartTivaRingBuffer[1]) },
{ .baseAddr = UART4_BASE,
.intNum = INT_UART4,
.intPriority = (~0),
.flowControl = UART_FLOWCONTROL_RX | UART_FLOWCONTROL_TX,
.ringBufPtr = uartTivaRingBuffer[2],
.ringBufSize = sizeof(uartTivaRingBuffer[2]) },
};
// TODO: flow control settings
@@ -834,11 +786,12 @@ const XR20M1170_HWAttrs XR20M1170HWAttrs = {
// i2c bit rate
// uart interrupt
.i2cIndex = OC_CONNECT1_I2C7,
.i2cSlaveAddress = 0x60 >> 1, // TODO: i2c driver uses 7-bit address...sort of annoying
.i2cSlaveAddress =
0x60 >> 1, // TODO: i2c driver uses 7-bit address...sort of annoying
.xtal1_freq = 14745600, // 14.7456 MHz
.pin_irq = &(OcGpio_Pin){ &gbc_io_0, 0, OCGPIO_CFG_IN_PU },
.flowControl = XR20M1170_FLOWCONTROL_TX | XR20M1170_FLOWCONTROL_RX,
.ringBufPtr = XR20M1170RingBuffer[0],
.ringBufPtr = XR20M1170RingBuffer[0],
.ringBufSize = sizeof(XR20M1170RingBuffer[0]),
};
@@ -849,31 +802,24 @@ const UartMon_Cfg uart_mon_cfg = {
};
const UART_Config UART_config[OC_CONNECT1_UARTCOUNT + 1] = {
[OC_CONNECT1_UART0] = {
.fxnTablePtr = &UARTTiva_fxnTable,
.object = &uartTivaObjects[0],
.hwAttrs = &uartTivaHWAttrs[0]
},
[OC_CONNECT1_UART3] = {
.fxnTablePtr = &UARTTiva_fxnTable,
.object = &uartTivaObjects[1],
.hwAttrs = &uartTivaHWAttrs[1]
},
[OC_CONNECT1_UART4] = {
.fxnTablePtr = &UARTTiva_fxnTable,
.object = &uartTivaObjects[2],
.hwAttrs = &uartTivaHWAttrs[2]
},
[OC_CONNECT1_UARTXR0] = {
.fxnTablePtr = &XR20M1170_fxnTable,
.object = &XR20M1170Objects,
.hwAttrs = &XR20M1170HWAttrs
},
[OC_CONNECT1_UARTMON] = {
.fxnTablePtr = &UartMon_fxnTable,
.object = &uart_mon_obj,
.hwAttrs = &uart_mon_cfg,
},
[OC_CONNECT1_UART0] = { .fxnTablePtr = &UARTTiva_fxnTable,
.object = &uartTivaObjects[0],
.hwAttrs = &uartTivaHWAttrs[0] },
[OC_CONNECT1_UART3] = { .fxnTablePtr = &UARTTiva_fxnTable,
.object = &uartTivaObjects[1],
.hwAttrs = &uartTivaHWAttrs[1] },
[OC_CONNECT1_UART4] = { .fxnTablePtr = &UARTTiva_fxnTable,
.object = &uartTivaObjects[2],
.hwAttrs = &uartTivaHWAttrs[2] },
[OC_CONNECT1_UARTXR0] = { .fxnTablePtr = &XR20M1170_fxnTable,
.object = &XR20M1170Objects,
.hwAttrs = &XR20M1170HWAttrs },
[OC_CONNECT1_UARTMON] =
{
.fxnTablePtr = &UartMon_fxnTable,
.object = &uart_mon_obj,
.hwAttrs = &uart_mon_cfg,
},
{ NULL, NULL, NULL }
};
@@ -889,13 +835,13 @@ void OC_CONNECT1_initUART(void)
GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
// AP UART
//SysCtlPeripheralEnable(SYSCTL_PERIPH_UART3);
//GPIOPinConfigure(GPIO_PA4_U3RX);
//GPIOPinConfigure(GPIO_PA5_U3TX);
//GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_4 | GPIO_PIN_5);
// SysCtlPeripheralEnable(SYSCTL_PERIPH_UART3);
// GPIOPinConfigure(GPIO_PA4_U3RX);
// GPIOPinConfigure(GPIO_PA5_U3TX);
// GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_4 | GPIO_PIN_5);
// XR20M1170 IRQ pin
//GPIOPinTypeGPIOInput(GPIO_PORTE_BASE, GPIO_PIN_5);
// GPIOPinTypeGPIOInput(GPIO_PORTE_BASE, GPIO_PIN_5);
// GSM Module UART
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART4);
@@ -903,13 +849,13 @@ void OC_CONNECT1_initUART(void)
GPIOPinConfigure(GPIO_PK1_U4TX);
GPIOPinConfigure(GPIO_PK2_U4RTS);
GPIOPinConfigure(GPIO_PK3_U4CTS);
GPIOPinTypeUART(GPIO_PORTK_BASE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 |
GPIO_PIN_3);
GPIOPinTypeUART(GPIO_PORTK_BASE,
GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3);
/* Initialize the UART driver */
#if TI_DRIVERS_UART_DMA
# if TI_DRIVERS_UART_DMA
OC_CONNECT1_initDMA();
#endif
# endif
UART_init();
}
#endif /* TI_DRIVERS_UART_DMA */
@@ -962,8 +908,7 @@ void OC_CONNECT1_initUSB(OC_CONNECT1_USBMode usbMode)
* program. PQ4 is active low; set the pin as input with a weak
* pull-up.
*/
GPIOPadConfigSet(GPIO_PORTQ_BASE, GPIO_PIN_4,
GPIO_STRENGTH_2MA,
GPIOPadConfigSet(GPIO_PORTQ_BASE, GPIO_PIN_4, GPIO_STRENGTH_2MA,
GPIO_PIN_TYPE_STD_WPU);
GPIOIntTypeSet(GPIO_PORTQ_BASE, GPIO_PIN_4, GPIO_FALLING_EDGE);
GPIOIntClear(GPIO_PORTQ_BASE, GPIO_PIN_4);
@@ -984,8 +929,8 @@ void OC_CONNECT1_initUSB(OC_CONNECT1_USBMode usbMode)
*/
/* Place into subsections to allow the TI linker to remove items properly */
#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_SECTION(Watchdog_config, ".const:Watchdog_config")
#pragma DATA_SECTION(watchdogTivaHWAttrs, ".const:watchdogTivaHWAttrs")
# pragma DATA_SECTION(Watchdog_config, ".const:Watchdog_config")
# pragma DATA_SECTION(watchdogTivaHWAttrs, ".const:watchdogTivaHWAttrs")
#endif
#include <ti/drivers/Watchdog.h>
@@ -994,20 +939,20 @@ void OC_CONNECT1_initUSB(OC_CONNECT1_USBMode usbMode)
WatchdogTiva_Object watchdogTivaObjects[OC_CONNECT1_WATCHDOGCOUNT];
const WatchdogTiva_HWAttrs watchdogTivaHWAttrs[OC_CONNECT1_WATCHDOGCOUNT] = {
[OC_CONNECT1_WATCHDOG0] = {
.baseAddr = WATCHDOG0_BASE,
.intNum = INT_WATCHDOG,
.intPriority = (~0),
.reloadValue = 80000000 // 1 second period at default CPU clock freq
[OC_CONNECT1_WATCHDOG0] =
{
.baseAddr = WATCHDOG0_BASE,
.intNum = INT_WATCHDOG,
.intPriority = (~0),
.reloadValue = 80000000 // 1 second period at default CPU clock freq
},
};
const Watchdog_Config Watchdog_config[] = {
[OC_CONNECT1_WATCHDOG0] = {
.fxnTablePtr = &WatchdogTiva_fxnTable,
.object = &watchdogTivaObjects[OC_CONNECT1_WATCHDOG0],
.hwAttrs = &watchdogTivaHWAttrs[OC_CONNECT1_WATCHDOG0]
},
[OC_CONNECT1_WATCHDOG0] =
{ .fxnTablePtr = &WatchdogTiva_fxnTable,
.object = &watchdogTivaObjects[OC_CONNECT1_WATCHDOG0],
.hwAttrs = &watchdogTivaHWAttrs[OC_CONNECT1_WATCHDOG0] },
{ NULL, NULL, NULL },
};

187
firmware/ec/platform/oc-sdr/cfg/OC_CONNECT_FE.c
View File

@@ -42,54 +42,56 @@ Eeprom_Cfg eeprom_fe_inv = {
// FE Channel 1 Power sensor.
INA226_Dev fe_ch1_ps_5_7v = {
/* CH1 5.7V Sensor */
.cfg = {
.dev = {
.bus = OC_CONNECT1_I2C4,
.slave_addr = RFFE_INA226_CH1_5_7V_ADDR,
.cfg =
{
.dev =
{
.bus = OC_CONNECT1_I2C4,
.slave_addr = RFFE_INA226_CH1_5_7V_ADDR,
},
.pin_alert = &(OcGpio_Pin){ &ec_io, OC_EC_RFFE_TEMP_INA_ALERT },
},
.pin_alert = &(OcGpio_Pin){ &ec_io,
OC_EC_RFFE_TEMP_INA_ALERT },
},
};
//FE Channel 2 Power sensor.
// FE Channel 2 Power sensor.
INA226_Dev fe_ch2_ps_5_7v = {
/* CH2 5.7V Sensor */
.cfg = {
.dev = {
.bus = OC_CONNECT1_I2C4,
.slave_addr = RFFE_INA226_CH2_5_7V_ADDR,
.cfg =
{
.dev =
{
.bus = OC_CONNECT1_I2C4,
.slave_addr = RFFE_INA226_CH2_5_7V_ADDR,
},
.pin_alert = &(OcGpio_Pin){ &ec_io, OC_EC_RFFE_TEMP_INA_ALERT },
},
.pin_alert = &(OcGpio_Pin){ &ec_io,
OC_EC_RFFE_TEMP_INA_ALERT },
},
};
//FE Channel 1 temperature sensor.
// FE Channel 1 temperature sensor.
I2C_Dev fe_ch1_ts = {
.bus = OC_CONNECT1_I2C4,
.slave_addr = RFFE_CH1_TEMP_SENSOR_ADDR,
};
//FE Channel 2 temperature sensor.
// FE Channel 2 temperature sensor.
I2C_Dev fe_ch2_ts = (I2C_Dev){
.bus = OC_CONNECT1_I2C4,
.slave_addr = RFFE_CH2_TEMP_SENSOR_ADDR,
.bus = OC_CONNECT1_I2C4,
.slave_addr = RFFE_CH2_TEMP_SENSOR_ADDR,
};
//FE EEPROM inventory
void* fe_eeprom_inventory = &eeprom_fe_inv;
// FE EEPROM inventory
void *fe_eeprom_inventory = &eeprom_fe_inv;
//FE Channel 1 ADC
// FE Channel 1 ADC
I2C_Dev fe_ch1_ads7830 = {
.bus = OC_CONNECT1_I2C4,
.slave_addr = RFFE_CHANNEL1_ADC_ADDR,
.bus = OC_CONNECT1_I2C4,
.slave_addr = RFFE_CHANNEL1_ADC_ADDR,
};
//FE Channel 2 ADC
// FE Channel 2 ADC
I2C_Dev fe_ch2_ads7830 = {
.bus = OC_CONNECT1_I2C4,
.slave_addr = RFFE_CHANNEL2_ADC_ADDR,
.bus = OC_CONNECT1_I2C4,
.slave_addr = RFFE_CHANNEL2_ADC_ADDR,
};
Fe_Gain_Cfg fe_ch1_gain = {
@@ -98,111 +100,111 @@ Fe_Gain_Cfg fe_ch1_gain = {
/* CH1_TX_ATTN_P5DB */
.pin_tx_attn_p5db = { &fe_ch1_gain_io, 2 },
/* CH1_TX_ATTN_1DB */
.pin_tx_attn_1db = { &fe_ch1_gain_io, 3 },
.pin_tx_attn_1db = { &fe_ch1_gain_io, 3 },
/* CH1_TX_ATTN_2DB */
.pin_tx_attn_2db = { &fe_ch1_gain_io, 4 },
.pin_tx_attn_2db = { &fe_ch1_gain_io, 4 },
/* CH1_TX_ATTN_4DB */
.pin_tx_attn_4db = { &fe_ch1_gain_io, 5 },
.pin_tx_attn_4db = { &fe_ch1_gain_io, 5 },
/* CH1_TX_ATTN_8DB */
.pin_tx_attn_8db = { &fe_ch1_gain_io, 6 },
.pin_tx_attn_8db = { &fe_ch1_gain_io, 6 },
/* CH1_TX_ATTN_ENB */
.pin_tx_attn_enb = { &fe_ch1_gain_io, 7 },
.pin_tx_attn_enb = { &fe_ch1_gain_io, 7 },
};
Fe_Gain_Cfg fe_ch2_gain = {
/* CH2_TX_ATTN_16DB */
.pin_tx_attn_16db = { &fe_ch2_gain_io, 1 },
/* CH2_TX_ATTN_P5DB */
.pin_tx_attn_p5db = { &fe_ch2_gain_io, 2 },
/* CH2_TX_ATTN_1DB */
.pin_tx_attn_1db = { &fe_ch2_gain_io, 3 },
/* CH2_TX_ATTN_2DB */
.pin_tx_attn_2db = { &fe_ch2_gain_io, 4 },
/* CH2_TX_ATTN_4DB */
.pin_tx_attn_4db = { &fe_ch2_gain_io, 5 },
/* CH2_TX_ATTN_8DB */
.pin_tx_attn_8db = { &fe_ch2_gain_io, 6 },
/* CH2_TX_ATTN_ENB */
.pin_tx_attn_enb = { &fe_ch2_gain_io, 7 },
/* CH2_TX_ATTN_16DB */
.pin_tx_attn_16db = { &fe_ch2_gain_io, 1 },
/* CH2_TX_ATTN_P5DB */
.pin_tx_attn_p5db = { &fe_ch2_gain_io, 2 },
/* CH2_TX_ATTN_1DB */
.pin_tx_attn_1db = { &fe_ch2_gain_io, 3 },
/* CH2_TX_ATTN_2DB */
.pin_tx_attn_2db = { &fe_ch2_gain_io, 4 },
/* CH2_TX_ATTN_4DB */
.pin_tx_attn_4db = { &fe_ch2_gain_io, 5 },
/* CH2_TX_ATTN_8DB */
.pin_tx_attn_8db = { &fe_ch2_gain_io, 6 },
/* CH2_TX_ATTN_ENB */
.pin_tx_attn_enb = { &fe_ch2_gain_io, 7 },
};
Fe_Lna_Cfg fe_ch1_lna = {
/* CH1_RX_ATTN_P5DB */
.pin_rx_attn_p5db = { &fe_ch1_lna_io, 2 },
/* CH1_RX_ATTN_1DB */
.pin_rx_attn_1db = { &fe_ch1_lna_io, 3 },
.pin_rx_attn_1db = { &fe_ch1_lna_io, 3 },
/* CH1_RX_ATTN_2DB */
.pin_rx_attn_2db = { &fe_ch1_lna_io, 4 },
.pin_rx_attn_2db = { &fe_ch1_lna_io, 4 },
/* CH1_RX_ATTN_4DB */
.pin_rx_attn_4db = { &fe_ch1_lna_io, 5 },
.pin_rx_attn_4db = { &fe_ch1_lna_io, 5 },
/* CH1_RX_ATTN_8DB */
.pin_rx_attn_8db = { &fe_ch1_lna_io, 6 },
.pin_rx_attn_8db = { &fe_ch1_lna_io, 6 },
/* CH1_RX_ATTN_ENB */
.pin_rx_attn_enb = { &fe_ch1_lna_io, 7 },
.pin_rx_attn_enb = { &fe_ch1_lna_io, 7 },
};
Fe_Lna_Cfg fe_ch2_lna = {
/* CH2_RX_ATTN_P5DB */
.pin_rx_attn_p5db = { &fe_ch2_lna_io, 2 },
/* CH2_RX_ATTN_1DB */
.pin_rx_attn_1db = { &fe_ch2_lna_io, 3 },
.pin_rx_attn_1db = { &fe_ch2_lna_io, 3 },
/* CH2_RX_ATTN_2DB */
.pin_rx_attn_2db = { &fe_ch2_lna_io, 4 },
.pin_rx_attn_2db = { &fe_ch2_lna_io, 4 },
/* CH2_RX_ATTN_4DB */
.pin_rx_attn_4db = { &fe_ch2_lna_io, 5 },
.pin_rx_attn_4db = { &fe_ch2_lna_io, 5 },
/* CH2_RX_ATTN_8DB */
.pin_rx_attn_8db = { &fe_ch2_lna_io, 6 },
.pin_rx_attn_8db = { &fe_ch2_lna_io, 6 },
/* CH2_RX_ATTN_ENB */
.pin_rx_attn_enb = { &fe_ch2_lna_io, 7 },
.pin_rx_attn_enb = { &fe_ch2_lna_io, 7 },
};
//FE watch dog
// FE watch dog
Fe_Watchdog_Cfg fe_watchdog_cfg = {
/* AOSEL_FPGA */
.pin_aosel_fpga = { &fe_watchdog_io, 0 },
.pin_aosel_fpga = { &fe_watchdog_io, 0 },
/* CH2_RF_PWR_OFF */
.pin_ch2_rf_pwr_off = { &fe_watchdog_io, 1 },
/* CO6_WD */
.pin_co6_wd = { &fe_watchdog_io, 2 },
.pin_co6_wd = { &fe_watchdog_io, 2 },
/* CO5_WD */
.pin_co5_wd = { &fe_watchdog_io, 3 },
.pin_co5_wd = { &fe_watchdog_io, 3 },
/* CO4_WD */
.pin_co4_wd = { &fe_watchdog_io, 4 },
.pin_co4_wd = { &fe_watchdog_io, 4 },
/* CO3_WD */
.pin_co3_wd = { &fe_watchdog_io, 5 },
.pin_co3_wd = { &fe_watchdog_io, 5 },
/* CO2_WD */
.pin_co2_wd = { &fe_watchdog_io, 6 },
.pin_co2_wd = { &fe_watchdog_io, 6 },
/* COPOL_FPGA */
.pin_copol_fpga = { &fe_watchdog_io, 7 },
.pin_copol_fpga = { &fe_watchdog_io, 7 },
};
Fe_gpioCfg fe_gpiocfg = {
/* EC_TRXFECONN_GPIO3/RF_PGOOD_LDO */
.pin_rf_pgood_ldo = { &ec_io, OC_EC_FE_PWR_GD },
/* FE_12V_CTRL */
.pin_fe_12v_ctrl = { &ec_io, OC_EC_FE_CONTROL },
.pin_trxfe_conn_reset = { &ec_io, OC_EC_FE_TRXFE_CONN_RESET },
/* EC_TRXFECONN_GPIO3/RF_PGOOD_LDO */
.pin_rf_pgood_ldo = { &ec_io, OC_EC_FE_PWR_GD },
/* FE_12V_CTRL */
.pin_fe_12v_ctrl = { &ec_io, OC_EC_FE_CONTROL },
.pin_trxfe_conn_reset = { &ec_io, OC_EC_FE_TRXFE_CONN_RESET },
};
//FE Ch1 TX Gain control
Fe_Ch1_Gain_Cfg fe_ch1_tx_gain_cfg = (Fe_Ch1_Gain_Cfg) {
// FE Ch1 TX Gain control
Fe_Ch1_Gain_Cfg fe_ch1_tx_gain_cfg = (Fe_Ch1_Gain_Cfg){
.fe_gain_cfg = &fe_ch1_gain,
};
//FE Ch2 TX Gain control
Fe_Ch2_Gain_Cfg fe_ch2_tx_gain_cfg = (Fe_Ch2_Gain_Cfg) {
// FE Ch2 TX Gain control
Fe_Ch2_Gain_Cfg fe_ch2_tx_gain_cfg = (Fe_Ch2_Gain_Cfg){
/* CH1_2G_LB_BAND_SEL_L */
.pin_ch1_2g_lb_band_sel_l = { &fe_ch2_gain_io, 0 },
.fe_gain_cfg = &fe_ch2_gain,
};
//FE Ch1 LNA config
Fe_Ch1_Lna_Cfg fe_ch1_rx_gain_cfg = (Fe_Ch1_Lna_Cfg) {
// FE Ch1 LNA config
Fe_Ch1_Lna_Cfg fe_ch1_rx_gain_cfg = (Fe_Ch1_Lna_Cfg){
.fe_lna_cfg = &fe_ch1_lna,
};
//FE Ch2 LNA config
Fe_Ch2_Lna_Cfg fe_ch2_rx_gain_cfg = (Fe_Ch2_Lna_Cfg) {
// FE Ch2 LNA config
Fe_Ch2_Lna_Cfg fe_ch2_rx_gain_cfg = (Fe_Ch2_Lna_Cfg){
/* CH1_RF_PWR_OFF */
.pin_ch1_rf_pwr_off = { &fe_ch2_lna_io, 1 },
.fe_lna_cfg = &fe_ch2_lna,
@@ -225,11 +227,11 @@ RfWatchdog_Cfg fe_ch2_watchdog = {
/* FE GPIO's */
Fe_Cfg fe_rffecfg = {
.fe_gpio_cfg = &fe_gpiocfg,
.fe_ch1_gain_cfg = (Fe_Ch1_Gain_Cfg*)&fe_ch1_tx_gain_cfg,
.fe_ch2_gain_cfg = (Fe_Ch2_Gain_Cfg*)&fe_ch2_tx_gain_cfg,
.fe_ch1_lna_cfg = (Fe_Ch1_Lna_Cfg*)&fe_ch1_rx_gain_cfg,
.fe_ch2_lna_cfg = (Fe_Ch2_Lna_Cfg*)&fe_ch2_rx_gain_cfg,
.fe_watchdog_cfg = (Fe_Watchdog_Cfg*)&fe_watchdog_cfg,
.fe_ch1_gain_cfg = (Fe_Ch1_Gain_Cfg *)&fe_ch1_tx_gain_cfg,
.fe_ch2_gain_cfg = (Fe_Ch2_Gain_Cfg *)&fe_ch2_tx_gain_cfg,
.fe_ch1_lna_cfg = (Fe_Ch1_Lna_Cfg *)&fe_ch1_rx_gain_cfg,
.fe_ch2_lna_cfg = (Fe_Ch2_Lna_Cfg *)&fe_ch2_rx_gain_cfg,
.fe_watchdog_cfg = (Fe_Watchdog_Cfg *)&fe_watchdog_cfg,
};
FE_Ch_Band_cfg fe_ch1_bandcfg = {
@@ -240,19 +242,16 @@ FE_Ch_Band_cfg fe_ch2_bandcfg = {
.channel = RFFE_CHANNEL2,
};
Fe_Ch_Pwr_Cfg fe_ch1_pwrcfg = {
.channel = RFFE_CHANNEL1,
.fe_Rffecfg = (Fe_Cfg*)&fe_rffecfg
};
Fe_Ch_Pwr_Cfg fe_ch1_pwrcfg = { .channel = RFFE_CHANNEL1,
.fe_Rffecfg = (Fe_Cfg *)&fe_rffecfg };
Fe_Ch_Pwr_Cfg fe_ch2_pwrcfg = {
.channel = RFFE_CHANNEL2,
.fe_Rffecfg = (Fe_Cfg*)&fe_rffecfg
};
Fe_Ch_Pwr_Cfg fe_ch2_pwrcfg = { .channel = RFFE_CHANNEL2,
.fe_Rffecfg = (Fe_Cfg *)&fe_rffecfg };
// TestModule
// TestModule
TestMod_Cfg testModuleCfg = (TestMod_Cfg){
.g510_cfg = {
.g510_cfg =
{
.uart = OC_CONNECT1_UART4,
/* 2G_SIM_PRESENCE */
.pin_sim_present = { &gbc_io_1, 0, OCGPIO_CFG_IN_PU },
@@ -263,7 +262,7 @@ TestMod_Cfg testModuleCfg = (TestMod_Cfg){
/* EC_2GMODULE_PWR_ON */
.pin_pwr_en = { &gbc_io_1, 1, OCGPIO_CFG_INVERT },
},
.pin_ant_sw = {},
.pin_ant_sw = {},
};
// RFFE IO EXPANDERS
@@ -287,7 +286,7 @@ S_OCGPIO_Cfg debug_fe_ioexpanderx1D = {
.port = &fe_ch2_lna_io,
};
//FE Factory config
// FE Factory config
const ADT7481_Config fact_fe_ch1_adt7481_cfg = {
.lowlimit = -20,
.highlimit = 80,

320
firmware/ec/platform/oc-sdr/cfg/OC_CONNECT_GBC.c
View File

@@ -36,14 +36,14 @@ SCHEMA_IMPORT OcGpio_Port gbc_io_1;
SCHEMA_IMPORT const Driver_fxnTable LTC4274_fxnTable;
/* These are terrible pin names, but they match the net names... */
OcGpio_Pin pin_inven_eeprom_wp = { &gbc_io_0, 1, OCGPIO_CFG_OUT_OD_NOPULL };
OcGpio_Pin pin_s_id_eeprom_wp = { &gbc_io_0, 2, OCGPIO_CFG_OUT_OD_NOPULL };
OcGpio_Pin pin_tempsen_evt1 = { &gbc_io_0, 4 };
OcGpio_Pin pin_tempsen_evt2 = { &gbc_io_0, 5 };
OcGpio_Pin pin_tempsen_evt3 = { &gbc_io_0, 6 };
OcGpio_Pin pin_tempsen_evt4 = { &gbc_io_0, 7 };
OcGpio_Pin pin_tempsen_evt5 = { &gbc_io_0, 8 };
OcGpio_Pin eth_sw_tiva_intn = { &gbc_io_0, 11 };
OcGpio_Pin pin_inven_eeprom_wp = { &gbc_io_0, 1, OCGPIO_CFG_OUT_OD_NOPULL };
OcGpio_Pin pin_s_id_eeprom_wp = { &gbc_io_0, 2, OCGPIO_CFG_OUT_OD_NOPULL };
OcGpio_Pin pin_tempsen_evt1 = { &gbc_io_0, 4 };
OcGpio_Pin pin_tempsen_evt2 = { &gbc_io_0, 5 };
OcGpio_Pin pin_tempsen_evt3 = { &gbc_io_0, 6 };
OcGpio_Pin pin_tempsen_evt4 = { &gbc_io_0, 7 };
OcGpio_Pin pin_tempsen_evt5 = { &gbc_io_0, 8 };
OcGpio_Pin eth_sw_tiva_intn = { &gbc_io_0, 11 };
/*****************************************************************************
* EEPROM CONFIG
@@ -67,140 +67,150 @@ Eeprom_Cfg eeprom_gbc_inv = {
*****************************************************************************/
/* SPI AT45DB Flash Config */
AT45DB_Dev gbc_spi_flash_memory = {
.cfg = {
.dev = {
.bus = OC_CONNECT1_SPI0,
.chip_select = &(OcGpio_Pin){ &ec_io, OC_EC_FLASH_nCS },
},
.pin_alert = NULL,
},
.obj = {},
.cfg =
{
.dev =
{
.bus = OC_CONNECT1_SPI0,
.chip_select = &(OcGpio_Pin){ &ec_io, OC_EC_FLASH_nCS },
},
.pin_alert = NULL,
},
.obj = {},
};
/* Power SubSystem Config */
//Lead Acid Temperature sensor.
// Lead Acid Temperature sensor.
SE98A_Dev gbc_pwr_lead_acid_ts = {
.cfg = {
.dev = {
.bus = OC_CONNECT1_I2C1,
.slave_addr = PWR_LEAD_ACID_BATT_DEV_TEMP_SENS_ADDR
.cfg =
{
.dev = { .bus = OC_CONNECT1_I2C1,
.slave_addr = PWR_LEAD_ACID_BATT_DEV_TEMP_SENS_ADDR },
.pin_evt = &pin_tempsen_evt1,
},
.pin_evt = &pin_tempsen_evt1,
},
.obj = {},
};
//Lead acid battery charge controller.
// Lead acid battery charge controller.
LTC4015_Dev gbc_pwr_ext_bat_charger = {
.cfg = {
.i2c_dev = {
.bus = OC_CONNECT1_I2C0,
.slave_addr = 0x68, /* LTC4015 I2C address in 7-bit format */
},
.cfg =
{
.i2c_dev =
{
.bus = OC_CONNECT1_I2C0,
.slave_addr =
0x68, /* LTC4015 I2C address in 7-bit format */
},
.chem = LTC4015_CHEM_LEAD_ACID,
.r_snsb = PWR_EXT_BATT_RSNSB,
.r_snsi = PWR_EXT_BATT_RSNSI,
.cellcount = 6,
.pin_lt4015_i2c_sel = { &gbc_io_1, 4, OCGPIO_CFG_OUT_OD_NOPULL },
.pin_alert = &(OcGpio_Pin){ &ec_io,
OC_EC_PWR_LACID_ALERT },
.pin_alert = &(OcGpio_Pin){ &ec_io, OC_EC_PWR_LACID_ALERT },
},
.obj = {},
};
//Lithium ion battery charge controller.
LTC4015_Dev gbc_pwr_int_bat_charger = {
.cfg = {
.i2c_dev = {
.bus = OC_CONNECT1_I2C0,
.slave_addr = 0x68, /* LTC4015 I2C address in 7-bit format */
},
.chem = LTC4015_CHEM_LI_ION,
.r_snsb = PWR_INT_BATT_RSNSB,
.r_snsi = PWR_INT_BATT_RSNSI,
.cellcount = 3,
.pin_lt4015_i2c_sel = { &gbc_io_1, 4, OCGPIO_CFG_OUT_OD_NOPULL },
.pin_alert = &(OcGpio_Pin){ &ec_io, OC_EC_PWR_LION_ALERT },
},
.obj = {},
};
//Power Source Equipment
LTC4274_Dev gbc_pwr_pse = {
.cfg = {
.i2c_dev = {
.bus = OC_CONNECT1_I2C8,
.slave_addr = 0x2F, /* LTC4274 I2C address in 7-bit format */
},
.pin_evt = &(OcGpio_Pin){ &ec_io,
OC_EC_GBC_PSE_ALERT },
.reset_pin ={ &ec_io, OC_EC_PWR_PSE_RESET },
},
.obj = {},
};
//Power Device
// Lithium ion battery charge controller.
LTC4015_Dev gbc_pwr_int_bat_charger = {
.cfg =
{
.i2c_dev =
{
.bus = OC_CONNECT1_I2C0,
.slave_addr =
0x68, /* LTC4015 I2C address in 7-bit format */
},
.chem = LTC4015_CHEM_LI_ION,
.r_snsb = PWR_INT_BATT_RSNSB,
.r_snsi = PWR_INT_BATT_RSNSI,
.cellcount = 3,
.pin_lt4015_i2c_sel = { &gbc_io_1, 4, OCGPIO_CFG_OUT_OD_NOPULL },
.pin_alert = &(OcGpio_Pin){ &ec_io, OC_EC_PWR_LION_ALERT },
},
.obj = {},
};
// Power Source Equipment
LTC4274_Dev gbc_pwr_pse = {
.cfg =
{
.i2c_dev =
{
.bus = OC_CONNECT1_I2C8,
.slave_addr =
0x2F, /* LTC4274 I2C address in 7-bit format */
},
.pin_evt = &(OcGpio_Pin){ &ec_io, OC_EC_GBC_PSE_ALERT },
.reset_pin = { &ec_io, OC_EC_PWR_PSE_RESET },
},
.obj = {},
};
// Power Device
LTC4275_Dev gbc_pwr_pd = {
.cfg = {
.pin_evt = &(OcGpio_Pin){ &ec_io,
OC_EC_PD_PWRGD_ALERT },
.pin_detect = &(OcGpio_Pin){ &ec_io,
OC_EC_PWR_PD_NT2P },
.cfg =
{
.pin_evt = &(OcGpio_Pin){ &ec_io, OC_EC_PD_PWRGD_ALERT },
.pin_detect = &(OcGpio_Pin){ &ec_io, OC_EC_PWR_PD_NT2P },
},
.obj = {},
};
.obj = {},
};
//Power Source
PWRSRC_Dev gbc_pwr_powerSource = { /*Added as a place holder for now.*/
.cfg = {
// Power Source
PWRSRC_Dev gbc_pwr_powerSource = {
/*Added as a place holder for now.*/
.cfg =
{
/* SOLAR_AUX_PRSNT_N */
.pin_solar_aux_prsnt_n = { &ec_io, OC_EC_PWR_PRSNT_SOLAR_AUX },
.pin_solar_aux_prsnt_n = { &ec_io, OC_EC_PWR_PRSNT_SOLAR_AUX },
/* POE_PRSNT_N */
.pin_poe_prsnt_n = { &ec_io, OC_EC_PWR_PRSNT_POE },
.pin_poe_prsnt_n = { &ec_io, OC_EC_PWR_PRSNT_POE },
/* INT_BAT_PRSNT */
.pin_int_bat_prsnt = { &gbc_io_0, 11 },
.pin_int_bat_prsnt = { &gbc_io_0, 11 },
/* EXT_BAT_PRSNT */
.pin_ext_bat_prsnt = { &gbc_io_0, 12 },
.pin_ext_bat_prsnt = { &gbc_io_0, 12 },
},
.obj = {},
.obj = {},
};
/* BMS SubSystem Config */
//EC Power sensor for 12V rail.
// EC Power sensor for 12V rail.
INA226_Dev gbc_bms_ec_ps_12v = {
/* 12V Power Sensor */
.cfg = {
.dev = {
.bus = OC_CONNECT1_I2C6,
.slave_addr = BMS_EC_CURRENT_SENSOR_12V_ADDR,
.cfg =
{
.dev =
{
.bus = OC_CONNECT1_I2C6,
.slave_addr = BMS_EC_CURRENT_SENSOR_12V_ADDR,
},
.pin_alert = &(OcGpio_Pin){ &ec_io, OC_EC_GBC_INA_ALERT },
},
.pin_alert = &(OcGpio_Pin){ &ec_io,
OC_EC_GBC_INA_ALERT },
},
};
//EC Power sensor for 3.3V rail.
// EC Power sensor for 3.3V rail.
INA226_Dev gbc_bms_ec_ps_3p3v = {
/* 3.3V Power Sensor */
.cfg = {
.dev = {
.bus = OC_CONNECT1_I2C7,
.slave_addr = BMS_EC_CURRENT_SENSOR_3P3V_ADDR,
.cfg =
{
.dev =
{
.bus = OC_CONNECT1_I2C7,
.slave_addr = BMS_EC_CURRENT_SENSOR_3P3V_ADDR,
},
.pin_alert = &(OcGpio_Pin){ &ec_io, OC_EC_GBC_INA_ALERT },
},
.pin_alert = &(OcGpio_Pin){ &ec_io,
OC_EC_GBC_INA_ALERT },
},
};
// EC Temperature sensor.
SE98A_Dev gbc_bms_ec_ts = {
.cfg = {
.dev = {
.bus = OC_CONNECT1_I2C1,
.slave_addr = BMS_EC_TEMP_SENSOR_ADDR
},
.cfg =
{
.dev = { .bus = OC_CONNECT1_I2C1,
.slave_addr = BMS_EC_TEMP_SENSOR_ADDR },
.pin_evt = &pin_tempsen_evt2,
},
},
.obj = {},
};
@@ -217,116 +227,115 @@ Eth_Sw_Cfg g_eth_cfg = {
.eth_switch = {},
};
//PORT 0
// PORT 0
Eth_cfg gbc_eth_port0 = {
.eth_sw_cfg = &g_eth_cfg,
.eth_sw_port = PORT0,
};
//PORT 1
// PORT 1
Eth_cfg gbc_eth_port1 = {
.eth_sw_cfg = &g_eth_cfg,
.eth_sw_port = PORT1,
};
//PORT 2
// PORT 2
Eth_cfg gbc_eth_port2 = {
.eth_sw_cfg = &g_eth_cfg,
.eth_sw_port = PORT2,
};
//PORT 3
// PORT 3
Eth_cfg gbc_eth_port3 = {
.eth_sw_cfg = &g_eth_cfg,
.eth_sw_port = PORT3,
};
//PORT 4
// PORT 4
Eth_cfg gbc_eth_port4 = {
.eth_sw_cfg = &g_eth_cfg,
.eth_sw_port = PORT4,
};
/* GPP Subsystem Config*/
//EC Power sensor for 12V rail.
// EC Power sensor for 12V rail.
INA226_Dev gbc_gpp_ap_ps = {
.cfg = {
.dev = {
.bus = OC_CONNECT1_I2C6,
.slave_addr = GPP_AP_CURRENT_SENSOR_ADDR,
.cfg =
{
.dev =
{
.bus = OC_CONNECT1_I2C6,
.slave_addr = GPP_AP_CURRENT_SENSOR_ADDR,
},
.pin_alert = &(OcGpio_Pin){ &ec_io, OC_EC_GBC_AP_INA_ALERT },
},
.pin_alert = &(OcGpio_Pin){ &ec_io,
OC_EC_GBC_AP_INA_ALERT },
},
};
// AP Temperature sensor
SE98A_Dev gbc_gpp_ap_ts1 = {
.cfg = {
.dev = {
.bus = OC_CONNECT1_I2C1,
.slave_addr = GPP_AP_TEMPSENS1_ADDR
},
.pin_evt = &pin_tempsen_evt3,
},
.obj = {},
.cfg =
{
.dev = { .bus = OC_CONNECT1_I2C1,
.slave_addr = GPP_AP_TEMPSENS1_ADDR },
.pin_evt = &pin_tempsen_evt3,
},
.obj = {},
};
SE98A_Dev gbc_gpp_ap_ts2 = {
.cfg = {
.dev = {
.bus = OC_CONNECT1_I2C1,
.slave_addr = GPP_AP_TEMPSENS2_ADDR
},
.cfg =
{
.dev = { .bus = OC_CONNECT1_I2C1,
.slave_addr = GPP_AP_TEMPSENS2_ADDR },
.pin_evt = &pin_tempsen_evt5,
},
},
.obj = {},
};
SE98A_Dev gbc_gpp_ap_ts3 = {
.cfg = {
.dev = {
.bus = OC_CONNECT1_I2C1,
.slave_addr = GPP_AP_TEMPSENS3_ADDR
},
.pin_evt = &pin_tempsen_evt4,
},
.obj = {},
.cfg =
{
.dev = { .bus = OC_CONNECT1_I2C1,
.slave_addr = GPP_AP_TEMPSENS3_ADDR },
.pin_evt = &pin_tempsen_evt4,
},
.obj = {},
};
//mSATA power sensor
// mSATA power sensor
INA226_Dev gbc_gpp_msata_ps = {
.cfg = {
.dev = {
.bus = OC_CONNECT1_I2C6,
.slave_addr = GPP_MSATA_CURRENT_SENSOR_ADDR,
.cfg =
{
.dev =
{
.bus = OC_CONNECT1_I2C6,
.slave_addr = GPP_MSATA_CURRENT_SENSOR_ADDR,
},
.pin_alert = &(OcGpio_Pin){ &ec_io, OC_EC_GBC_AP_INA_ALERT },
},
.pin_alert = &(OcGpio_Pin){ &ec_io,
OC_EC_GBC_AP_INA_ALERT },
},
};
Gpp_gpioCfg gbc_gpp_gpioCfg = (Gpp_gpioCfg){
/* SOC_PLTRST_N */
.pin_soc_pltrst_n = { &ec_io, OC_EC_GPP_SOC_PLTRST },
.pin_soc_pltrst_n = { &ec_io, OC_EC_GPP_SOC_PLTRST },
/* TIVA_SOC_GPIO2 */
.pin_ap_boot_alert1 = { &ec_io, OC_EC_GPP_AP_BM_1 },
.pin_ap_boot_alert1 = { &ec_io, OC_EC_GPP_AP_BM_1 },
/* TIVA_SOC_GPIO3 */
.pin_ap_boot_alert2 = { &ec_io, OC_EC_GPP_AP_BM_2 },
.pin_ap_boot_alert2 = { &ec_io, OC_EC_GPP_AP_BM_2 },
/* SOC_COREPWROK */
.pin_soc_corepwr_ok = { &ec_io, OC_EC_GPP_PMIC_CORE_PWR },
.pin_soc_corepwr_ok = { &ec_io, OC_EC_GPP_PMIC_CORE_PWR },
/* MSATA_EC_DAS */
.pin_msata_ec_das = { &ec_io, OC_EC_GPP_MSATA_DAS },
.pin_msata_ec_das = { &ec_io, OC_EC_GPP_MSATA_DAS },
/* LT4256_EC_PWRGD */
.pin_lt4256_ec_pwrgd = { &ec_io, OC_EC_GPP_PWRGD_PROTECTION },
.pin_lt4256_ec_pwrgd = { &ec_io, OC_EC_GPP_PWRGD_PROTECTION },
/* AP_12V_ONOFF */
.pin_ap_12v_onoff = { &ec_io, OC_EC_GPP_PMIC_CTRL },
.pin_ap_12v_onoff = { &ec_io, OC_EC_GPP_PMIC_CTRL },
/* EC_RESET_TO_PROC */
.pin_ec_reset_to_proc = { &ec_io, OC_EC_GPP_RST_TO_PROC },
};
/* Debug Subsystem Config.*/
//I2C Bus
// I2C Bus
S_I2C_Cfg debug_I2C0 = {
.bus = OC_CONNECT1_I2C0,
};
@@ -416,7 +425,7 @@ S_MDIO_Cfg debug_mdio_global1 = {
.port = OC_CONNECT1_GLOBAL1,
};
//Native GPIO
// Native GPIO
S_OCGPIO_Cfg debug_ec_gpio_pa = {
.port = &ec_io,
.group = PA,
@@ -501,9 +510,8 @@ S_OCGPIO_Cfg debug_gbc_ioexpanderx71 = {
.port = &gbc_io_0,
};
/* Factory Configuration for the Devices*/
//Power Factory Config.
// Power Factory Config.
const SE98A_Config fact_bc_se98a = {
.lowlimit = -20,
.highlimit = 75,
@@ -538,7 +546,7 @@ const LTC4274_Config fact_ltc4274_cfg = {
.pseHpEnable = LTC4274_HP_ENABLE,
};
//BMS factory config.
// BMS factory config.
const SE98A_Config fact_ec_se98a_cfg = {
.lowlimit = -20,
.highlimit = 75,
@@ -553,7 +561,7 @@ const INA226_Config fact_ec_3v_ps_cfg = {
.current_lim = 1000,
};
//GPP fact config
// GPP fact config
const SE98A_Config fact_ap_se98a_ts1_cfg = {
.lowlimit = -20,
.highlimit = 75,

37
firmware/ec/platform/oc-sdr/cfg/OC_CONNECT_LED.c
View File

@@ -15,33 +15,34 @@ SCHEMA_IMPORT OcGpio_Port sync_io;
/*****************************************************************************
* SYSTEM CONFIG
*****************************************************************************/
//LED Temperature sensor
// LED Temperature sensor
SE98A_Dev led_hci_ts = {
.cfg = {
.dev = {
.bus = OC_CONNECT1_I2C8,
.slave_addr = HCI_LED_TEMP_SENSOR_ADDR
.cfg =
{
.dev = { .bus = OC_CONNECT1_I2C8,
.slave_addr = HCI_LED_TEMP_SENSOR_ADDR },
.pin_evt = NULL,
},
.pin_evt = NULL,
},
.obj = {},
};
//LED IO Expander
HciLedCfg led_hci_ioexp ={
.sx1509_dev[HCI_LED_DRIVER_LEFT] = {
.bus = OC_CONNECT1_I2C8,
.slave_addr = LED_SX1509_LEFT_ADDRESS,
},
.sx1509_dev[HCI_LED_DRIVER_RIGHT] = {
.bus = OC_CONNECT1_I2C8,
.slave_addr = LED_SX1509_RIGHT_ADDRESS,
},
// LED IO Expander
HciLedCfg led_hci_ioexp = {
.sx1509_dev[HCI_LED_DRIVER_LEFT] =
{
.bus = OC_CONNECT1_I2C8,
.slave_addr = LED_SX1509_LEFT_ADDRESS,
},
.sx1509_dev[HCI_LED_DRIVER_RIGHT] =
{
.bus = OC_CONNECT1_I2C8,
.slave_addr = LED_SX1509_RIGHT_ADDRESS,
},
/* EC_GPIO */
.pin_ec_gpio = { &ec_io, OC_EC_HCI_LED_RESET },
};
//HCI factory Config
// HCI factory Config
const SE98A_Config fact_led_se98a_cfg = {
.lowlimit = -20,
.highlimit = 75,

54
firmware/ec/platform/oc-sdr/cfg/OC_CONNECT_SDR.c
View File

@@ -30,35 +30,37 @@ Eeprom_Cfg eeprom_sdr_inv = {
/* SDR Subsystem Config.*/
// SDR FPGA power sensor.
INA226_Dev sdr_fpga_ps = {
.cfg = {
.dev = {
.bus = OC_CONNECT1_I2C3,
.slave_addr = SDR_FPGA_CURRENT_SENSOR_ADDR,
.cfg =
{
.dev =
{
.bus = OC_CONNECT1_I2C3,
.slave_addr = SDR_FPGA_CURRENT_SENSOR_ADDR,
},
.pin_alert = &(OcGpio_Pin){ &ec_io, OC_EC_SDR_FPGA_TEMP_INA_ALERT },
},
.pin_alert = &(OcGpio_Pin){ &ec_io,
OC_EC_SDR_FPGA_TEMP_INA_ALERT },
},
};
//SDR FPGA temperature sensor
// SDR FPGA temperature sensor
I2C_Dev sdr_fpga_ts = {
.bus = OC_CONNECT1_I2C3,
.slave_addr = SDR_FPGA_TEMP_SENSOR_ADDR,
};
//SDR EEPROM
void* sdr_eeprom_inventory = &eeprom_sdr_inv;
// SDR EEPROM
void *sdr_eeprom_inventory = &eeprom_sdr_inv;
//SDR Power sensor
// SDR Power sensor
INA226_Dev sdr_ps = {
.cfg = {
.dev = {
.bus = OC_CONNECT1_I2C6,
.slave_addr = SDR_CURRENT_SENSOR_ADDR,
.cfg =
{
.dev =
{
.bus = OC_CONNECT1_I2C6,
.slave_addr = SDR_CURRENT_SENSOR_ADDR,
},
.pin_alert = &(OcGpio_Pin){ &ec_io, OC_EC_SDR_INA_ALERT },
},
.pin_alert = &(OcGpio_Pin){ &ec_io,
OC_EC_SDR_INA_ALERT },
},
};
// SDR IO EXPANDERS
@@ -66,7 +68,7 @@ S_OCGPIO_Cfg debug_sdr_ioexpanderx1E = {
.port = &sdr_fx3_io,
};
//SDR Factory config
// SDR Factory config
const INA226_Config fact_sdr_3v_ps_cfg = {
.current_lim = 3000,
};
@@ -81,17 +83,17 @@ const INA226_Config fact_sdr_fpga_ps_cfg = {
.current_lim = 500,
};
Sdr_gpioCfg sdr_gpioCfg = (Sdr_gpioCfg) {
Sdr_gpioCfg sdr_gpioCfg = (Sdr_gpioCfg){
/* EC_TRXFECONN_GPIO2/SDR_REG_LDO_PGOOD */
.pin_sdr_reg_ldo_pgood = { &ec_io, OC_EC_SDR_PWR_GD },
.pin_sdr_reg_ldo_pgood = { &ec_io, OC_EC_SDR_PWR_GD },
/* TRXFE_12V_ONOFF */
.pin_trxfe_12v_onoff = { &ec_io, OC_EC_SDR_PWR_CNTRL },
.pin_trxfe_12v_onoff = { &ec_io, OC_EC_SDR_PWR_CNTRL },
/* EC_FE_RESET_OUT/RF_FE_IO_RESET */
.pin_rf_fe_io_reset = { &ec_io, OC_EC_SDR_FE_IO_RESET_CTRL },
.pin_rf_fe_io_reset = { &ec_io, OC_EC_SDR_FE_IO_RESET_CTRL },
/* EC_TRXFECONN_GPIO1/SDR_RESET_IN */
.pin_sdr_reset_in = { &ec_io, OC_EC_SDR_DEVICE_CONTROL },
.pin_sdr_reset_in = { &ec_io, OC_EC_SDR_DEVICE_CONTROL },
/* EC_TRXFE_RESET */
.pin_ec_trxfe_reset = { &ec_io, OC_EC_RFFE_RESET },
.pin_ec_trxfe_reset = { &ec_io, OC_EC_RFFE_RESET },
/* FX3_RESET */
.pin_fx3_reset = { &sdr_fx3_io, 0 },
.pin_fx3_reset = { &sdr_fx3_io, 0 },
};

28
firmware/ec/platform/oc-sdr/cfg/OC_CONNECT_SYNC.c
View File

@@ -18,17 +18,17 @@ SCHEMA_IMPORT OcGpio_Port sync_io;
* SYSTEM CONFIG
*****************************************************************************/
/* OBC Subsystem Config.*/
//Irridium
// Irridium
Iridium_Cfg obc_irridium = {
.uart = OC_CONNECT1_UARTXR0,
/* IRIDIUM_RSTIOEXP */
.pin_enable = { &sync_io, 2, OCGPIO_CFG_OUT_STD },
.pin_enable = { &sync_io, 2, OCGPIO_CFG_OUT_STD },
/* R_NW_AVAIL */
.pin_nw_avail = { &sync_io, 3, OCGPIO_CFG_IN_PU },
.pin_nw_avail = { &sync_io, 3, OCGPIO_CFG_IN_PU },
};
/* Sync Subsystem Config.*/
//Temperature sensor.
// Temperature sensor.
I2C_Dev sync_gps_ts = {
.bus = OC_CONNECT1_I2C7,
.slave_addr = SYNC_TEMP_SENSOR_ADDR,
@@ -44,7 +44,7 @@ S_OCGPIO_Cfg debug_sync_ioexpanderx71 = {
.port = &sync_io,
};
//Sync Factory config
// Sync Factory config
const ADT7481_Config fact_sync_ts_cfg = {
.lowlimit = -20,
.highlimit = 80,
@@ -53,25 +53,25 @@ const ADT7481_Config fact_sync_ts_cfg = {
Sync_gpioCfg sync_gpiocfg = (Sync_gpioCfg){
/* SPDT_CNTRL_LVL */
.pin_spdt_cntrl_lvl = { &sync_io, 0, OCGPIO_CFG_OUT_OD_NOPULL },
.pin_spdt_cntrl_lvl = { &sync_io, 0, OCGPIO_CFG_OUT_OD_NOPULL },
/* WARMUP_SURVEY_INIT_SEL */
.pin_warmup_survey_init_sel = { &sync_io, 1, OCGPIO_CFG_OUT_OD_NOPULL },
.pin_warmup_survey_init_sel = { &sync_io, 1, OCGPIO_CFG_OUT_OD_NOPULL },
/* R_PHASE_LOCK_IOEXP */
.pin_r_phase_lock_ioexp = { &sync_io, 4, OCGPIO_CFG_IN_PU },
.pin_r_phase_lock_ioexp = { &sync_io, 4, OCGPIO_CFG_IN_PU },
/* R_LOCK_OK_IOEXP */
.pin_r_lock_ok_ioexp = { &sync_io, 5, OCGPIO_CFG_IN_PU },
.pin_r_lock_ok_ioexp = { &sync_io, 5, OCGPIO_CFG_IN_PU },
/* R_ALARM_IOEXP */
.pin_r_alarm_ioexp = { &sync_io, 6, OCGPIO_CFG_IN_PU },
.pin_r_alarm_ioexp = { &sync_io, 6, OCGPIO_CFG_IN_PU },
/* 12V_REG_ENB */
.pin_12v_reg_enb = { &sync_io, 7, OCGPIO_CFG_OUT_STD },
.pin_12v_reg_enb = { &sync_io, 7, OCGPIO_CFG_OUT_STD },
/* TEMP_ALERT */
.pin_temp_alert = { &sync_io, 8, OCGPIO_CFG_IN_PU },
.pin_temp_alert = { &sync_io, 8, OCGPIO_CFG_IN_PU },
/* SPDT_CNTRL_LTE_CPU_GPS_LVL */
.pin_spdt_cntrl_lte_cpu_gps_lvl = { &sync_io, 9, OCGPIO_CFG_OUT_OD_NOPULL },
/* INIT_SURVEY_SEL */
.pin_init_survey_sel = { &sync_io, 10, OCGPIO_CFG_OUT_OD_NOPULL },
.pin_init_survey_sel = { &sync_io, 10, OCGPIO_CFG_OUT_OD_NOPULL },
/* EC_SYNC_RESET */
.pin_ec_sync_reset = { &ec_io, OC_EC_SYNC_RESET },
.pin_ec_sync_reset = { &ec_io, OC_EC_SYNC_RESET },
};
Obc_gpioCfg sync_obc_gpiocfg = {

1760
firmware/ec/platform/oc-sdr/schema/schema.c
View File

File diff suppressed because it is too large Load Diff

70
firmware/ec/src/Board.h
View File

@@ -44,47 +44,47 @@ extern "C" {
#include "common/inc/global/OC_CONNECT1.h"
#define Board_initEMAC OC_CONNECT1_initEMAC
#define Board_initGeneral OC_CONNECT1_initGeneral
#define Board_initGPIO OC_CONNECT1_initGPIO
#define Board_initI2C OC_CONNECT1_initI2C
#define Board_initSPI OC_CONNECT1_initSPI
#define Board_initUART OC_CONNECT1_initUART
#define Board_initUSB OC_CONNECT1_initUSB
#define Board_initWatchdog OC_CONNECT1_initWatchdog
#define Board_initEMAC OC_CONNECT1_initEMAC
#define Board_initGeneral OC_CONNECT1_initGeneral
#define Board_initGPIO OC_CONNECT1_initGPIO
#define Board_initI2C OC_CONNECT1_initI2C
#define Board_initSPI OC_CONNECT1_initSPI
#define Board_initUART OC_CONNECT1_initUART
#define Board_initUSB OC_CONNECT1_initUSB
#define Board_initWatchdog OC_CONNECT1_initWatchdog
#define Board_IOEXP_ALERT OC_EC_GBC_IOEXP71_ALERT
#define Board_ECINA_ALERT OC_EC_GBC_INA_ALERT
#define Board_APINA_ALERT OC_EC_GBC_AP_INA_ALERT
#define Board_IOEXP_ALERT OC_EC_GBC_IOEXP71_ALERT
#define Board_ECINA_ALERT OC_EC_GBC_INA_ALERT
#define Board_APINA_ALERT OC_EC_GBC_AP_INA_ALERT
#define Board_SDRFPGA_TEMPINA_ALERT OC_EC_SDR_FPGA_TEMP_INA_ALERT
#define Board_SDR_INA_ALERT OC_EC_SDR_INA_ALERT
#define Board_RFFE_TEMP_INA_ALERT OC_EC_RFFE_TEMP_INA_ALERT
#define Board_SYNC_IOEXP_ALERT OC_EC_SYNC_IOEXP_ALERT
#define Board_LeadAcidAlert OC_EC_PWR_LACID_ALERT
#define Board_LithiumIonAlert OC_EC_PWR_LION_ALERT
#define Board_PSEALERT OC_EC_GBC_PSE_ALERT
#define Board_PD_PWRGDAlert OC_EC_PD_PWRGD_ALERT
#define Board_SOC_UART3_TX OC_EC_SOC_UART3_TX
#define Board_SDR_INA_ALERT OC_EC_SDR_INA_ALERT
#define Board_RFFE_TEMP_INA_ALERT OC_EC_RFFE_TEMP_INA_ALERT
#define Board_SYNC_IOEXP_ALERT OC_EC_SYNC_IOEXP_ALERT
#define Board_LeadAcidAlert OC_EC_PWR_LACID_ALERT
#define Board_LithiumIonAlert OC_EC_PWR_LION_ALERT
#define Board_PSEALERT OC_EC_GBC_PSE_ALERT
#define Board_PD_PWRGDAlert OC_EC_PD_PWRGD_ALERT
#define Board_SOC_UART3_TX OC_EC_SOC_UART3_TX
#define Board_I2C0 OC_CONNECT1_I2C0
#define Board_I2C1 OC_CONNECT1_I2C1
#define Board_I2C2 OC_CONNECT1_I2C2
#define Board_I2C3 OC_CONNECT1_I2C3
#define Board_I2C4 OC_CONNECT1_I2C4
#define Board_I2C6 OC_CONNECT1_I2C6
#define Board_I2C7 OC_CONNECT1_I2C7
#define Board_I2C8 OC_CONNECT1_I2C8
#define Board_I2CCOUNT OC_CONNECT1_I2CCOUNT
#define Board_I2C0 OC_CONNECT1_I2C0
#define Board_I2C1 OC_CONNECT1_I2C1
#define Board_I2C2 OC_CONNECT1_I2C2
#define Board_I2C3 OC_CONNECT1_I2C3
#define Board_I2C4 OC_CONNECT1_I2C4
#define Board_I2C6 OC_CONNECT1_I2C6
#define Board_I2C7 OC_CONNECT1_I2C7
#define Board_I2C8 OC_CONNECT1_I2C8
#define Board_I2CCOUNT OC_CONNECT1_I2CCOUNT
#define Board_USBHOST OC_CONNECT1_USBHOST
#define Board_USBDEVICE OC_CONNECT1_USBDEVICE
#define Board_USBHOST OC_CONNECT1_USBHOST
#define Board_USBDEVICE OC_CONNECT1_USBDEVICE
// TODO: maybe rename to "UART_GSM" and stuff to be more abstracted from HW
#define Board_UART0 OC_CONNECT1_UART0
#define Board_UART3 OC_CONNECT1_UART3
#define Board_UART4 OC_CONNECT1_UART4
#define Board_UARTXR0 OC_CONNECT1_UARTXR0
#define Board_WATCHDOG0 OC_CONNECT1_WATCHDOG0
#define Board_UART0 OC_CONNECT1_UART0
#define Board_UART3 OC_CONNECT1_UART3
#define Board_UART4 OC_CONNECT1_UART4
#define Board_UARTXR0 OC_CONNECT1_UARTXR0
#define Board_WATCHDOG0 OC_CONNECT1_WATCHDOG0
#ifdef __cplusplus
}

95
firmware/ec/src/bigbrother.c
View File

@@ -73,7 +73,8 @@ extern void usb_tx_createtask(void);
extern void uartdma_rx_createtask(void);
extern void uartdma_tx_createtask(void);
extern void ebmp_create_task(void);
extern void watchdog_create_task(void);;
extern void watchdog_create_task(void);
;
/*****************************************************************************
** FUNCTION NAME : bigbrother_process_tx_msg
@@ -90,7 +91,7 @@ static ReturnStatus bigbrother_process_tx_msg(uint8_t *pMsg)
ReturnStatus status = RETURN_OK;
LOGGER_DEBUG("BIGBROTHER:INFO:: Processing Big Brother TX Message.\n");
if (pMsg != NULL) {
Util_enqueueMsg(gossiperTxMsgQueue, semGossiperMsg, (uint8_t*) pMsg);
Util_enqueueMsg(gossiperTxMsgQueue, semGossiperMsg, (uint8_t *)pMsg);
} else {
LOGGER_ERROR("BIGBROTHER::ERROR::No Valid Pointer.\n");
}
@@ -131,10 +132,10 @@ static ReturnStatus bigbrother_process_rx_msg(uint8_t *pMsg)
{
ReturnStatus status = RETURN_OK;
LOGGER_DEBUG("BIGBROTHER:INFO:: Processing Big Brother RX Message.\n");
OCMPMessageFrame * pOCMPMessageFrame = (OCMPMessageFrame *) pMsg;
OCMPMessageFrame *pOCMPMessageFrame = (OCMPMessageFrame *)pMsg;
if (pOCMPMessageFrame != NULL) {
LOGGER_DEBUG("BIGBROTHER:INFO:: RX Msg recieved with Length: 0x%x,"
"Interface: 0x%x, Seq.No: 0x%x, TimeStamp: 0x%x.\n",
"Interface: 0x%x, Seq.No: 0x%x, TimeStamp: 0x%x.\n",
pOCMPMessageFrame->header.ocmpFrameLen,
pOCMPMessageFrame->header.ocmpInterface,
pOCMPMessageFrame->header.ocmpSeqNumber,
@@ -186,22 +187,23 @@ extern OcGpio_Port gbc_io_0;
/* These pins aren't properly referenced in a subsystem yet, so we'll define
* them here for now */
//OcGpio_Pin pin_r_irq_intrpt = { &gbc_io_0, 0, OCGPIO_CFG_IN_PU };
//OcGpio_Pin pin_inven_eeprom_wp = { &gbc_io_0, 1, OCGPIO_CFG_OUT_OD_NOPULL };
//OcGpio_Pin pin_s_id_eeprom_wp = { &gbc_io_0, 2, OCGPIO_CFG_OUT_OD_NOPULL };
OcGpio_Pin pin_uart_sel = { &gbc_io_0, 3, OCGPIO_CFG_OUT_OD_NOPULL };
//OcGpio_Pin pin_tempsen_evt1 = { &gbc_io_0, 4 };
//OcGpio_Pin pin_tempsen_evt2 = { &gbc_io_0, 5 };
//OcGpio_Pin pin_tempsen_evt3 = { &gbc_io_0, 6 };
//OcGpio_Pin pin_tempsen_evt4 = { &gbc_io_0, 7 };
//OcGpio_Pin pin_tempsen_evt5 = { &gbc_io_0, 8 };
//OcGpio_Pin pin_buzzer_on = { &gbc_io_0, 10, OCGPIO_CFG_OUT_OD_NOPULL };
//OcGpio_Pin pin_int_bat_prsnt = { &gbc_io_0, 11 };
//OcGpio_Pin pin_ext_bat_prsnt = { &gbc_io_0, 12 };
OcGpio_Pin pin_ec_syncconn_gpio1 = { &gbc_io_0, 13, OCGPIO_CFG_OUT_OD_NOPULL };
OcGpio_Pin pin_eth_sw_ec_intn = { &gbc_io_0, 14 };
// OcGpio_Pin pin_r_irq_intrpt = { &gbc_io_0, 0, OCGPIO_CFG_IN_PU };
// OcGpio_Pin pin_inven_eeprom_wp = { &gbc_io_0, 1,
// OCGPIO_CFG_OUT_OD_NOPULL }; OcGpio_Pin pin_s_id_eeprom_wp = {
// &gbc_io_0, 2, OCGPIO_CFG_OUT_OD_NOPULL };
OcGpio_Pin pin_uart_sel = { &gbc_io_0, 3, OCGPIO_CFG_OUT_OD_NOPULL };
// OcGpio_Pin pin_tempsen_evt1 = { &gbc_io_0, 4 };
// OcGpio_Pin pin_tempsen_evt2 = { &gbc_io_0, 5 };
// OcGpio_Pin pin_tempsen_evt3 = { &gbc_io_0, 6 };
// OcGpio_Pin pin_tempsen_evt4 = { &gbc_io_0, 7 };
// OcGpio_Pin pin_tempsen_evt5 = { &gbc_io_0, 8 };
// OcGpio_Pin pin_buzzer_on = { &gbc_io_0, 10,
// OCGPIO_CFG_OUT_OD_NOPULL }; OcGpio_Pin pin_int_bat_prsnt = {
// &gbc_io_0, 11 }; OcGpio_Pin pin_ext_bat_prsnt = { &gbc_io_0, 12 };
OcGpio_Pin pin_ec_syncconn_gpio1 = { &gbc_io_0, 13, OCGPIO_CFG_OUT_OD_NOPULL };
OcGpio_Pin pin_eth_sw_ec_intn = { &gbc_io_0, 14 };
OcGpio_Pin pin_v5_a_pgood = { &gbc_io_1, 3, OCGPIO_CFG_IN_PU };
OcGpio_Pin pin_v5_a_pgood = { &gbc_io_1, 3, OCGPIO_CFG_IN_PU };
extern OcGpio_Port sync_io;
extern OcGpio_Port sdr_fx3_io;
@@ -233,7 +235,7 @@ ReturnStatus bigbrother_ioexp_init(void)
* IO13 - NA
* IO14 - NA
* IO15 - NA
*/
*/
/* TODO: we need a better spot to init. our IO expanders, but this works
* for now
@@ -271,18 +273,18 @@ ReturnStatus bigbrother_ioexp_init(void)
*/
OcGpio_init(&gbc_io_0);
//OcGpio_configure(&pin_r_irq_intrpt, OCGPIO_CFG_INPUT);
//OcGpio_configure(&pin_inven_eeprom_wp, OCGPIO_CFG_OUTPUT);
//OcGpio_configure(&pin_s_id_eeprom_wp, OCGPIO_CFG_OUTPUT);
// OcGpio_configure(&pin_r_irq_intrpt, OCGPIO_CFG_INPUT);
// OcGpio_configure(&pin_inven_eeprom_wp, OCGPIO_CFG_OUTPUT);
// OcGpio_configure(&pin_s_id_eeprom_wp, OCGPIO_CFG_OUTPUT);
OcGpio_configure(&pin_uart_sel, OCGPIO_CFG_OUTPUT);
//OcGpio_configure(&pin_tempsen_evt1, OCGPIO_CFG_INPUT);
//OcGpio_configure(&pin_tempsen_evt2, OCGPIO_CFG_INPUT);
//OcGpio_configure(&pin_tempsen_evt3, OCGPIO_CFG_INPUT);
//OcGpio_configure(&pin_tempsen_evt4, OCGPIO_CFG_INPUT);
//OcGpio_configure(&pin_tempsen_evt5, OCGPIO_CFG_INPUT);
//OcGpio_configure(&pin_buzzer_on, OCGPIO_CFG_OUTPUT);
//OcGpio_configure(&pin_int_bat_prsnt, OCGPIO_CFG_INPUT);
//OcGpio_configure(&pin_ext_bat_prsnt, OCGPIO_CFG_INPUT);
// OcGpio_configure(&pin_tempsen_evt1, OCGPIO_CFG_INPUT);
// OcGpio_configure(&pin_tempsen_evt2, OCGPIO_CFG_INPUT);
// OcGpio_configure(&pin_tempsen_evt3, OCGPIO_CFG_INPUT);
// OcGpio_configure(&pin_tempsen_evt4, OCGPIO_CFG_INPUT);
// OcGpio_configure(&pin_tempsen_evt5, OCGPIO_CFG_INPUT);
// OcGpio_configure(&pin_buzzer_on, OCGPIO_CFG_OUTPUT);
// OcGpio_configure(&pin_int_bat_prsnt, OCGPIO_CFG_INPUT);
// OcGpio_configure(&pin_ext_bat_prsnt, OCGPIO_CFG_INPUT);
OcGpio_configure(&pin_ec_syncconn_gpio1, OCGPIO_CFG_OUTPUT);
OcGpio_configure(&pin_eth_sw_ec_intn, OCGPIO_CFG_INPUT);
@@ -306,9 +308,9 @@ static void bigborther_spwan_task(void)
/* Check the list for possible devices connected. */
/* Launches other tasks */
usb_rx_createtask(); // P - 05
usb_tx_createtask(); // P - 04
gossiper_createtask(); // P - 06
usb_rx_createtask(); // P - 05
usb_tx_createtask(); // P - 04
gossiper_createtask(); // P - 06
ebmp_create_task();
watchdog_create_task();
@@ -332,17 +334,20 @@ static void bigbrother_init(void)
/*Creating Semaphore for RX Message Queue*/
semBigBrotherMsg = Semaphore_create(0, NULL, NULL);
if (semBigBrotherMsg == NULL) {
LOGGER_ERROR("BIGBROTHER:ERROR::BIGBROTHER RX Semaphore creation failed.\n");
LOGGER_ERROR(
"BIGBROTHER:ERROR::BIGBROTHER RX Semaphore creation failed.\n");
}
/*Creating RX Message Queue*/
bigBrotherRxMsgQueue = Util_constructQueue(&bigBrotherRxMsg);
LOGGER_DEBUG("BIGBROTHER:INFO::Constructing message Queue for 0x%x Big Brother RX Messages.\n",
bigBrotherRxMsgQueue);
LOGGER_DEBUG(
"BIGBROTHER:INFO::Constructing message Queue for 0x%x Big Brother RX Messages.\n",
bigBrotherRxMsgQueue);
/*Creating TX Message Queue*/
bigBrotherTxMsgQueue = Util_constructQueue(&bigBrotherTxMsg);
LOGGER_DEBUG("BIGBROTHER:INFO::Constructing message Queue for 0x%x Big Brother RX Messages.\n",
bigBrotherTxMsgQueue);
LOGGER_DEBUG(
"BIGBROTHER:INFO::Constructing message Queue for 0x%x Big Brother RX Messages.\n",
bigBrotherTxMsgQueue);
}
/*****************************************************************************
@@ -363,22 +368,22 @@ static void bigbrother_taskfxn(UArg a0, UArg a1)
bigbrother_ioexp_init();
hci_buzzer_beep(1);
//Create Tasks.
// Create Tasks.
bigborther_spwan_task();
//Perform POST
// Perform POST
bigborther_initiate_post();
while (true) {
if (Semaphore_pend(semBigBrotherMsg, BIOS_WAIT_FOREVER)) {
while (!Queue_empty(bigBrotherRxMsgQueue)) {
uint8_t *pWrite = (uint8_t *) Util_dequeueMsg(
bigBrotherRxMsgQueue);
uint8_t *pWrite =
(uint8_t *)Util_dequeueMsg(bigBrotherRxMsgQueue);
if (pWrite) {
bigbrother_process_rx_msg(pWrite);
}
}
while (!Queue_empty(bigBrotherTxMsgQueue)) {
uint8_t *pWrite = (uint8_t *) Util_dequeueMsg(
bigBrotherTxMsgQueue);
uint8_t *pWrite =
(uint8_t *)Util_dequeueMsg(bigBrotherTxMsgQueue);
if (pWrite) {
bigbrother_process_tx_msg(pWrite);
}

70
firmware/ec/src/comm/gossiper.c
View File

@@ -111,18 +111,21 @@ static void gossiper_init(void)
/*Creating Semaphore for RX Message Queue*/
semGossiperMsg = Semaphore_create(0, NULL, NULL);
if (semGossiperMsg == NULL) {
LOGGER_ERROR("GOSSIPER:ERROR::GOSSIPER RX Semaphore creation failed.\n");
LOGGER_ERROR(
"GOSSIPER:ERROR::GOSSIPER RX Semaphore creation failed.\n");
}
/*Creating RX Message Queue*/
gossiperRxMsgQueue = Util_constructQueue(&gossiperRxMsg);
LOGGER_DEBUG("GOSSIPER:INFO::Constructing message Queue 0x%x for RX Gossiper Messages.\n",
gossiperRxMsgQueue);
LOGGER_DEBUG(
"GOSSIPER:INFO::Constructing message Queue 0x%x for RX Gossiper Messages.\n",
gossiperRxMsgQueue);
/*Creating TX Message Queue*/
gossiperTxMsgQueue = Util_constructQueue(&gossiperTxMsg);
LOGGER_DEBUG("GOSSIPER:INFO::Constructing message Queue 0x%x for TX Gossiper Messages.\n",
gossiperTxMsgQueue);
LOGGER_DEBUG(
"GOSSIPER:INFO::Constructing message Queue 0x%x for TX Gossiper Messages.\n",
gossiperTxMsgQueue);
}
/*****************************************************************************
@@ -142,8 +145,8 @@ static void gossiper_taskfxn(UArg a0, UArg a1)
if (Semaphore_pend(semGossiperMsg, BIOS_WAIT_FOREVER)) {
/* Gossiper RX Messgaes */
while (!Queue_empty(gossiperRxMsgQueue)) {
uint8_t *pWrite = (uint8_t *) Util_dequeueMsg(
gossiperRxMsgQueue);
uint8_t *pWrite =
(uint8_t *)Util_dequeueMsg(gossiperRxMsgQueue);
if (pWrite) {
gossiper_process_rx_msg(pWrite);
} else {
@@ -153,8 +156,8 @@ static void gossiper_taskfxn(UArg a0, UArg a1)
/* Gossiper TX Messgaes */
while (!Queue_empty(gossiperTxMsgQueue)) {
uint8_t *pWrite = (uint8_t *) Util_dequeueMsg(
gossiperTxMsgQueue);
uint8_t *pWrite =
(uint8_t *)Util_dequeueMsg(gossiperTxMsgQueue);
if (pWrite) {
gossiper_process_tx_msg(pWrite);
} else {
@@ -180,15 +183,16 @@ static ReturnStatus gossiper_process_rx_msg(uint8_t *pMsg)
ReturnStatus status = RETURN_OK;
LOGGER_DEBUG("GOSSIPER:INFO:: Processing Gossiper RX Message.\n");
OCMPMessageFrame * pOCMPMessageFrame = (OCMPMessageFrame *) pMsg;
OCMPMessageFrame *pOCMPMessageFrame = (OCMPMessageFrame *)pMsg;
if (pOCMPMessageFrame != NULL) {
LOGGER_DEBUG("GOSSIPER:INFO:: RX Msg recieved with Length: 0x%x, Interface: 0x%x, Seq.No: 0x%x, TimeStamp: 0x%x.\n",
pOCMPMessageFrame->header.ocmpFrameLen,
pOCMPMessageFrame->header.ocmpInterface,
pOCMPMessageFrame->header.ocmpSeqNumber,
pOCMPMessageFrame->header.ocmpTimestamp);
LOGGER_DEBUG(
"GOSSIPER:INFO:: RX Msg recieved with Length: 0x%x, Interface: 0x%x, Seq.No: 0x%x, TimeStamp: 0x%x.\n",
pOCMPMessageFrame->header.ocmpFrameLen,
pOCMPMessageFrame->header.ocmpInterface,
pOCMPMessageFrame->header.ocmpSeqNumber,
pOCMPMessageFrame->header.ocmpTimestamp);
/*Update the Debug info required based on the debug jumper connected*/
//status = CheckDebugEnabled()
// status = CheckDebugEnabled()
if (pOCMPMessageFrame->message.msgtype == OCMP_MSG_TYPE_DEBUG) {
#if 0
if (!IN_DEBUGMODE()) {
@@ -199,7 +203,8 @@ static ReturnStatus gossiper_process_rx_msg(uint8_t *pMsg)
}
#endif
}
Util_enqueueMsg(bigBrotherRxMsgQueue, semBigBrotherMsg, (uint8_t*) pMsg);
Util_enqueueMsg(bigBrotherRxMsgQueue, semBigBrotherMsg,
(uint8_t *)pMsg);
} else {
LOGGER_ERROR("GOSSIPER:ERROR:: Not valid pointer.\n");
}
@@ -220,18 +225,18 @@ static ReturnStatus gossiper_process_tx_msg(uint8_t *pMsg)
{
ReturnStatus status = RETURN_OK;
LOGGER_DEBUG("GOSSIPER:INFO:: Processing Gossiper TX Message.\n");
OCMPMessageFrame * pOCMPMessageFrame = (OCMPMessageFrame *) pMsg;
OCMPMessageFrame *pOCMPMessageFrame = (OCMPMessageFrame *)pMsg;
if (pOCMPMessageFrame != NULL) {
if (pOCMPMessageFrame->header.ocmpInterface == OCMP_COMM_IFACE_UART) {
status = gossiper_uart_send_msg(pMsg);
} else if (pOCMPMessageFrame->header.ocmpInterface
== OCMP_COMM_IFACE_ETHERNET) {
} else if (pOCMPMessageFrame->header.ocmpInterface ==
OCMP_COMM_IFACE_ETHERNET) {
status = gossiper_ethernet_send_msg(pMsg);
} else if (pOCMPMessageFrame->header.ocmpInterface
== OCMP_COMM_IFACE_SBD) {
// Will be added later.
} else if (pOCMPMessageFrame->header.ocmpInterface
== OCMP_COMM_IFACE_USB) {
} else if (pOCMPMessageFrame->header.ocmpInterface ==
OCMP_COMM_IFACE_SBD) {
// Will be added later.
} else if (pOCMPMessageFrame->header.ocmpInterface ==
OCMP_COMM_IFACE_USB) {
status = gossiper_usb_send_msg(pMsg);
}
} else {
@@ -253,9 +258,10 @@ static ReturnStatus gossiper_process_tx_msg(uint8_t *pMsg)
static ReturnStatus gossiper_ethernet_send_msg(uint8_t *pMsg)
{
ReturnStatus status = RETURN_OK;
LOGGER_DEBUG("GOSSIPER:INFO:: Forwarding TX message to the ETH Interface.\n");
LOGGER_DEBUG(
"GOSSIPER:INFO:: Forwarding TX message to the ETH Interface.\n");
if (pMsg != NULL) {
Util_enqueueMsg(ethTxMsgQueue, ethTxsem, (uint8_t*) pMsg);
Util_enqueueMsg(ethTxMsgQueue, ethTxsem, (uint8_t *)pMsg);
} else {
LOGGER_ERROR("GOSSIPER::ERROR::No Valid Pointer.\n");
}
@@ -275,9 +281,10 @@ static ReturnStatus gossiper_ethernet_send_msg(uint8_t *pMsg)
static ReturnStatus gossiper_uart_send_msg(uint8_t *pMsg)
{
ReturnStatus status = RETURN_OK;
LOGGER_DEBUG("GOSSIPER:INFO:: Forwarding TX message to the UART Interface.\n");
LOGGER_DEBUG(
"GOSSIPER:INFO:: Forwarding TX message to the UART Interface.\n");
if (pMsg != NULL) {
Util_enqueueMsg(uartTxMsgQueue, semUARTTX, (uint8_t*) pMsg);
Util_enqueueMsg(uartTxMsgQueue, semUARTTX, (uint8_t *)pMsg);
} else {
LOGGER_ERROR("GOSSIPER::ERROR::No Valid Pointer.\n");
}
@@ -297,9 +304,10 @@ static ReturnStatus gossiper_uart_send_msg(uint8_t *pMsg)
static ReturnStatus gossiper_usb_send_msg(uint8_t *pMsg)
{
ReturnStatus status = RETURN_OK;
LOGGER_DEBUG("GOSSIPER:INFO:: Forwarding TX message to the USB Interface.\n");
LOGGER_DEBUG(
"GOSSIPER:INFO:: Forwarding TX message to the USB Interface.\n");
if (pMsg != NULL) {
Util_enqueueMsg(usbTxMsgQueue, semUSBTX, (uint8_t*) pMsg);
Util_enqueueMsg(usbTxMsgQueue, semUSBTX, (uint8_t *)pMsg);
} else {
LOGGER_ERROR("GOSSIPER::ERROR::No Valid Pointer.\n");
}

8
firmware/ec/src/comm/gossiper.h
View File

@@ -18,11 +18,11 @@
/*****************************************************************************
* MACRO DEFINITIONS
*****************************************************************************/
#define GOSSIPER_TASK_PRIORITY 6
#define GOSSIPER_TASK_STACK_SIZE 2048
#define GOSSIPER_TASK_PRIORITY 6
#define GOSSIPER_TASK_STACK_SIZE 2048
#define SET_DEBEUG_MODE(debugMode) ((debugMode | 0x00))
#define UNSET_DEBUG_MODE(debugMode) ((debugMode & 0x0f))
#define SET_DEBEUG_MODE(debugMode) ((debugMode | 0x00))
#define UNSET_DEBUG_MODE(debugMode) ((debugMode & 0x0f))
/*****************************************************************************
* HANDLE DEFINITIONS

592
firmware/ec/src/devices/adt7481.c
View File

File diff suppressed because it is too large Load Diff

172
firmware/ec/src/devices/at45db.c
View File

@@ -1,42 +1,43 @@
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*
* This file is used as Device layer for AT45DB641E. Mainly it contains Data read,
* Data write, Page erase, Status check functions, these functions are called by
* littlefs filesystyem in order to perform read/write operation for data using SPI
* interface. Also while post execution device and manufacturing id's of AT45DB641E
* will be verified by probe function.
*/
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree. An additional grant
* of patent rights can be found in the PATENTS file in the same directory.
*
* This file is used as Device layer for AT45DB641E. Mainly it contains Data
* read, Data write, Page erase, Status check functions, these functions are
* called by littlefs filesystyem in order to perform read/write operation for
* data using SPI interface. Also while post execution device and manufacturing
* id's of AT45DB641E will be verified by probe function.
*/
#include "inc/devices/at45db.h"
#include "inc/common/spibus.h"
#include "inc/common/global_header.h"
#include "inc/global/OC_CONNECT1.h"
#define AT45DB_DATA_WR_OPCODE_WR_COUNT 4
#define AT45DB_DATA_RD_OPCODE_WR_COUNT 8
#define AT45DB_DEVICE_ID 0x0028
#define AT45DB_DEVID_RD_BYTES 2
#define AT45DB_DEVID_RD_OPCODE 0x9F
#define AT45DB_DEVID_OPCODE_WR_COUNT 1
#define AT45DB_ERASE_OPCODE_WR_COUNT 4
#define AT45DB_MANFACTURE_ID 0x1F
#define AT45DB_PAGE_ERASE_OPCODE 0x81
#define AT45DB_PAGE_RD_OPCODE 0xD2
#define AT45DB_PAGE_WR_OPCODE 0x86
#define AT45DB_READY 0x80 /* AT45DB Ready Value */
#define AT45DB_SRAM_BUFF2_WR_OPCODE 0x87
#define AT45DB_STATUS_OPCODE 0xD7
#define AT45DB_STATUS_OPCODE_WR_COUNT 1
#define AT45DB_STATUS_RD_BYTES 1
#define AT45DB_DATA_WR_OPCODE_WR_COUNT 4
#define AT45DB_DATA_RD_OPCODE_WR_COUNT 8
#define AT45DB_DEVICE_ID 0x0028
#define AT45DB_DEVID_RD_BYTES 2
#define AT45DB_DEVID_RD_OPCODE 0x9F
#define AT45DB_DEVID_OPCODE_WR_COUNT 1
#define AT45DB_ERASE_OPCODE_WR_COUNT 4
#define AT45DB_MANFACTURE_ID 0x1F
#define AT45DB_PAGE_ERASE_OPCODE 0x81
#define AT45DB_PAGE_RD_OPCODE 0xD2
#define AT45DB_PAGE_WR_OPCODE 0x86
#define AT45DB_READY 0x80 /* AT45DB Ready Value */
#define AT45DB_SRAM_BUFF2_WR_OPCODE 0x87
#define AT45DB_STATUS_OPCODE 0xD7
#define AT45DB_STATUS_OPCODE_WR_COUNT 1
#define AT45DB_STATUS_RD_BYTES 1
#define waitForReady(dev) \
while (!(AT45DB_READY & at45db_readStatusRegister(dev)));
#define waitForReady(dev) \
while (!(AT45DB_READY & at45db_readStatusRegister(dev))) \
;
/*****************************************************************************
** FUNCTION NAME : AT45DB_read_reg
@@ -50,27 +51,21 @@
**
*****************************************************************************/
static ReturnStatus AT45DB_read_reg(AT45DB_Dev *dev,
void *cmdbuffer, /* cmd or opcode buffer */
uint8_t *regValue,
uint32_t pageOffset,
uint32_t NumOfbytes,
uint8_t writeCount)
void *cmdbuffer, /* cmd or opcode buffer */
uint8_t *regValue, uint32_t pageOffset,
uint32_t NumOfbytes, uint8_t writeCount)
{
ReturnStatus status = RETURN_NOTOK;
SPI_Handle at45dbHandle = spi_get_handle(dev->cfg.dev.bus);
if (!at45dbHandle) {
LOGGER_ERROR("AT45DBFLASHMEMORY:ERROR:: Failed to get SPI Bus for at45db flash memory "
"0x%x on bus 0x%x.\n", dev->cfg.dev.chip_select,
dev->cfg.dev.bus);
LOGGER_ERROR(
"AT45DBFLASHMEMORY:ERROR:: Failed to get SPI Bus for at45db flash memory "
"0x%x on bus 0x%x.\n",
dev->cfg.dev.chip_select, dev->cfg.dev.bus);
} else {
status = spi_reg_read(at45dbHandle,
dev->cfg.dev.chip_select,
cmdbuffer,
regValue,
NumOfbytes,
pageOffset,
writeCount);
status = spi_reg_read(at45dbHandle, dev->cfg.dev.chip_select, cmdbuffer,
regValue, NumOfbytes, pageOffset, writeCount);
}
return status;
}
@@ -88,25 +83,20 @@ static ReturnStatus AT45DB_read_reg(AT45DB_Dev *dev,
*****************************************************************************/
static ReturnStatus AT45DB_write_reg(AT45DB_Dev *dev,
void *cmdbuffer, /* cmd or opcode buffer */
uint8_t *regValue,
uint32_t pageOffset,
uint32_t NumOfbytes,
uint8_t writeCount)
uint8_t *regValue, uint32_t pageOffset,
uint32_t NumOfbytes, uint8_t writeCount)
{
ReturnStatus status = RETURN_NOTOK;
SPI_Handle at45dbHandle = spi_get_handle(dev->cfg.dev.bus);
if (!at45dbHandle) {
LOGGER_ERROR("AT45DBFLASHMEMORY:ERROR:: Failed to get SPI Bus for at45db flash memory "
"0x%x on bus 0x%x.\n", dev->cfg.dev.chip_select,
dev->cfg.dev.bus);
LOGGER_ERROR(
"AT45DBFLASHMEMORY:ERROR:: Failed to get SPI Bus for at45db flash memory "
"0x%x on bus 0x%x.\n",
dev->cfg.dev.chip_select, dev->cfg.dev.bus);
} else {
status = spi_reg_write(at45dbHandle,
dev->cfg.dev.chip_select,
cmdbuffer,
regValue,
NumOfbytes,
pageOffset,
writeCount);
status =
spi_reg_write(at45dbHandle, dev->cfg.dev.chip_select, cmdbuffer,
regValue, NumOfbytes, pageOffset, writeCount);
}
return status;
}
@@ -125,10 +115,13 @@ static ReturnStatus AT45DB_write_reg(AT45DB_Dev *dev,
*****************************************************************************/
uint8_t at45db_readStatusRegister(AT45DB_Dev *dev)
{
uint8_t txBuffer = AT45DB_STATUS_OPCODE; /* opcode for ready status of AT45DB */;
uint8_t txBuffer =
AT45DB_STATUS_OPCODE; /* opcode for ready status of AT45DB */
;
uint8_t status;
AT45DB_read_reg(dev, &txBuffer, &status, NULL, AT45DB_STATUS_RD_BYTES, AT45DB_STATUS_OPCODE_WR_COUNT);
AT45DB_read_reg(dev, &txBuffer, &status, NULL, AT45DB_STATUS_RD_BYTES,
AT45DB_STATUS_OPCODE_WR_COUNT);
return (status);
}
@@ -150,12 +143,15 @@ ReturnStatus at45db_erasePage(AT45DB_Dev *dev, uint32_t page)
waitForReady(dev);
txBuffer[0] = AT45DB_PAGE_ERASE_OPCODE; /* opcode to erase main memory page */
txBuffer[1] = (uint8_t)(page >> 7); /* Page size is 15 bits 8 in tx1 and 7 in tx2 */
txBuffer[0] =
AT45DB_PAGE_ERASE_OPCODE; /* opcode to erase main memory page */
txBuffer[1] =
(uint8_t)(page >> 7); /* Page size is 15 bits 8 in tx1 and 7 in tx2 */
txBuffer[2] = (uint8_t)(page << 1);
txBuffer[3] = 0x00;
status = AT45DB_write_reg(dev, txBuffer, NULL, NULL, NULL, AT45DB_ERASE_OPCODE_WR_COUNT);
status = AT45DB_write_reg(dev, txBuffer, NULL, NULL, NULL,
AT45DB_ERASE_OPCODE_WR_COUNT);
return status;
}
@@ -172,19 +168,23 @@ ReturnStatus at45db_erasePage(AT45DB_Dev *dev, uint32_t page)
** RETURN TYPE : Success or failure
**
*****************************************************************************/
ReturnStatus at45db_data_read(AT45DB_Dev *dev, uint8_t *data, uint32_t data_size, uint32_t byte, uint32_t page)
ReturnStatus at45db_data_read(AT45DB_Dev *dev, uint8_t *data,
uint32_t data_size, uint32_t byte, uint32_t page)
{
ReturnStatus status = RETURN_NOTOK;
uint8_t txBuffer[8]; /* last 4 bytes are needed, but have don't care values */
uint8_t
txBuffer[8]; /* last 4 bytes are needed, but have don't care values */
waitForReady(dev);
txBuffer[0] = AT45DB_PAGE_RD_OPCODE; /* opcode to read main memory page */
txBuffer[1] = (uint8_t)(page >> 7); /* Page size is 15 bits 8 in tx1 and 7 in tx2 */
txBuffer[1] =
(uint8_t)(page >> 7); /* Page size is 15 bits 8 in tx1 and 7 in tx2 */
txBuffer[2] = (uint8_t)((page << 1));
txBuffer[3] = (uint8_t)(0xFF & byte);
status = AT45DB_read_reg(dev, &txBuffer, data, byte, data_size, AT45DB_DATA_RD_OPCODE_WR_COUNT);
status = AT45DB_read_reg(dev, &txBuffer, data, byte, data_size,
AT45DB_DATA_RD_OPCODE_WR_COUNT);
return status;
}
@@ -201,29 +201,36 @@ ReturnStatus at45db_data_read(AT45DB_Dev *dev, uint8_t *data, uint32_t data_size
** RETURN TYPE : Success or failure
**
*****************************************************************************/
ReturnStatus at45db_data_write(AT45DB_Dev *dev, uint8_t *data, uint32_t data_size, uint32_t byte, uint32_t page)
ReturnStatus at45db_data_write(AT45DB_Dev *dev, uint8_t *data,
uint32_t data_size, uint32_t byte, uint32_t page)
{
ReturnStatus status = RETURN_NOTOK;
uint8_t txBuffer[4];
waitForReady(dev);
txBuffer[0] = AT45DB_SRAM_BUFF2_WR_OPCODE; /* opcode to write data to AT45DB SRAM Buffer2 */
txBuffer[0] = AT45DB_SRAM_BUFF2_WR_OPCODE; /* opcode to write data to AT45DB
SRAM Buffer2 */
txBuffer[1] = 0x00;
txBuffer[2] = (uint8_t)(0x1 & (byte >> 8)); /* 9 bit buffer address */
txBuffer[3] = (uint8_t)(0xFF & byte);
status = AT45DB_write_reg(dev, &txBuffer, data, byte, data_size, AT45DB_DATA_WR_OPCODE_WR_COUNT);
status = AT45DB_write_reg(dev, &txBuffer, data, byte, data_size,
AT45DB_DATA_WR_OPCODE_WR_COUNT);
if(status == RETURN_OK) {
waitForReady(dev);
if (status == RETURN_OK) {
waitForReady(dev);
txBuffer[0] = AT45DB_PAGE_WR_OPCODE; /* opcode to Push the data from AT45DB SRAM Buffer2 to the page */
txBuffer[1] = (uint8_t)(page >> 7); /* Page size is 15 bits 8 in tx1 and 7 in tx2 */
txBuffer[2] = (uint8_t)(page << 1);
txBuffer[3] = 0x00;
txBuffer[0] =
AT45DB_PAGE_WR_OPCODE; /* opcode to Push the data from AT45DB SRAM
Buffer2 to the page */
txBuffer[1] = (uint8_t)(
page >> 7); /* Page size is 15 bits 8 in tx1 and 7 in tx2 */
txBuffer[2] = (uint8_t)(page << 1);
txBuffer[3] = 0x00;
status = AT45DB_write_reg(dev, &txBuffer, data, byte, data_size, AT45DB_DATA_WR_OPCODE_WR_COUNT);
status = AT45DB_write_reg(dev, &txBuffer, data, byte, data_size,
AT45DB_DATA_WR_OPCODE_WR_COUNT);
}
return status;
}
@@ -242,7 +249,8 @@ static ReturnStatus at45db_getDevID(AT45DB_Dev *dev, uint32_t *devID)
{
uint8_t txBuffer = AT45DB_DEVID_RD_OPCODE; /* opcode to get device id */
return AT45DB_read_reg(dev, &txBuffer, devID, NULL, AT45DB_DEVID_RD_BYTES, AT45DB_DEVID_OPCODE_WR_COUNT);
return AT45DB_read_reg(dev, &txBuffer, devID, NULL, AT45DB_DEVID_RD_BYTES,
AT45DB_DEVID_OPCODE_WR_COUNT);
}
/*****************************************************************************
@@ -275,9 +283,9 @@ ePostCode at45db_probe(AT45DB_Dev *dev, POSTData *postData)
if (manfId != AT45DB_MANFACTURE_ID) {
return POST_DEV_ID_MISMATCH;
}
}
post_update_POSTData(postData, dev->cfg.dev.bus, NULL,manfId, devId);
post_update_POSTData(postData, dev->cfg.dev.bus, NULL, manfId, devId);
return POST_DEV_FOUND;
}

150
firmware/ec/src/devices/eeprom.c
View File

@@ -18,11 +18,11 @@
#include <ti/drivers/I2C.h>
#ifndef UT_FRAMEWORK
#include <driverlib/emac.h> /* TODO: for htons - clean up this random include */
# include <driverlib/emac.h> /* TODO: for htons - clean up this random include */
#endif
#include <string.h>
#define WP_ASSERT 1
#define WP_ASSERT 1
#define WP_DEASSERT 0
extern Eeprom_Cfg eeprom_gbc_sid;
@@ -31,16 +31,12 @@ extern Eeprom_Cfg eeprom_sdr_inv;
extern Eeprom_Cfg eeprom_fe_inv;
static ReturnStatus i2c_eeprom_write(I2C_Handle i2cHandle,
uint8_t deviceAddress,
uint16_t regAddress,
const void *value,
size_t numofBytes);
uint8_t deviceAddress, uint16_t regAddress,
const void *value, size_t numofBytes);
static ReturnStatus i2c_eeprom_read(I2C_Handle i2cHandle,
uint16_t deviceAddress,
uint16_t regAddress,
void *value,
size_t numofbytes);
uint16_t deviceAddress, uint16_t regAddress,
void *value, size_t numofbytes);
/*****************************************************************************
** FUNCTION NAME : eeprom_init
@@ -52,11 +48,11 @@ static ReturnStatus i2c_eeprom_read(I2C_Handle i2cHandle,
** RETURN TYPE : Success or failure
**
*****************************************************************************/
bool eeprom_init(Eeprom_Cfg *cfg) {
bool eeprom_init(Eeprom_Cfg *cfg)
{
/* Configure our WP pin (if any) and set to be low (protected) by default */
if (cfg->pin_wp) {
OcGpio_configure(cfg->pin_wp,
OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_HIGH);
OcGpio_configure(cfg->pin_wp, OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_HIGH);
}
/* Test communication to the EEPROM */
@@ -79,16 +75,15 @@ bool eeprom_init(Eeprom_Cfg *cfg) {
** RETURN TYPE : Success or failure
**
*****************************************************************************/
ReturnStatus eeprom_read(const Eeprom_Cfg *cfg,
uint16_t address,
void *buffer,
ReturnStatus eeprom_read(const Eeprom_Cfg *cfg, uint16_t address, void *buffer,
size_t size)
{
ReturnStatus status = RETURN_OK;
I2C_Handle eepromHandle = i2c_get_handle(cfg->i2c_dev.bus);
if (!eepromHandle) {
LOGGER_ERROR("EEPROM:ERROR:: Failed to get I2C Bus for "
"EEPROM device 0x%x.\n", cfg->i2c_dev.slave_addr);
"EEPROM device 0x%x.\n",
cfg->i2c_dev.slave_addr);
} else {
/* TODO: if we're concerned about hogging the bus, we could always
* page reads, but this doesn't seem necessary right now
@@ -96,8 +91,8 @@ ReturnStatus eeprom_read(const Eeprom_Cfg *cfg,
/* TODO: check for out-of-bounds addresses (some EEPROM wrap around
* when reading after the end, so this could lead to confusion)
*/
status = i2c_eeprom_read(eepromHandle, cfg->i2c_dev.slave_addr,
address, buffer, size);
status = i2c_eeprom_read(eepromHandle, cfg->i2c_dev.slave_addr, address,
buffer, size);
}
return status;
}
@@ -113,16 +108,15 @@ ReturnStatus eeprom_read(const Eeprom_Cfg *cfg,
** RETURN TYPE : Success or failure
**
*****************************************************************************/
ReturnStatus eeprom_write(const Eeprom_Cfg *cfg,
uint16_t address,
const void *buffer,
size_t size)
ReturnStatus eeprom_write(const Eeprom_Cfg *cfg, uint16_t address,
const void *buffer, size_t size)
{
ReturnStatus status = RETURN_OK;
I2C_Handle eepromHandle = i2c_get_handle(cfg->i2c_dev.bus);
if (!eepromHandle) {
LOGGER_ERROR("EEPROM:ERROR:: Failed to get I2C Bus for "
"EEPROM device 0x%x.\n", cfg->i2c_dev.slave_addr);
"EEPROM device 0x%x.\n",
cfg->i2c_dev.slave_addr);
} else {
/* Respect EEPROM page size */
const size_t page_size = cfg->type.page_size;
@@ -152,10 +146,8 @@ ReturnStatus eeprom_write(const Eeprom_Cfg *cfg,
** RETURN TYPE : Success or failure
**
*****************************************************************************/
static ReturnStatus i2c_eeprom_write(I2C_Handle i2cHandle,
uint8_t slaveAddress,
uint16_t memAddress,
const void *value,
static ReturnStatus i2c_eeprom_write(I2C_Handle i2cHandle, uint8_t slaveAddress,
uint16_t memAddress, const void *value,
size_t numofBytes)
{
ReturnStatus status = RETURN_OK;
@@ -171,12 +163,14 @@ static ReturnStatus i2c_eeprom_write(I2C_Handle i2cHandle,
i2cTransaction.readBuf = NULL;
i2cTransaction.readCount = 0;
if (I2C_transfer(i2cHandle, &i2cTransaction)) {
LOGGER_DEBUG("EEPROM:INFO:: I2C write success for device: 0x%x reg Addr: 0x%x\n",
slaveAddress, memAddress);
LOGGER_DEBUG(
"EEPROM:INFO:: I2C write success for device: 0x%x reg Addr: 0x%x\n",
slaveAddress, memAddress);
status = RETURN_OK;
} else {
LOGGER_ERROR("EEPROM:ERROR:: I2C write failed for for device: 0x%x reg Addr: 0x%x\n",
slaveAddress, memAddress);
LOGGER_ERROR(
"EEPROM:ERROR:: I2C write failed for for device: 0x%x reg Addr: 0x%x\n",
slaveAddress, memAddress);
status = RETURN_NOTOK;
}
return status;
@@ -192,10 +186,8 @@ static ReturnStatus i2c_eeprom_write(I2C_Handle i2cHandle,
** RETURN TYPE : Success or failure
**
*****************************************************************************/
static ReturnStatus i2c_eeprom_read(I2C_Handle i2cHandle,
uint16_t slaveAddress,
uint16_t memAddress,
void *value,
static ReturnStatus i2c_eeprom_read(I2C_Handle i2cHandle, uint16_t slaveAddress,
uint16_t memAddress, void *value,
size_t numofbytes)
{
ReturnStatus status = RETURN_OK;
@@ -208,12 +200,14 @@ static ReturnStatus i2c_eeprom_read(I2C_Handle i2cHandle,
i2cTransaction.readBuf = value;
i2cTransaction.readCount = numofbytes;
if (I2C_transfer(i2cHandle, &i2cTransaction)) {
LOGGER_DEBUG("EEPROM:INFO:: I2C read success for device: 0x%x reg Addr: 0x%x\n",
slaveAddress, memAddress);
LOGGER_DEBUG(
"EEPROM:INFO:: I2C read success for device: 0x%x reg Addr: 0x%x\n",
slaveAddress, memAddress);
status = RETURN_OK;
} else {
LOGGER_ERROR("EEPROM:ERROR:: I2C write failed for for device: 0x%x reg Addr: 0x%x\n",
slaveAddress, memAddress);
LOGGER_ERROR(
"EEPROM:ERROR:: I2C write failed for for device: 0x%x reg Addr: 0x%x\n",
slaveAddress, memAddress);
status = RETURN_NOTOK;
}
return status;
@@ -262,7 +256,8 @@ ReturnStatus eeprom_enable_write(Eeprom_Cfg *cfg)
/*****************************************************************************
** FUNCTION NAME : eeprom_read_oc_info
**
** DESCRIPTION : Read the info about OC connect1 box from the EEPROM register.
** DESCRIPTION : Read the info about OC connect1 box from the EEPROM
*register.
**
** ARGUMENTS : EEPROM (Slave) address, Register address and
** pointer to value read.
@@ -270,13 +265,14 @@ ReturnStatus eeprom_enable_write(Eeprom_Cfg *cfg)
** RETURN TYPE : Success or failure
**
*****************************************************************************/
ReturnStatus eeprom_read_oc_info(uint8_t * oc_serial)
ReturnStatus eeprom_read_oc_info(uint8_t *oc_serial)
{
ReturnStatus status = RETURN_NOTOK;
status = eeprom_read(&eeprom_gbc_sid, OC_CONNECT1_SERIAL_INFO,
oc_serial, OC_CONNECT1_SERIAL_SIZE);
status = eeprom_read(&eeprom_gbc_sid, OC_CONNECT1_SERIAL_INFO, oc_serial,
OC_CONNECT1_SERIAL_SIZE);
if (status != RETURN_OK) {
LOGGER_ERROR("EEPROM:ERROR:: Failed to get I2C Bus for GBC serial ID EEPROM.\n");
LOGGER_ERROR(
"EEPROM:ERROR:: Failed to get I2C Bus for GBC serial ID EEPROM.\n");
} else {
LOGGER_ERROR("EEPROM:Info:: OC Connect1 %d.\n", *oc_serial);
}
@@ -286,7 +282,8 @@ ReturnStatus eeprom_read_oc_info(uint8_t * oc_serial)
/*****************************************************************************
** FUNCTION NAME : eeprom_read_board_info
**
** DESCRIPTION : Read the info about various board from the EEPROM register.
** DESCRIPTION : Read the info about various board from the EEPROM
*register.
**
** ARGUMENTS : EEPROM (Slave) address, Register address and
** pointer to value read.
@@ -294,39 +291,36 @@ ReturnStatus eeprom_read_oc_info(uint8_t * oc_serial)
** RETURN TYPE : Success or failure
**
*****************************************************************************/
ReturnStatus eeprom_read_board_info(const Eeprom_Cfg *cfg, uint8_t * rom_info)
ReturnStatus eeprom_read_board_info(const Eeprom_Cfg *cfg, uint8_t *rom_info)
{
ReturnStatus status = RETURN_NOTOK;
uint8_t info_size = 0x00;
uint16_t eepromOffset = 0x0000;
switch (cfg->ss) {
case OC_SS_SYS:
{
case OC_SS_SYS: {
info_size = OC_GBC_BOARD_INFO_SIZE;
eepromOffset = OC_GBC_BOARD_INFO;
break;
}
case OC_SS_SDR:
{
case OC_SS_SDR: {
info_size = OC_SDR_BOARD_INFO_SIZE;
eepromOffset = OC_SDR_BOARD_INFO;
break;
}
case OC_SS_RF:
{
case OC_SS_RF: {
info_size = OC_RFFE_BOARD_INFO_SIZE;
eepromOffset = OC_RFFE_BOARD_INFO;
break;
}
default:
{
default: {
return status;
}
}
status = eeprom_read(cfg, eepromOffset, rom_info, info_size);
if (status != RETURN_OK) {
LOGGER_ERROR("EEPROM:ERROR:: Failed to get I2C Bus for EEPROM device 0x%x.\n",
cfg->i2c_dev.slave_addr);
LOGGER_ERROR(
"EEPROM:ERROR:: Failed to get I2C Bus for EEPROM device 0x%x.\n",
cfg->i2c_dev.slave_addr);
} else {
LOGGER_ERROR("EEPROM:Info:: OC Connect1 %s.\n", rom_info);
}
@@ -346,37 +340,33 @@ ReturnStatus eeprom_read_board_info(const Eeprom_Cfg *cfg, uint8_t * rom_info)
**
*****************************************************************************/
ReturnStatus eeprom_read_device_info_record(const Eeprom_Cfg *cfg,
uint8_t recordNo,
char * device_info)
uint8_t recordNo, char *device_info)
{
ReturnStatus status = RETURN_NOTOK;
uint8_t info_size = OC_DEVICE_INFO_SIZE;
uint16_t eepromOffset = 0x0000;
switch (cfg->ss) {
case OC_SS_SYS:
{
case OC_SS_SYS: {
eepromOffset = OC_GBC_DEVICE_INFO + (recordNo * info_size);
break;
}
case OC_SS_SDR:
{
case OC_SS_SDR: {
eepromOffset = OC_SDR_DEVICE_INFO + (recordNo * info_size);
break;
}
case OC_SS_RF:
{
case OC_SS_RF: {
eepromOffset = OC_RFFE_DEVICE_INFO + (recordNo * info_size);
break;
}
default:
{
default: {
return status;
}
}
status = eeprom_read(cfg, eepromOffset, device_info, info_size);
if (status != RETURN_OK) {
LOGGER_ERROR("EEPROM:ERROR:: Failed to get I2C Bus for EEPROM device 0x%x.\n",
cfg->i2c_dev.slave_addr);
LOGGER_ERROR(
"EEPROM:ERROR:: Failed to get I2C Bus for EEPROM device 0x%x.\n",
cfg->i2c_dev.slave_addr);
} else {
LOGGER_ERROR("EEPROM:Info:: Record read for 0x%x.\n",
cfg->i2c_dev.slave_addr);
@@ -396,38 +386,34 @@ ReturnStatus eeprom_read_device_info_record(const Eeprom_Cfg *cfg,
** RETURN TYPE : Success or failure
**
*****************************************************************************/
ReturnStatus eeprom_write_device_info_record(Eeprom_Cfg *cfg,
uint8_t recordNo,
char * device_info)
ReturnStatus eeprom_write_device_info_record(Eeprom_Cfg *cfg, uint8_t recordNo,
char *device_info)
{
ReturnStatus status = RETURN_NOTOK;
uint8_t info_size = OC_DEVICE_INFO_SIZE;
uint16_t eepromOffset = 0x0000;
switch (cfg->ss) {
case OC_SS_SYS:
{
case OC_SS_SYS: {
eepromOffset = OC_GBC_DEVICE_INFO + (recordNo * info_size);
break;
}
case OC_SS_SDR:
{
case OC_SS_SDR: {
eepromOffset = OC_SDR_DEVICE_INFO + (recordNo * info_size);
break;
}
case OC_SS_RF:
{
case OC_SS_RF: {
eepromOffset = OC_RFFE_DEVICE_INFO + (recordNo * info_size);
break;
}
default:
{
default: {
return status;
}
}
status = eeprom_write(cfg, eepromOffset, device_info, info_size);
if (status != RETURN_OK) {
LOGGER_ERROR("EEPROM:ERROR:: Failed to get I2C Bus for EEPROM device 0x%x.\n",
cfg->i2c_dev.slave_addr);
LOGGER_ERROR(
"EEPROM:ERROR:: Failed to get I2C Bus for EEPROM device 0x%x.\n",
cfg->i2c_dev.slave_addr);
} else {
LOGGER_ERROR("EEPROM:Info:: Record written for 0x%x.\n",
cfg->i2c_dev.slave_addr);

444
firmware/ec/src/devices/eth_sw.c
View File

@@ -21,7 +21,7 @@
#include <ti/sysbios/knl/Task.h>
#include <xdc/runtime/Error.h>
#define CLEAR_BIT(x, y) (y = (~x) & y)
#define CLEAR_BIT(x, y) (y = (~x) & y)
#define SET_BIT(x, y) (y = x | y)
#define MACLOOPBACK 0
#define LINELOOPBACK 1
@@ -37,15 +37,16 @@ const char *destIp;
uint8_t numRepeat;
char convStr[IPSTRING_LENGTH];
char temp[IPSTRING_LENGTH];
char *tempBuf=temp;
char *tempBuf = temp;
void eth_sw_configure(Eth_cfg* ethCfg)
void eth_sw_configure(Eth_cfg *ethCfg)
{
uint8_t link_up;
uint16_t read_val = 0;
if (!s_eth_sw_linkup) {
OcGpio_configure(&ethCfg->eth_sw_cfg->pin_ec_ethsw_reset, OCGPIO_CFG_OUTPUT| OCGPIO_CFG_OUT_HIGH);
SysCtlDelay(16000000); //400ms delay
OcGpio_configure(&ethCfg->eth_sw_cfg->pin_ec_ethsw_reset,
OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_HIGH);
SysCtlDelay(16000000); // 400ms delay
}
read_val = mdiobb_read_by_paging(PHY_PORT_0, REG_PHY_SPEC_STATUS);
link_up = (RT_LINK & read_val) ? 1 : 0;
@@ -57,18 +58,18 @@ void eth_sw_configure(Eth_cfg* ethCfg)
}
}
ePostCode eth_sw_probe( POSTData *postData)
ePostCode eth_sw_probe(POSTData *postData)
{
ePostCode eth_sw_found = POST_DEV_MISSING;
uint16_t switch_pid = 0;
uint16_t devId = 0x00;
/*Switch idenifier*/
switch_pid = mdiobb_read(0x8, 3);
switch_pid = (switch_pid >>4);
switch_pid = mdiobb_read(0x8, 3);
switch_pid = (switch_pid >> 4);
if (switch_pid == ETH_SW_PRODUCT_ID) {
/* Phy Identifier */
devId = mdiobb_read_by_paging(0, REG_PHY_ID_1);
if ( devId == PHY_IDENTIFIER) {
if (devId == PHY_IDENTIFIER) {
eth_sw_found = POST_DEV_FOUND;
}
}
@@ -97,8 +98,9 @@ uint16_t get_interrupt_status(uint8_t port)
/*****************************************************************************
* Internal IRQ handler - reads in triggered interrupts and dispatches CBs
*****************************************************************************/
static void _ethernet_sw_isr(void *context) {
Eth_cfg *ethCfg= context;
static void _ethernet_sw_isr(void *context)
{
Eth_cfg *ethCfg = context;
uint8_t port = 0;
uint8_t value;
if (!ethCfg->eth_sw_cfg->eth_switch.obj.alert_cb) {
@@ -107,95 +109,91 @@ static void _ethernet_sw_isr(void *context) {
/* Confirm the interrupt*/
uint16_t read_val = mdiobb_read(GLOBAL_2, REG_INTERRUPT_MASK);
read_val = mdiobb_read(GLOBAL_2, REG_INTERRUPT_SOURCE);
LOGGER_DEBUG("ETHSW::INFO:: Ethernet switch Interrupt mask register shows 0x%x.\n",read_val);
LOGGER_DEBUG(
"ETHSW::INFO:: Ethernet switch Interrupt mask register shows 0x%x.\n",
read_val);
if (read_val & 0x1F) {
while (!((read_val >> port) & 1)) {
port++;
}
}
LOGGER_DEBUG("ETHSW::INFO:: Ethernet switch context report interrupt from 0x%x.\n",ethCfg->eth_sw_port);
LOGGER_DEBUG(
"ETHSW::INFO:: Ethernet switch context report interrupt from 0x%x.\n",
ethCfg->eth_sw_port);
uint16_t interrupt_status = 0;
uint16_t i = 0;
Eth_Sw_Events eth_Evt;
if (interrupt_status = get_interrupt_status(port)) {
for (i = 0; (1 << i) != 0x10000; i++) {
switch (interrupt_status & (1 << i)) {
case SPEED_INT_STATUS:
{
if (mdiobb_read_by_paging(port, REG_PHY_CONTROL) & AUTONEG_EN) {
value = (RES_SPEED & mdiobb_read_by_paging(port, REG_PHY_SPEC_STATUS)) ?
SPEED_100M : SPEED_10M;
case SPEED_INT_STATUS: {
if (mdiobb_read_by_paging(port, REG_PHY_CONTROL) &
AUTONEG_EN) {
value = (RES_SPEED & mdiobb_read_by_paging(
port, REG_PHY_SPEC_STATUS)) ?
SPEED_100M :
SPEED_10M;
} else {
value = (SPEED & mdiobb_read_by_paging(port, REG_PHY_CONTROL)) ?
SPEED_100M : SPEED_10M;
value = (SPEED &
mdiobb_read_by_paging(port, REG_PHY_CONTROL)) ?
SPEED_100M :
SPEED_10M;
}
eth_Evt = ETH_EVT_SPEED;
}
break;
case DUPLEX_INT_STATUS:
{
if (mdiobb_read_by_paging(port, REG_PHY_CONTROL) & AUTONEG_EN) {
value = (RES_DUPLEX & mdiobb_read_by_paging(port, REG_PHY_SPEC_STATUS)) ?
FULL_DUPLEX : HALF_DUPLEX;
} break;
case DUPLEX_INT_STATUS: {
if (mdiobb_read_by_paging(port, REG_PHY_CONTROL) &
AUTONEG_EN) {
value = (RES_DUPLEX & mdiobb_read_by_paging(
port, REG_PHY_SPEC_STATUS)) ?
FULL_DUPLEX :
HALF_DUPLEX;
} else {
value = (DUPLEX & mdiobb_read_by_paging(port, REG_PHY_CONTROL)) ?
FULL_DUPLEX : HALF_DUPLEX;
value = (DUPLEX &
mdiobb_read_by_paging(port, REG_PHY_CONTROL)) ?
FULL_DUPLEX :
HALF_DUPLEX;
}
eth_Evt = ETH_EVT_DUPLEX;
}
break;
case AUTONEG_COMPLETE_INT_STATUS:
{
} break;
case AUTONEG_COMPLETE_INT_STATUS: {
read_val = mdiobb_read_by_paging(port, REG_PHY_STATUS);
value = (AUTONEG_DONE & read_val) ? 1 : 0;
eth_Evt = ETH_EVT_AUTONEG;
}
break;
case LINK_CHANGE_INT_STATUS:
{
} break;
case LINK_CHANGE_INT_STATUS: {
read_val = mdiobb_read_by_paging(port, REG_PHY_SPEC_STATUS);
value = (RT_LINK & read_val) ? 1 : 0;
eth_Evt = ETH_EVT_LINK;
}
break;
case MDI_CROSSOVER_INT_STATUS:
{
} break;
case MDI_CROSSOVER_INT_STATUS: {
read_val = mdiobb_read_by_paging(port, REG_PHY_SPEC_STATUS);
value = (MDI_CROSSOVER_STATUS & read_val) ? 1 : 0;
eth_Evt = ETH_EVT_CROSSOVER;
}
break;
case ENERGY_DET_INT_STATUS:
{
} break;
case ENERGY_DET_INT_STATUS: {
read_val = mdiobb_read_by_paging(port, REG_PHY_SPEC_STATUS);
value = (SLEEP_MODE & read_val) ? 1 : 0;
eth_Evt = ETH_EVT_ENERGY;
}
break;
case POLARITY_INT_STATUS:
{
} break;
case POLARITY_INT_STATUS: {
read_val = mdiobb_read_by_paging(port, REG_PHY_SPEC_STATUS);
value = (POLARITY & read_val) ? 1 : 0;
eth_Evt = ETH_EVT_POLARITY;
break;
}
case JABBER_INT_STATUS:
{
case JABBER_INT_STATUS: {
read_val = mdiobb_read_by_paging(port, REG_PHY_SPEC_STATUS);
value = (JABBER_DET & read_val) ? 1 : 0;
eth_Evt = ETH_EVT_JABBER;
}
break;
default:
{
} break;
default: {
LOGGER_ERROR("ETHSW:Unknown event type\n");
return;
}
}
ethCfg->eth_sw_cfg->eth_switch.obj.alert_cb(
eth_Evt,
value,
ethCfg->eth_sw_cfg->eth_switch.obj.cb_context);
eth_Evt, value, ethCfg->eth_sw_cfg->eth_switch.obj.cb_context);
}
}
}
@@ -203,7 +201,8 @@ static void _ethernet_sw_isr(void *context) {
/*****************************************************************************
*****************************************************************************/
void eth_sw_setAlertHandler(Eth_cfg *ethCfg, Eth_Sw_CallbackFn alert_cb,
void *cb_context) {
void *cb_context)
{
ethCfg->eth_sw_cfg->eth_switch.obj.alert_cb = alert_cb;
ethCfg->eth_sw_cfg->eth_switch.obj.cb_context = cb_context;
}
@@ -211,15 +210,15 @@ void eth_sw_setAlertHandler(Eth_cfg *ethCfg, Eth_Sw_CallbackFn alert_cb,
ePostCode eth_sw_init(Eth_cfg *ethCfg)
{
ePostCode ret = POST_DEV_CFG_DONE;
//TODO: Enabling of the ethernet interrupts requires some more work.
// TODO: Enabling of the ethernet interrupts requires some more work.
/*
if (ethCfg->eth_sw_cfg.pin_evt) {
const uint32_t pin_evt_cfg = OCGPIO_CFG_INPUT | OCGPIO_CFG_INT_FALLING;
if (OcGpio_configure(ethCfg->eth_sw_cfg.pin_evt, pin_evt_cfg) < OCGPIO_SUCCESS) {
ret = POST_DEV_CFG_FAIL;
} else {
if (OcGpio_configure(ethCfg->eth_sw_cfg.pin_evt, pin_evt_cfg) <
OCGPIO_SUCCESS) { ret = POST_DEV_CFG_FAIL; } else {
// Use a threaded interrupt to handle IRQ
ThreadedInt_Init(ethCfg->eth_sw_cfg.pin_evt, _ethernet_sw_isr, (void *)ethCfg);
ThreadedInt_Init(ethCfg->eth_sw_cfg.pin_evt, _ethernet_sw_isr, (void
*)ethCfg);
}
}
*/
@@ -230,11 +229,14 @@ ReturnStatus eth_sw_get_status_speed(uint8_t port, port_speed *speed)
{
ReturnStatus ret = RETURN_OK;
if (mdiobb_read_by_paging(port, REG_PHY_CONTROL) & AUTONEG_EN)
*speed = (RES_SPEED & mdiobb_read_by_paging(port, REG_PHY_SPEC_STATUS)) ?
SPEED_100M : SPEED_10M;
*speed =
(RES_SPEED & mdiobb_read_by_paging(port, REG_PHY_SPEC_STATUS)) ?
SPEED_100M :
SPEED_10M;
else
*speed = (SPEED & mdiobb_read_by_paging(port, REG_PHY_CONTROL)) ?
SPEED_100M : SPEED_10M;
SPEED_100M :
SPEED_10M;
return ret;
}
@@ -242,35 +244,39 @@ ReturnStatus eth_sw_get_status_duplex(uint8_t port, port_duplex *duplex)
{
ReturnStatus ret = RETURN_OK;
if (mdiobb_read_by_paging(port, REG_PHY_CONTROL) & AUTONEG_EN)
*duplex = (RES_DUPLEX & mdiobb_read_by_paging(port, REG_PHY_SPEC_STATUS)) ?
FULL_DUPLEX : HALF_DUPLEX;
*duplex =
(RES_DUPLEX & mdiobb_read_by_paging(port, REG_PHY_SPEC_STATUS)) ?
FULL_DUPLEX :
HALF_DUPLEX;
else
*duplex = (DUPLEX & mdiobb_read_by_paging(port, REG_PHY_CONTROL)) ?
FULL_DUPLEX : HALF_DUPLEX;
FULL_DUPLEX :
HALF_DUPLEX;
return ret;
}
ReturnStatus eth_sw_get_status_auto_neg(uint8_t port, uint8_t *autoneg_on)
{
ReturnStatus ret = RETURN_OK;
*autoneg_on = (AUTONEG_EN & mdiobb_read_by_paging(port, REG_PHY_CONTROL)) ?
1 : 0;
*autoneg_on =
(AUTONEG_EN & mdiobb_read_by_paging(port, REG_PHY_CONTROL)) ? 1 : 0;
return ret;
}
ReturnStatus eth_sw_get_status_sleep_mode(uint8_t port, uint8_t *sleep_mode_en)
{
ReturnStatus ret = RETURN_OK;
*sleep_mode_en = (SLEEP_MODE & mdiobb_read_by_paging(port, REG_PHY_SPEC_STATUS)) ?
1 : 0;
*sleep_mode_en =
(SLEEP_MODE & mdiobb_read_by_paging(port, REG_PHY_SPEC_STATUS)) ? 1 : 0;
return ret;
}
ReturnStatus eth_sw_get_status_auto_neg_complete(uint8_t port, uint8_t *autoneg_complete)
ReturnStatus eth_sw_get_status_auto_neg_complete(uint8_t port,
uint8_t *autoneg_complete)
{
ReturnStatus ret = RETURN_OK;
*autoneg_complete = (AUTONEG_DONE & mdiobb_read_by_paging(port, REG_PHY_STATUS)) ?
1 : 0;
*autoneg_complete =
(AUTONEG_DONE & mdiobb_read_by_paging(port, REG_PHY_STATUS)) ? 1 : 0;
return ret;
}
@@ -296,26 +302,26 @@ ReturnStatus restart_autoneg(uint8_t port)
ReturnStatus eth_sw_set_config_speed(uint8_t port, port_speed speed)
{
ReturnStatus ret = RETURN_OK;
uint16_t read_val =0x0000;
uint16_t read_val = 0x0000;
switch (speed) {
case SPEED_10M:
read_val = mdiobb_read_by_paging(port, REG_PHY_CONTROL);
CLEAR_BIT((AUTONEG_EN | SPEED), read_val);
SET_BIT(SOFT_RESET, read_val);
mdiobb_write_by_paging(port, REG_PHY_CONTROL, read_val);
break;
case SPEED_100M:
read_val = mdiobb_read_by_paging(port, REG_PHY_CONTROL);
CLEAR_BIT(AUTONEG_EN, read_val);
SET_BIT((SOFT_RESET | SPEED), read_val);
mdiobb_write_by_paging(port, REG_PHY_CONTROL, read_val);
break;
case SPEED_AUTONEG:
restart_autoneg(port);
break;
default:
DEBUG("Invalid Ethernet speed set option");
return RETURN_NOTOK;
case SPEED_10M:
read_val = mdiobb_read_by_paging(port, REG_PHY_CONTROL);
CLEAR_BIT((AUTONEG_EN | SPEED), read_val);
SET_BIT(SOFT_RESET, read_val);
mdiobb_write_by_paging(port, REG_PHY_CONTROL, read_val);
break;
case SPEED_100M:
read_val = mdiobb_read_by_paging(port, REG_PHY_CONTROL);
CLEAR_BIT(AUTONEG_EN, read_val);
SET_BIT((SOFT_RESET | SPEED), read_val);
mdiobb_write_by_paging(port, REG_PHY_CONTROL, read_val);
break;
case SPEED_AUTONEG:
restart_autoneg(port);
break;
default:
DEBUG("Invalid Ethernet speed set option");
return RETURN_NOTOK;
}
return ret;
}
@@ -323,31 +329,31 @@ ReturnStatus eth_sw_set_config_speed(uint8_t port, port_speed speed)
ReturnStatus eth_sw_set_config_duplex(uint8_t port, port_duplex duplex)
{
ReturnStatus ret = RETURN_OK;
uint16_t read_val =0x0000;
uint16_t read_val = 0x0000;
switch (duplex) {
case SPEED_10M:
read_val = mdiobb_read_by_paging(port, REG_PHY_CONTROL);
CLEAR_BIT((AUTONEG_EN | DUPLEX), read_val);
SET_BIT(SOFT_RESET, read_val);
mdiobb_write_by_paging(port, REG_PHY_CONTROL, read_val);
break;
case SPEED_100M:
read_val = mdiobb_read_by_paging(port, REG_PHY_CONTROL);
CLEAR_BIT(AUTONEG_EN, read_val);
SET_BIT((SOFT_RESET | DUPLEX), read_val);
mdiobb_write_by_paging(port, REG_PHY_CONTROL, read_val);
break;
case SPEED_AUTONEG:
restart_autoneg(port);
break;
default:
DEBUG("Invalid Ethernet speed set option");
return RETURN_NOTOK;
case SPEED_10M:
read_val = mdiobb_read_by_paging(port, REG_PHY_CONTROL);
CLEAR_BIT((AUTONEG_EN | DUPLEX), read_val);
SET_BIT(SOFT_RESET, read_val);
mdiobb_write_by_paging(port, REG_PHY_CONTROL, read_val);
break;
case SPEED_100M:
read_val = mdiobb_read_by_paging(port, REG_PHY_CONTROL);
CLEAR_BIT(AUTONEG_EN, read_val);
SET_BIT((SOFT_RESET | DUPLEX), read_val);
mdiobb_write_by_paging(port, REG_PHY_CONTROL, read_val);
break;
case SPEED_AUTONEG:
restart_autoneg(port);
break;
default:
DEBUG("Invalid Ethernet speed set option");
return RETURN_NOTOK;
}
return ret;
}
ReturnStatus eth_sw_set_config_power_down(uint8_t port,uint8_t power_down)
ReturnStatus eth_sw_set_config_power_down(uint8_t port, uint8_t power_down)
{
ReturnStatus ret = RETURN_OK;
if (power_down)
@@ -357,8 +363,8 @@ ReturnStatus eth_sw_set_config_power_down(uint8_t port,uint8_t power_down)
return ret;
}
ReturnStatus eth_sw_set_config_sleep_mode_enable(uint8_t port,uint8_t sleep_mode_en)
ReturnStatus eth_sw_set_config_sleep_mode_enable(uint8_t port,
uint8_t sleep_mode_en)
{
ReturnStatus ret = RETURN_OK;
if (sleep_mode_en)
@@ -374,53 +380,56 @@ ReturnStatus get_interrupt(uint8_t port)
return mdiobb_read_by_paging(port, REG_PHY_INTERRUPT_EN);
}
ReturnStatus eth_sw_set_config_interrupt_enable(uint8_t port, uint8_t *interrupt_mask)
ReturnStatus eth_sw_set_config_interrupt_enable(uint8_t port,
uint8_t *interrupt_mask)
{
ReturnStatus ret = RETURN_OK;
uint16_t i = 0;
uint16_t write_val = get_interrupt(port);
for (i = 0; (1 << i) != 0x10; i++) {
switch ((1 << i)) {
case ETH_ALERT_SPEED_CHANGE:
(*interrupt_mask & ETH_ALERT_SPEED_CHANGE) ?
(write_val |= SPEED_INT_EN) : (write_val &= ~SPEED_INT_EN);
break;
case ETH_ALERT_DUPLEX_CHANGE:
(*interrupt_mask & ETH_ALERT_DUPLEX_CHANGE) ?
(write_val |= DUPLEX_INT_EN) : (write_val &= ~DUPLEX_INT_EN);
break;
case ETH_ALERT_AUTONEG_DONE:
(*interrupt_mask & ETH_ALERT_AUTONEG_DONE) ?
(write_val |= AUTONEG_COMPLETE_INT_EN) :
(write_val &= ~AUTONEG_COMPLETE_INT_EN);
break;
case ETH_ALERT_LINK_CHANGE:
(*interrupt_mask & ETH_ALERT_LINK_CHANGE) ?
(write_val |= LINK_CHANGE_INT_EN) :
(write_val &= ~LINK_CHANGE_INT_EN);
break;
case ETH_ALERT_CROSSOVER_DET:
(*interrupt_mask & ETH_ALERT_CROSSOVER_DET) ?
(write_val |= MDI_CROSSOVER_INT_EN) :
(write_val &= ~MDI_CROSSOVER_INT_EN);
break;
case ETH_ALERT_ENERGY_DET:
(*interrupt_mask & ETH_ALERT_ENERGY_DET) ?
(write_val |= ENERGY_DET_INT_EN) :
(write_val &= ~ENERGY_DET_INT_EN);
break;
case ETH_ALERT_POLARITY_DET:
(*interrupt_mask & ETH_ALERT_POLARITY_DET) ?
(write_val |= POLARITY_INT_EN) :
(write_val &= ~POLARITY_INT_EN);
break;
case ETH_ALERT_JABBER_DET:
(*interrupt_mask & ETH_ALERT_JABBER_DET) ?
(write_val |= JABBER_INT_EN) :
(write_val &= ~JABBER_INT_EN);
default:
DEBUG("Interrupt not supported");
return RETURN_NOTOK;
case ETH_ALERT_SPEED_CHANGE:
(*interrupt_mask & ETH_ALERT_SPEED_CHANGE) ?
(write_val |= SPEED_INT_EN) :
(write_val &= ~SPEED_INT_EN);
break;
case ETH_ALERT_DUPLEX_CHANGE:
(*interrupt_mask & ETH_ALERT_DUPLEX_CHANGE) ?
(write_val |= DUPLEX_INT_EN) :
(write_val &= ~DUPLEX_INT_EN);
break;
case ETH_ALERT_AUTONEG_DONE:
(*interrupt_mask & ETH_ALERT_AUTONEG_DONE) ?
(write_val |= AUTONEG_COMPLETE_INT_EN) :
(write_val &= ~AUTONEG_COMPLETE_INT_EN);
break;
case ETH_ALERT_LINK_CHANGE:
(*interrupt_mask & ETH_ALERT_LINK_CHANGE) ?
(write_val |= LINK_CHANGE_INT_EN) :
(write_val &= ~LINK_CHANGE_INT_EN);
break;
case ETH_ALERT_CROSSOVER_DET:
(*interrupt_mask & ETH_ALERT_CROSSOVER_DET) ?
(write_val |= MDI_CROSSOVER_INT_EN) :
(write_val &= ~MDI_CROSSOVER_INT_EN);
break;
case ETH_ALERT_ENERGY_DET:
(*interrupt_mask & ETH_ALERT_ENERGY_DET) ?
(write_val |= ENERGY_DET_INT_EN) :
(write_val &= ~ENERGY_DET_INT_EN);
break;
case ETH_ALERT_POLARITY_DET:
(*interrupt_mask & ETH_ALERT_POLARITY_DET) ?
(write_val |= POLARITY_INT_EN) :
(write_val &= ~POLARITY_INT_EN);
break;
case ETH_ALERT_JABBER_DET:
(*interrupt_mask & ETH_ALERT_JABBER_DET) ?
(write_val |= JABBER_INT_EN) :
(write_val &= ~JABBER_INT_EN);
default:
DEBUG("Interrupt not supported");
return RETURN_NOTOK;
}
}
mdiobb_write_by_paging(port, REG_PHY_INTERRUPT_EN, write_val);
@@ -431,42 +440,42 @@ ReturnStatus eth_sw_set_config_soft_reset(uint8_t port)
{
ReturnStatus ret = RETURN_OK;
/* write into REG_PHY_CONTROL bit# 15 */
mdiobb_set_bits(port, REG_PHY_CONTROL, SOFT_RESET);
return ret;
mdiobb_set_bits(port, REG_PHY_CONTROL, SOFT_RESET);
return ret;
}
ReturnStatus eth_sw_enable_loopback(void *driver, void *params){
ReturnStatus eth_sw_enable_loopback(void *driver, void *params)
{
ReturnStatus status = RETURN_OK;
Eth_cfg* s_eth_cfg = (Eth_cfg*)driver;
Eth_LoopBack_Params* s_eth_lpback = (Eth_LoopBack_Params*)params;
switch (s_eth_lpback->loopBackType)
{
case MACLOOPBACK:
status = eth_sw_enable_macloopback(s_eth_cfg->eth_sw_port);
break;
/*TODO: Implementation to be done for Line and External Loopback*/
case LINELOOPBACK:
case EXTLOOPBACK:
default:
break;
Eth_cfg *s_eth_cfg = (Eth_cfg *)driver;
Eth_LoopBack_Params *s_eth_lpback = (Eth_LoopBack_Params *)params;
switch (s_eth_lpback->loopBackType) {
case MACLOOPBACK:
status = eth_sw_enable_macloopback(s_eth_cfg->eth_sw_port);
break;
/*TODO: Implementation to be done for Line and External Loopback*/
case LINELOOPBACK:
case EXTLOOPBACK:
default:
break;
}
return status;
}
ReturnStatus eth_sw_disable_loopback(void *driver, void *params){
ReturnStatus eth_sw_disable_loopback(void *driver, void *params)
{
ReturnStatus status = RETURN_OK;
Eth_cfg* s_eth_cfg = (Eth_cfg*)driver;
Eth_LoopBack_Params* s_eth_lpback = (Eth_LoopBack_Params*)params;
switch (s_eth_lpback->loopBackType)
{
case MACLOOPBACK:
status = eth_sw_disable_macloopback(s_eth_cfg->eth_sw_port);
break;
/*TODO: Implementation to be done for Line and External Loopback*/
case LINELOOPBACK:
case EXTLOOPBACK:
default:
break;
Eth_cfg *s_eth_cfg = (Eth_cfg *)driver;
Eth_LoopBack_Params *s_eth_lpback = (Eth_LoopBack_Params *)params;
switch (s_eth_lpback->loopBackType) {
case MACLOOPBACK:
status = eth_sw_disable_macloopback(s_eth_cfg->eth_sw_port);
break;
/*TODO: Implementation to be done for Line and External Loopback*/
case LINELOOPBACK:
case EXTLOOPBACK:
default:
break;
}
return status;
}
@@ -491,32 +500,36 @@ ReturnStatus eth_sw_disable_macloopback(uint8_t port)
ReturnStatus eth_sw_enable_packet_gen(void *driver, void *params)
{
ReturnStatus ret = RETURN_OK;
Eth_cfg* s_eth_cfg = (Eth_cfg*)driver;
Eth_PacketGen_Params* s_eth_packetParams = (Eth_PacketGen_Params*)params;
/*Packet generator params such as packet length, payload type, frame count etc are set in REG_C45_PACKET_GEN*/
mdiobb_write_by_paging_c45(s_eth_cfg->eth_sw_port, REG_C45_PACKET_GEN, s_eth_packetParams->reg_value);
Eth_cfg *s_eth_cfg = (Eth_cfg *)driver;
Eth_PacketGen_Params *s_eth_packetParams = (Eth_PacketGen_Params *)params;
/*Packet generator params such as packet length, payload type, frame count
* etc are set in REG_C45_PACKET_GEN*/
mdiobb_write_by_paging_c45(s_eth_cfg->eth_sw_port, REG_C45_PACKET_GEN,
s_eth_packetParams->reg_value);
return ret;
}
ReturnStatus eth_sw_disable_packet_gen(void *driver)
{
ReturnStatus ret = RETURN_OK;
Eth_cfg* s_eth_cfg = (Eth_cfg*)driver;
mdiobb_clear_bits_C45(s_eth_cfg->eth_sw_port, REG_C45_PACKET_GEN, PACKET_GEN_EN);
Eth_cfg *s_eth_cfg = (Eth_cfg *)driver;
mdiobb_clear_bits_C45(s_eth_cfg->eth_sw_port, REG_C45_PACKET_GEN,
PACKET_GEN_EN);
return ret;
}
char *convString(int i, char *result)
{
sprintf(result,"%d",i);
sprintf(result, "%d", i);
return result;
}
ReturnStatus eth_sw_config_tiva_client(void *driver, void *params) {
ReturnStatus eth_sw_config_tiva_client(void *driver, void *params)
{
ReturnStatus ret = RETURN_OK;
int count = 0;
Eth_cfg* s_eth_cfg = (Eth_cfg*)driver;
Eth_TcpClient_Params *s_eth_tcpParams = (Eth_TcpClient_Params*)params;
Eth_cfg *s_eth_cfg = (Eth_cfg *)driver;
Eth_TcpClient_Params *s_eth_tcpParams = (Eth_TcpClient_Params *)params;
Task_Handle taskHandle_client;
Task_Params taskParams;
@@ -530,7 +543,7 @@ ReturnStatus eth_sw_config_tiva_client(void *driver, void *params) {
do {
convString(s_eth_tcpParams->ipAddress[count], tempBuf);
strcat(convStr, tempBuf);
if((MAX - 1) != count) {
if ((MAX - 1) != count) {
strcat(convStr, ".");
}
count++;
@@ -547,7 +560,8 @@ ReturnStatus eth_sw_config_tiva_client(void *driver, void *params) {
taskParams.priority = ETHTIVACLEINT_TASK_PRIORITY;
taskParams.arg0 = s_eth_tcpParams->tcpPort;
taskHandle_client = Task_create((Task_FuncPtr) tcpHandler_client, &taskParams, &eb);
taskHandle_client =
Task_create((Task_FuncPtr)tcpHandler_client, &taskParams, &eb);
if (taskHandle_client == NULL) {
System_printf("Failed to create taskHandle_client Task\n");
}
@@ -560,49 +574,53 @@ ReturnStatus eth_sw_set_config_restart_neg(uint8_t port)
ReturnStatus ret = RETURN_OK;
/* write into PHY control register & in autoneg enable bit */
mdiobb_set_bits(port, REG_PHY_CONTROL,
(RESTART_AUTONEG | AUTONEG_EN | SOFT_RESET));
(RESTART_AUTONEG | AUTONEG_EN | SOFT_RESET));
return ret;
}
ReturnStatus eth_sw_get_config_speed(uint8_t port, port_speed* speed)
ReturnStatus eth_sw_get_config_speed(uint8_t port, port_speed *speed)
{
ReturnStatus ret = RETURN_OK;
if (AUTONEG_EN & mdiobb_read_by_paging(port, REG_PHY_CONTROL))
if (AUTONEG_EN & mdiobb_read_by_paging(port, REG_PHY_CONTROL))
*speed = SPEED_AUTONEG;
else
*speed = SPEED & mdiobb_read_by_paging(port, REG_PHY_CONTROL) ?
SPEED_100M : SPEED_10M;
SPEED_100M :
SPEED_10M;
return ret;
}
ReturnStatus eth_sw_get_config_duplex(uint8_t port, port_duplex* duplex)
ReturnStatus eth_sw_get_config_duplex(uint8_t port, port_duplex *duplex)
{
ReturnStatus ret = RETURN_OK;
if (AUTONEG_EN & mdiobb_read_by_paging(port, REG_PHY_CONTROL))
if (AUTONEG_EN & mdiobb_read_by_paging(port, REG_PHY_CONTROL))
*duplex = DUPLEX_AUTONEG;
else
*duplex = (DUPLEX & mdiobb_read_by_paging(port, REG_PHY_CONTROL)) ?
FULL_DUPLEX : HALF_DUPLEX;
FULL_DUPLEX :
HALF_DUPLEX;
return ret;
}
ReturnStatus eth_sw_get_config_power_down(uint8_t port, uint8_t* power_dwn)
ReturnStatus eth_sw_get_config_power_down(uint8_t port, uint8_t *power_dwn)
{
ReturnStatus ret = RETURN_OK;
*power_dwn = (PWR_DOWN & mdiobb_read_by_paging(port, REG_PHY_CONTROL)) ?
1 : 0;
*power_dwn =
(PWR_DOWN & mdiobb_read_by_paging(port, REG_PHY_CONTROL)) ? 1 : 0;
return ret;
}
ReturnStatus eth_sw_get_config_sleep_mode(uint8_t port, uint8_t* sleep_mode)
ReturnStatus eth_sw_get_config_sleep_mode(uint8_t port, uint8_t *sleep_mode)
{
ReturnStatus ret = RETURN_OK;
*sleep_mode = (ENERGY_DET & mdiobb_read_by_paging(port, REG_PHY_SPEC_CONTROL)) ?
1 : 0;
*sleep_mode =
(ENERGY_DET & mdiobb_read_by_paging(port, REG_PHY_SPEC_CONTROL)) ? 1 :
0;
return ret;
}
ReturnStatus eth_sw_get_config_interrupt_enable(uint8_t port, uint8_t* interrupt_enb)
ReturnStatus eth_sw_get_config_interrupt_enable(uint8_t port,
uint8_t *interrupt_enb)
{
ReturnStatus ret = RETURN_OK;
/* read the register REG_PHY_INTERRUPT_EN */

216
firmware/ec/src/devices/g510.c
View File

@@ -25,45 +25,45 @@
/* TODO: move to helper? */
#define STATIC_STRLEN(s) (ARRAY_SIZE(s) - 1)
#define TESTMOD_TASK_PRIORITY 2
#define TESTMOD_TASK_STACK_SIZE 2048
#define TESTMOD_TASK_PRIORITY 2
#define TESTMOD_TASK_STACK_SIZE 2048
#define G510_WRITE_TIMEOUT 500
#define G510_READ_TIMEOUT 5000
/* G510 enable line is active-low */
#define GSM_EN_ASSERT (0)
#define GSM_EN_ASSERT (0)
#define GSM_EN_DEASSERT (1)
#define GSM_PWR_EN_ASSERT (1)
#define GSM_PWR_EN_ASSERT (1)
#define GSM_PWR_EN_DEASSERT (0)
#define GSM_SHUTDOWN_TIME 200
#define GSM_COOLDOWN_TIME 50
typedef enum {
TWOG_SIM_CALLSTATE_CHANGE = 0,
TWOG_SIM_INCOMING_MSG = 1,
TWOG_SIM_ALERT_PARAMS_MAX /* Limiter */
TWOG_SIM_CALLSTATE_CHANGE = 0,
TWOG_SIM_INCOMING_MSG = 1,
TWOG_SIM_ALERT_PARAMS_MAX /* Limiter */
} eTEST_MOD_ALERTParam;
typedef enum {
TWOG_CALL_EVT_RING = 0,
typedef enum {
TWOG_CALL_EVT_RING = 0,
TWOG_CALL_EVT_CALL_END = 1,
} eTEST_MODE_CallEvent;
typedef enum {
TWOG_IMEI = 0,
TWOG_IMSI = 1,
TWOG_GETMFG = 2,
TWOG_GETMODEL = 3,
TWOG_RSSI = 4,
TWOG_BER = 5,
TWOG_REGSTATUS = 6,
TWOG_NETWORK_OP_INFO = 7,
TWOG_CELLID = 8,
TWOG_BSIC = 9,
TWOG_LASTERR = 10,
TWOG_PARAM_MAX /* Limiter */
TWOG_IMEI = 0,
TWOG_IMSI = 1,
TWOG_GETMFG = 2,
TWOG_GETMODEL = 3,
TWOG_RSSI = 4,
TWOG_BER = 5,
TWOG_REGSTATUS = 6,
TWOG_NETWORK_OP_INFO = 7,
TWOG_CELLID = 8,
TWOG_BSIC = 9,
TWOG_LASTERR = 10,
TWOG_PARAM_MAX /* Limiter */
} eTestModule_StatusParam;
static UART_Handle uartGsm;
@@ -89,7 +89,7 @@ static void cmti_cb(const GsmCmtiInfo *info, void *context)
static void call_state_cb(const GsmClccInfo *info, void *context)
{
LOGGER("CLCC %u\n", info->call_state);
LOGGER("CLCC %u\n", info->call_state);
switch (info->call_state) {
case GSM_CALL_STATE_INCOMING: {
eTEST_MODE_CallEvent callState = TWOG_CALL_EVT_RING;
@@ -105,22 +105,21 @@ static void call_state_cb(const GsmClccInfo *info, void *context)
}
/* Configures the various IO pins associated with this subsystem */
static bool configure_io(TestMod_Cfg *testmod_cfg) {
//const TestMod_Cfg *testmod_cfg = (TestMod_Cfg *)testModuleCfg;
G510_Cfg *cfg = &testmod_cfg->g510_cfg;
static bool configure_io(TestMod_Cfg *testmod_cfg)
{
// const TestMod_Cfg *testmod_cfg = (TestMod_Cfg *)testModuleCfg;
G510_Cfg *cfg = &testmod_cfg->g510_cfg;
OcGpio_configure(&cfg->pin_sim_present, OCGPIO_CFG_INPUT);
OcGpio_configure(&cfg->pin_enable, OCGPIO_CFG_OUTPUT |
OCGPIO_CFG_OUT_LOW);
OcGpio_configure(&cfg->pin_pwr_en, OCGPIO_CFG_OUTPUT |
OCGPIO_CFG_OUT_LOW);
OcGpio_configure(&cfg->pin_enable, OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW);
OcGpio_configure(&cfg->pin_pwr_en, OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW);
return true;
}
static UART_Handle open_comm(TestMod_Cfg * testmod_cfg)
static UART_Handle open_comm(TestMod_Cfg *testmod_cfg)
{
//const TestMod_Cfg *testmod_cfg = (TestMod_Cfg *)testModuleCfg;
// const TestMod_Cfg *testmod_cfg = (TestMod_Cfg *)testModuleCfg;
// Open GSM UART
UART_Params uartParams;
@@ -138,9 +137,9 @@ static UART_Handle open_comm(TestMod_Cfg * testmod_cfg)
return UART_open(testmod_cfg->g510_cfg.uart, &uartParams);
}
static bool g510_reset(TestMod_Cfg * testmod_cfg)
static bool g510_reset(TestMod_Cfg *testmod_cfg)
{
//const TestMod_Cfg *testmod_cfg = (TestMod_Cfg *)testModuleCfg;
// const TestMod_Cfg *testmod_cfg = (TestMod_Cfg *)testModuleCfg;
const G510_Cfg *cfg = &testmod_cfg->g510_cfg;
/* Ensure the enable line is high (deasserted) so the module doesn't
@@ -184,8 +183,7 @@ static bool g510_reset(TestMod_Cfg * testmod_cfg)
return true;
}
ReturnStatus g510_init(TestMod_Cfg* testModuleCfg, const void *alert_token)
ReturnStatus g510_init(TestMod_Cfg *testModuleCfg, const void *alert_token)
{
if (!configure_io(testModuleCfg)) {
return RETURN_NOTOK;
@@ -243,7 +241,7 @@ static void testModule_task(UArg a0, UArg a1)
GSM_cimi(s_hGsm, &imsi);
/* TODO: hack because System_printf is crappy and doesn't support %llu */
char imsiStr[16];
snprintf(imsiStr, sizeof(imsiStr), "%"PRIu64, imsi);
snprintf(imsiStr, sizeof(imsiStr), "%" PRIu64, imsi);
LOGGER("IMSI: %s\n", imsiStr);
/* NOTE: if the message storage fills up, the G510 will just
@@ -255,7 +253,7 @@ static void testModule_task(UArg a0, UArg a1)
GSM_clccSet(s_hGsm, true); /* Enable clcc (call state) msg */
/* Finish device configuration */
if (!GSM_cnmi(s_hGsm, 2, 1, 0, 0 , 0) || /* enable sms arrival notif */
if (!GSM_cnmi(s_hGsm, 2, 1, 0, 0, 0) || /* enable sms arrival notif */
!GSM_cmgf(s_hGsm, GSM_MSG_FMT_TEXT) || /* set to text mode */
!GSM_csmp(s_hGsm, 17, 167, 0, 0) || /* text mode parameters */
!GSM_csdh(s_hGsm, true)) { /* display extra info for cgmr */
@@ -267,7 +265,8 @@ static void testModule_task(UArg a0, UArg a1)
GSM_cnma(s_hGsm);
static char sms[160];
if (GSM_cmgr(s_hGsm, sms_idx, sms, NULL)) {
LOGGER("SMS: %.*s\n", 50, sms); // System_printf has a limited buffer
LOGGER("SMS: %.*s\n", 50,
sms); // System_printf has a limited buffer
OCMP_GenerateAlert(alert_token, TWOG_SIM_INCOMING_MSG, sms);
} else {
LOGGER_ERROR("TESTMOD:Failed to read SMS\n");
@@ -276,7 +275,7 @@ static void testModule_task(UArg a0, UArg a1)
GSM_cmgd(s_hGsm, sms_idx, GSM_CMGD_DELETE_AT_INDEX);
sms_idx = -1;
//if (GSM_cmgs(s_hGsm, "29913", "Hello from GSM :)") < 0) {
// if (GSM_cmgs(s_hGsm, "29913", "Hello from GSM :)") < 0) {
// LOGGER_ERROR("TESTMOD:Error sending SMS\n");
//}
}
@@ -306,130 +305,128 @@ ePostCode g510_task_init(void *driver, const void **config,
taskParams.arg0 = (intptr_t)alert_token;
Task_Handle task = Task_create(testModule_task, &taskParams, NULL);
if (!task) {
LOGGER("TESTMOD::FATAL: Unable to start G510 task\n");
LOGGER("TESTMOD::FATAL: Unable to start G510 task\n");
Semaphore_delete(&sem_simReady);
Semaphore_delete(&sem_sms);
return POST_DEV_CFG_FAIL;
}
if (g510_init(driver,alert_token) != RETURN_OK) {
if (g510_init(driver, alert_token) != RETURN_OK) {
return POST_DEV_CFG_FAIL;
}
return POST_DEV_CFG_DONE;
}
bool g510_get_imei( TestMod_2G_Status_Data *p2gStatusData)
bool g510_get_imei(TestMod_2G_Status_Data *p2gStatusData)
{
GsmCgsnInfo cgsnInfo;
if (!GSM_cgsn(s_hGsm, &cgsnInfo)) {
return false;
}
p2gStatusData->imei = strtoull(cgsnInfo.imei, NULL, 10);
return true;
GsmCgsnInfo cgsnInfo;
if (!GSM_cgsn(s_hGsm, &cgsnInfo)) {
return false;
}
p2gStatusData->imei = strtoull(cgsnInfo.imei, NULL, 10);
return true;
}
bool g510_get_imsi( TestMod_2G_Status_Data *p2gStatusData)
bool g510_get_imsi(TestMod_2G_Status_Data *p2gStatusData)
{
uint64_t imsi;
if (!GSM_cimi(s_hGsm, &imsi)) {
return false;
}
p2gStatusData->imsi = imsi;
return true;
uint64_t imsi;
if (!GSM_cimi(s_hGsm, &imsi)) {
return false;
}
p2gStatusData->imsi = imsi;
return true;
}
bool g510_get_mfg( TestMod_2G_Status_Data *p2gStatusData)
bool g510_get_mfg(TestMod_2G_Status_Data *p2gStatusData)
{
GsmCgmiInfo cgmiInfo;
if (!GSM_cgmi(s_hGsm, &cgmiInfo)) {
return false;
}
/* TODO: idea - make safe strncpy that always terminates str */
strncpy(p2gStatusData->mfg, cgmiInfo.mfgId,
sizeof(p2gStatusData->mfg));
return true;
GsmCgmiInfo cgmiInfo;
if (!GSM_cgmi(s_hGsm, &cgmiInfo)) {
return false;
}
/* TODO: idea - make safe strncpy that always terminates str */
strncpy(p2gStatusData->mfg, cgmiInfo.mfgId, sizeof(p2gStatusData->mfg));
return true;
}
bool g510_get_model( TestMod_2G_Status_Data *p2gStatusData)
bool g510_get_model(TestMod_2G_Status_Data *p2gStatusData)
{
GsmCgmmInfo cgmmInfo;
if (!GSM_cgmm(s_hGsm, &cgmmInfo)) {
return false;
}
strncpy(p2gStatusData->model, cgmmInfo.model,
sizeof(p2gStatusData->model));
return true;
GsmCgmmInfo cgmmInfo;
if (!GSM_cgmm(s_hGsm, &cgmmInfo)) {
return false;
}
strncpy(p2gStatusData->model, cgmmInfo.model, sizeof(p2gStatusData->model));
return true;
}
bool g510_get_rssi( TestMod_2G_Status_Data *p2gStatusData)
bool g510_get_rssi(TestMod_2G_Status_Data *p2gStatusData)
{
GsmCsqInfo csqInfo;
if (!GSM_csq(s_hGsm, &csqInfo)) {
return false;
}
p2gStatusData->rssi = csqInfo.rssi;
return true;
GsmCsqInfo csqInfo;
if (!GSM_csq(s_hGsm, &csqInfo)) {
return false;
}
p2gStatusData->rssi = csqInfo.rssi;
return true;
}
bool g510_get_ber( TestMod_2G_Status_Data *p2gStatusData)
bool g510_get_ber(TestMod_2G_Status_Data *p2gStatusData)
{
GsmCsqInfo csqInfo;
if (!GSM_csq(s_hGsm, &csqInfo)) {
return false;
}
p2gStatusData->ber = csqInfo.ber;
return true;
GsmCsqInfo csqInfo;
if (!GSM_csq(s_hGsm, &csqInfo)) {
return false;
}
p2gStatusData->ber = csqInfo.ber;
return true;
}
bool g510_get_regStatus( TestMod_2G_Status_Data *p2gStatusData)
bool g510_get_regStatus(TestMod_2G_Status_Data *p2gStatusData)
{
GsmCregInfo cregInfo;
if (!GSM_cregRead(s_hGsm, &cregInfo)) {
return false;
}
p2gStatusData->regStat = cregInfo.stat;
return true;
GsmCregInfo cregInfo;
if (!GSM_cregRead(s_hGsm, &cregInfo)) {
return false;
}
p2gStatusData->regStat = cregInfo.stat;
return true;
}
bool g510_get_cellId( TestMod_2G_Status_Data *p2gStatusData)
bool g510_get_cellId(TestMod_2G_Status_Data *p2gStatusData)
{
/* NOTE: requires CREG mode 2 (unsolicited + location info) */
GsmCregInfo cregInfo;
if (!GSM_cregRead(s_hGsm, &cregInfo)) {
return false;
}
p2gStatusData->cid = cregInfo.cid;
return true;
/* NOTE: requires CREG mode 2 (unsolicited + location info) */
GsmCregInfo cregInfo;
if (!GSM_cregRead(s_hGsm, &cregInfo)) {
return false;
}
p2gStatusData->cid = cregInfo.cid;
return true;
}
/* Command handling */
bool TestMod_cmdEnable(void *driver, void *params)
{
LOGGER("TESTMOD 2G Enable\n");
LOGGER("TESTMOD 2G Enable\n");
return GSM_cfun(s_hGsm, GSM_CFUN_FULL);
}
bool TestMod_cmdDisable(void *driver, void *params)
{
LOGGER("TESTMOD 2G Disable\n");
LOGGER("TESTMOD 2G Disable\n");
return GSM_cfun(s_hGsm, GSM_CFUN_AIRPLANE);
}
bool TestMod_cmdDisconnect(void *driver, void *params)
{
LOGGER("TESTMOD 2G Disconnect\n");
LOGGER("TESTMOD 2G Disconnect\n");
return GSM_cops(s_hGsm, GSM_COPS_MODE_DEREG, GSM_COPS_FMT_NUMERIC, "");
}
bool TestMod_cmdConnect(void *driver, void *params)
{
LOGGER("TESTMOD 2G Connect\n");
LOGGER("TESTMOD 2G Connect\n");
return GSM_cops(s_hGsm, GSM_COPS_MODE_AUTO, GSM_COPS_FMT_NUMERIC, "");
}
bool TestMod_cmdSendSms(void *driver, void *params)
{
LOGGER("TESTMOD 2G SMS\n");
LOGGER("TESTMOD 2G SMS\n");
/* TODO: we assume number is null terminated, should have check */
TestModule_sms *sms = params;
return GSM_cmgs(s_hGsm, sms->number, sms->msg);
@@ -446,19 +443,18 @@ bool TestMod_cmdDial(void *driver, void *params)
bool TestMod_cmdAnswer(void *driver, void *params)
{
LOGGER("TESTMOD 2G answer\n");
LOGGER("TESTMOD 2G answer\n");
return GSM_a(s_hGsm);
}
bool TestMod_cmdHangup(void *driver, void *params)
{
LOGGER("TESTMOD 2G hangup\n");
LOGGER("TESTMOD 2G hangup\n");
return GSM_h(s_hGsm);
}
bool TestMod_cmdReset(void *driver, void *params)
{
LOGGER("TESTMOD Reset\n");
LOGGER("TESTMOD Reset\n");
return false; /* Not yet implemented */
}

136
firmware/ec/src/devices/i2c/XR20M1170.c
View File

@@ -47,11 +47,9 @@ static const XrStopBit XR_STOP_BIT_MAP[] = {
};
static const XrParity XR_PARITY_MAP[] = {
[UART_PAR_NONE] = XR_PARITY_NONE,
[UART_PAR_EVEN] = XR_PARITY_EVEN,
[UART_PAR_ODD] = XR_PARITY_ODD,
[UART_PAR_ZERO] = XR_PARITY_ZERO,
[UART_PAR_ONE] = XR_PARITY_ONE,
[UART_PAR_NONE] = XR_PARITY_NONE, [UART_PAR_EVEN] = XR_PARITY_EVEN,
[UART_PAR_ODD] = XR_PARITY_ODD, [UART_PAR_ZERO] = XR_PARITY_ZERO,
[UART_PAR_ONE] = XR_PARITY_ONE,
};
// TXLVL IRQ will automatically fire after reset & give us the actual level
@@ -59,7 +57,7 @@ static XrRegTxlvl s_txEmptyBytes = 0;
// UART function table for XR20M1170 implementation
void XR20M1170_close(UART_Handle handle);
int XR20M1170_control(UART_Handle handle, unsigned int cmd, void *arg);
int XR20M1170_control(UART_Handle handle, unsigned int cmd, void *arg);
void XR20M1170_init(UART_Handle handle);
UART_Handle XR20M1170_open(UART_Handle handle, UART_Params *params);
int XR20M1170_read(UART_Handle handle, void *buffer, size_t size);
@@ -70,26 +68,23 @@ int XR20M1170_writePolling(UART_Handle handle, const void *buffer, size_t size);
void XR20M1170_writeCancel(UART_Handle handle);
const UART_FxnTable XR20M1170_fxnTable = {
XR20M1170_close,
XR20M1170_control,
XR20M1170_init,
XR20M1170_open,
XR20M1170_read,
XR20M1170_readPolling,
XR20M1170_readCancel,
XR20M1170_write,
XR20M1170_writePolling,
XR20M1170_close, XR20M1170_control, XR20M1170_init,
XR20M1170_open, XR20M1170_read, XR20M1170_readPolling,
XR20M1170_readCancel, XR20M1170_write, XR20M1170_writePolling,
XR20M1170_writeCancel
};
static XrSubAddress getSubAddress(XrRegister reg) {
return (XrSubAddress) {
static XrSubAddress getSubAddress(XrRegister reg)
{
return (XrSubAddress){
.channel = XR_CHANNEL_A, // The only supported option
.reg = reg,
};
}
static bool writeData(UART_Handle handle, XrRegister reg, const void *buffer, size_t size) {
static bool writeData(UART_Handle handle, XrRegister reg, const void *buffer,
size_t size)
{
XR20M1170_Object *object = handle->object;
const XR20M1170_HWAttrs *hwAttrs = handle->hwAttrs;
@@ -101,7 +96,9 @@ static bool writeData(UART_Handle handle, XrRegister reg, const void *buffer, si
return true;
}
static void readData(UART_Handle handle, XrRegister reg, void *buffer, size_t size) {
static void readData(UART_Handle handle, XrRegister reg, void *buffer,
size_t size)
{
XR20M1170_Object *object = handle->object;
const XR20M1170_HWAttrs *hwAttrs = handle->hwAttrs;
@@ -111,10 +108,12 @@ static void readData(UART_Handle handle, XrRegister reg, void *buffer, size_t si
}
}
void XR20M1170_close(UART_Handle handle) {
void XR20M1170_close(UART_Handle handle)
{
}
int XR20M1170_control(UART_Handle handle, unsigned int cmd, void *arg) {
int XR20M1170_control(UART_Handle handle, unsigned int cmd, void *arg)
{
XR20M1170_Object *object = handle->object;
// Most of the commands require this info, might as well dedupe
@@ -126,21 +125,18 @@ int XR20M1170_control(UART_Handle handle, unsigned int cmd, void *arg) {
}
GateMutex_leave(object->ringBufMutex, mutexKey);
switch(cmd) {
case UART_CMD_ISAVAILABLE:
{
switch (cmd) {
case UART_CMD_ISAVAILABLE: {
bool *available = arg;
*available = (rxLvl > 0);
return (UART_STATUS_SUCCESS);
}
case UART_CMD_GETRXCOUNT:
{
case UART_CMD_GETRXCOUNT: {
int *count = arg;
*count = rxLvl;
return (UART_STATUS_SUCCESS);
}
case UART_CMD_PEEK:
{
case UART_CMD_PEEK: {
int *byte = (int *)arg;
if (!rxLvl) {
*byte = UART_ERROR;
@@ -159,15 +155,17 @@ int XR20M1170_control(UART_Handle handle, unsigned int cmd, void *arg) {
}
// XR20M1170_init
void XR20M1170_init(UART_Handle handle) {
void XR20M1170_init(UART_Handle handle)
{
XR20M1170_Object *object = handle->object;
*object = (XR20M1170_Object) {
*object = (XR20M1170_Object){
.state.opened = false,
};
}
static void processIrq(void *context) {
static void processIrq(void *context)
{
UART_Handle handle = context;
XR20M1170_Object *object = handle->object;
@@ -176,10 +174,9 @@ static void processIrq(void *context) {
XrRegIsr isr;
readData(handle, XR_REG_ISR, &isr, sizeof(isr));
switch(isr.source) {
switch (isr.source) {
case ISR_SRC_RXRDY_TMOUT:
case ISR_SRC_RXRDY:
{
case ISR_SRC_RXRDY: {
// See how much data is available
XrRegRxlvl rxLvl;
readData(handle, XR_REG_RXLVL, &rxLvl, sizeof(rxLvl));
@@ -211,14 +208,16 @@ static void processIrq(void *context) {
// copy and maybe auto-locking
for (int i = 0; i < bytesToRead; ++i) {
RingBuf_put(&object->ringBuffer, buf[i]);
Semaphore_post(object->readSem); // TODO: move out of mutex lock?
Semaphore_post(
object->readSem); // TODO: move out of mutex lock?
}
}
GateMutex_leave(object->ringBufMutex, mutexKey);
break;
}
case ISR_SRC_TXRDY:
readData(handle, XR_REG_TXLVL, &s_txEmptyBytes, sizeof(s_txEmptyBytes));
readData(handle, XR_REG_TXLVL, &s_txEmptyBytes,
sizeof(s_txEmptyBytes));
Semaphore_post(object->writeSem);
break;
case ISR_SRC_LSR:
@@ -235,11 +234,13 @@ static void processIrq(void *context) {
}
static double calc_divisor(double xtal_freq, double prescaler, double baudRate,
double sampling_mode) {
double sampling_mode)
{
return (xtal_freq / prescaler) / (baudRate * sampling_mode);
}
static bool reset_ic(UART_Handle handle) {
static bool reset_ic(UART_Handle handle)
{
XrRegIOCtrl ioCtrl = {
.uartReset = true,
};
@@ -251,7 +252,8 @@ static bool reset_ic(UART_Handle handle) {
}
// Sets up the XR20M1170 registers to match desired settings
static bool register_config(UART_Handle handle, UART_Params *params) {
static bool register_config(UART_Handle handle, UART_Params *params)
{
const XR20M1170_HWAttrs *hwAttrs = handle->hwAttrs;
// TODO: Idea: have a function for setting registers to make sure everything
@@ -260,7 +262,8 @@ static bool register_config(UART_Handle handle, UART_Params *params) {
/* TODO: handle i2c failures better */
// Enable modifications to enhanced function registers and enable HW flow control (might as well)
// Enable modifications to enhanced function registers and enable HW flow
// control (might as well)
uint8_t bf = 0xBF; // TODO: hack - required to modify this register
if (!writeData(handle, XR_REG_LCR, &bf, 1)) {
return false;
@@ -289,8 +292,8 @@ static bool register_config(UART_Handle handle, UART_Params *params) {
// If the divisor is too big, introduce the prescaler
if (divisor > UINT16_MAX) {
prescaler = 4;
divisor = calc_divisor(hwAttrs->xtal1_freq, prescaler,
params->baudRate, samplingMode);
divisor = calc_divisor(hwAttrs->xtal1_freq, prescaler, params->baudRate,
samplingMode);
}
// Split the divisor into its integer and fractional parts
@@ -311,14 +314,14 @@ static bool register_config(UART_Handle handle, UART_Params *params) {
// Calculate data error rate
double realDivisor = (dld.fracDivisor / 16.0) + trunc(divisor);
double dataErrorRate = ((divisor - realDivisor)/divisor) * 100.0;
double dataErrorRate = ((divisor - realDivisor) / divisor) * 100.0;
if (dataErrorRate > 0.001) {
Log_warning2("XR20M1170: Data error rate of %d%% for baud rate %d",
dataErrorRate, params->baudRate);
}
// Set up LCR
lcr = (XrRegLcr) {
lcr = (XrRegLcr){
.wordLen = XR_WORD_LEN_MAP[params->dataLength],
.stopBits = XR_STOP_BIT_MAP[params->stopBits],
.parity = XR_PARITY_MAP[params->parityType],
@@ -334,7 +337,7 @@ static bool register_config(UART_Handle handle, UART_Params *params) {
.op1 = true, /* Select access to TCR from MSR */
.loopbackEn = false,
.clkPrescaler =
((prescaler > 1) ? XR_CLK_PRESCALER_4x : XR_CLK_PRESCALER_1x),
((prescaler > 1) ? XR_CLK_PRESCALER_4x : XR_CLK_PRESCALER_1x),
};
writeData(handle, XR_REG_MCR, &mcr, sizeof(mcr));
@@ -345,11 +348,11 @@ static bool register_config(UART_Handle handle, UART_Params *params) {
writeData(handle, XR_REG_FCR, &fcr, sizeof(fcr));
/* Set trigger levels - these override the levels set by FCR if nonzero */
XrRegTlr tlr = {
.rxTrigger = 32 / 4, /* 4-60, multiple of 4 */
.txTrigger = 32 / 4, /* 4-60, multiple of 4 */
};
writeData(handle, XR_REG_TLR, &tlr, sizeof(tlr));
XrRegTlr tlr = {
.rxTrigger = 32 / 4, /* 4-60, multiple of 4 */
.txTrigger = 32 / 4, /* 4-60, multiple of 4 */
};
writeData(handle, XR_REG_TLR, &tlr, sizeof(tlr));
/* Set halt/resume levels - these can be relatively low since data should
* normally be cleared quite quickly */
@@ -382,12 +385,13 @@ static bool register_config(UART_Handle handle, UART_Params *params) {
}
// XR20M1170_open
UART_Handle XR20M1170_open(UART_Handle handle, UART_Params *params) {
UART_Handle XR20M1170_open(UART_Handle handle, UART_Params *params)
{
XR20M1170_Object *object = handle->object;
const XR20M1170_HWAttrs *hwAttrs = handle->hwAttrs;
if (object->state.opened == true) {
//Log_warning1("UART:(%p) already in use.", hwAttrs->baseAddr);
// Log_warning1("UART:(%p) already in use.", hwAttrs->baseAddr);
return NULL;
}
@@ -429,8 +433,8 @@ UART_Handle XR20M1170_open(UART_Handle handle, UART_Params *params) {
DEBUG("XR20M1170:ERROR::Can't ring buffer mutex\n");
}
OcGpio_configure(hwAttrs->pin_irq, OCGPIO_CFG_INPUT |
OCGPIO_CFG_INT_FALLING);
OcGpio_configure(hwAttrs->pin_irq,
OCGPIO_CFG_INPUT | OCGPIO_CFG_INT_FALLING);
// Set up our threaded interrupt handler
ThreadedInt_Init(hwAttrs->pin_irq, processIrq, handle);
@@ -447,8 +451,8 @@ UART_Handle XR20M1170_open(UART_Handle handle, UART_Params *params) {
// object->state.readDataMode = params->readDataMode;
// object->state.writeDataMode = params->writeDataMode;
// object->state.readEcho = params->readEcho;
object->readTimeout = params->readTimeout;
object->writeTimeout = params->writeTimeout;
object->readTimeout = params->readTimeout;
object->writeTimeout = params->writeTimeout;
// object->readCallback = params->readCallback;
// object->writeCallback = params->writeCallback;
@@ -457,7 +461,8 @@ UART_Handle XR20M1170_open(UART_Handle handle, UART_Params *params) {
return (handle);
}
int XR20M1170_read(UART_Handle handle, void *buffer, size_t size) {
int XR20M1170_read(UART_Handle handle, void *buffer, size_t size)
{
XR20M1170_Object *object = handle->object;
uint8_t *char_buf = buffer;
@@ -483,11 +488,12 @@ int XR20M1170_read(UART_Handle handle, void *buffer, size_t size) {
return bytesRead;
}
int XR20M1170_write(UART_Handle handle, const void *buffer, size_t size) {
int XR20M1170_write(UART_Handle handle, const void *buffer, size_t size)
{
XR20M1170_Object *object = handle->object;
int bytes_written = 0;
while(size) {
while (size) {
if (!Semaphore_pend(object->writeSem, object->writeTimeout)) {
return bytes_written;
}
@@ -501,20 +507,24 @@ int XR20M1170_write(UART_Handle handle, const void *buffer, size_t size) {
return bytes_written;
}
int XR20M1170_readPolling(UART_Handle handle, void *buffer, size_t size) {
int XR20M1170_readPolling(UART_Handle handle, void *buffer, size_t size)
{
DEBUG("XR20M1170::readPolling not yet implemented");
return 0;
}
void XR20M1170_readCancel(UART_Handle handle) {
void XR20M1170_readCancel(UART_Handle handle)
{
DEBUG("XR20M1170::readCancel not yet implemented");
}
int XR20M1170_writePolling(UART_Handle handle, const void *buffer, size_t size) {
int XR20M1170_writePolling(UART_Handle handle, const void *buffer, size_t size)
{
DEBUG("XR20M1170::writePolling not yet implemented");
return 0;
}
void XR20M1170_writeCancel(UART_Handle handle) {
void XR20M1170_writeCancel(UART_Handle handle)
{
DEBUG("XR20M1170::writeCancel not yet implemented");
}

105
firmware/ec/src/devices/i2c/XR20M1170.h
View File

@@ -11,21 +11,21 @@
#pragma once
#ifndef XR20M1170_H_
#define XR20M1170_H_
# define XR20M1170_H_
#include "drivers/OcGpio.h"
# include "drivers/OcGpio.h"
#include <ti/drivers/I2C.h>
#include <ti/drivers/UART.h>
#include <ti/drivers/utils/RingBuf.h>
#include <ti/sysbios/gates/GateMutex.h>
#include <ti/sysbios/knl/Semaphore.h>
# include <ti/drivers/I2C.h>
# include <ti/drivers/UART.h>
# include <ti/drivers/utils/RingBuf.h>
# include <ti/sysbios/gates/GateMutex.h>
# include <ti/sysbios/knl/Semaphore.h>
#include <stdbool.h>
# include <stdbool.h>
typedef enum XR20M1170_FlowControl {
XR20M1170_FLOWCONTROL_TX = 0x01, // Enable auto CTS
XR20M1170_FLOWCONTROL_RX = 0x02, // Enable auto RTS
XR20M1170_FLOWCONTROL_TX = 0x01, // Enable auto CTS
XR20M1170_FLOWCONTROL_RX = 0x02, // Enable auto RTS
XR20M1170_FLOWCONTROL_NONE = 0x00,
} XR20M1170_FlowControl;
@@ -41,14 +41,14 @@ typedef struct XR20M1170_HWAttrs {
OcGpio_Pin *pin_irq; /*!< XR20M IRQ# pin */
/*! UART Peripheral's interrupt priority */
// TODO: might be able to do something with this
unsigned int intPriority;
unsigned int intPriority;
/*! Hardware flow control setting defined by driverlib */
XR20M1170_FlowControl flowControl;
/*! Pointer to a application ring buffer */
unsigned char *ringBufPtr;
unsigned char *ringBufPtr;
/*! Size of ringBufPtr */
size_t ringBufSize;
size_t ringBufSize;
} XR20M1170_HWAttrs;
/*!
@@ -59,63 +59,64 @@ typedef struct XR20M1170_HWAttrs {
typedef struct XR20M1170_Object {
/* UART state variable */
struct {
bool opened:1; /* Has the obj been opened */
UART_Mode readMode:1; /* Mode for all read calls */
UART_Mode writeMode:1; /* Mode for all write calls */
UART_DataMode readDataMode:1; /* Type of data being read */
UART_DataMode writeDataMode:1; /* Type of data being written */
UART_ReturnMode readReturnMode:1; /* Receive return mode */
UART_Echo readEcho:1; /* Echo received data back */
bool opened : 1; /* Has the obj been opened */
UART_Mode readMode : 1; /* Mode for all read calls */
UART_Mode writeMode : 1; /* Mode for all write calls */
UART_DataMode readDataMode : 1; /* Type of data being read */
UART_DataMode writeDataMode : 1; /* Type of data being written */
UART_ReturnMode readReturnMode : 1; /* Receive return mode */
UART_Echo readEcho : 1; /* Echo received data back */
/*
* Flag to determine if a timeout has occurred when the user called
* UART_read(). This flag is set by the timeoutClk clock object.
*/
bool bufTimeout:1;
bool bufTimeout : 1;
/*
* Flag to determine when an ISR needs to perform a callback; in both
* UART_MODE_BLOCKING or UART_MODE_CALLBACK
*/
bool callCallback:1;
bool callCallback : 1;
/*
* Flag to determine if the ISR is in control draining the ring buffer
* when in UART_MODE_CALLBACK
*/
bool drainByISR:1;
bool drainByISR : 1;
/* Flag to keep the state of the read ring buffer */
bool rxEnabled:1;
bool rxEnabled : 1;
} state;
I2C_Handle i2cHandle;
// TODO: these are from UART_Tiva - need to revise the struct members
// Clock_Struct timeoutClk; /* Clock object to for timeouts */
// uint32_t baudRate; /* Baud rate for UART */
// UART_LEN dataLength; /* Data length for UART */
// UART_STOP stopBits; /* Stop bits for UART */
// UART_PAR parityType; /* Parity bit type for UART */
//
// /* UART read variables */
RingBuf_Object ringBuffer; /* local circular buffer object */
GateMutex_Handle ringBufMutex; // Mutex for accessing ring buffer
// /* A complement pair of read functions for both the ISR and UART_read() */
// UARTTiva_FxnSet readFxns;
// unsigned char *readBuf; /* Buffer data pointer */
// size_t readSize; /* Desired number of bytes to read */
// size_t readCount; /* Number of bytes left to read */
// TODO: these are from UART_Tiva - need to revise the struct members
// Clock_Struct timeoutClk; /* Clock object to for timeouts
// */ uint32_t baudRate; /* Baud rate for UART */
// UART_LEN dataLength; /* Data length for UART */
// UART_STOP stopBits; /* Stop bits for UART */
// UART_PAR parityType; /* Parity bit type for UART */
//
// /* UART read variables */
RingBuf_Object ringBuffer; /* local circular buffer object */
GateMutex_Handle ringBufMutex; // Mutex for accessing ring buffer
// /* A complement pair of read functions for both the ISR and
// UART_read() */ UARTTiva_FxnSet readFxns; unsigned char *readBuf;
// /* Buffer data pointer */ size_t readSize; /*
// Desired number of bytes to read */ size_t readCount; /*
// Number of bytes left to read */
Semaphore_Handle readSem; /* UART read semaphore */
unsigned int readTimeout; /* Timeout for read semaphore */
// UART_Callback readCallback; /* Pointer to read callback */
//
// /* UART write variables */
// const unsigned char *writeBuf; /* Buffer data pointer */
// size_t writeSize; /* Desired number of bytes to write*/
// size_t writeCount; /* Number of bytes left to write */
Semaphore_Handle writeSem; /* UART write semaphore*/
unsigned int writeTimeout; /* Timeout for write semaphore */
// UART_Callback writeCallback; /* Pointer to write callback */
//
// ti_sysbios_family_arm_m3_Hwi_Struct hwi; /* Hwi object */
Semaphore_Handle readSem; /* UART read semaphore */
unsigned int readTimeout; /* Timeout for read semaphore */
// UART_Callback readCallback; /* Pointer to read callback */
//
// /* UART write variables */
// const unsigned char *writeBuf; /* Buffer data pointer */
// size_t writeSize; /* Desired number of bytes to
// write*/ size_t writeCount; /* Number of bytes left
// to write */
Semaphore_Handle writeSem; /* UART write semaphore*/
unsigned int writeTimeout; /* Timeout for write semaphore */
// UART_Callback writeCallback; /* Pointer to write callback */
//
// ti_sysbios_family_arm_m3_Hwi_Struct hwi; /* Hwi object */
} XR20M1170_Object, *XR20M1170_Handle;
#endif

179
firmware/ec/src/devices/i2c/XR20M1170_Registers.h
View File

@@ -15,12 +15,12 @@
#pragma once
#ifndef XR20M1170_REGISTERS_H_
#define XR20M1170_REGISTERS_H_
# define XR20M1170_REGISTERS_H_
#include <stdbool.h>
#include <stdint.h>
# include <stdbool.h>
# include <stdint.h>
#include "helpers/attribute.h"
# include "helpers/attribute.h"
typedef enum XrRegister {
XR_REG_RHR = 0x00, // LCR[7] = 0 (read only)
@@ -45,17 +45,17 @@ typedef enum XrRegister {
XR_REG_TCR = 0x06, /* EFR[4] == 1 && MCR[2] == 1 */
XR_REG_TLR = 0x07, /* EFR[4] == 1 && MCR[2] == 1 */
XR_REG_TXLVL = 0x08, // LCR[7] = 0
XR_REG_RXLVL = 0x09, // LCR[7] = 0
XR_REG_IODIR = 0x0A, // LCR[7] = 0
XR_REG_IOSTATE = 0x0B, // LCR[7] = 0
XR_REG_TXLVL = 0x08, // LCR[7] = 0
XR_REG_RXLVL = 0x09, // LCR[7] = 0
XR_REG_IODIR = 0x0A, // LCR[7] = 0
XR_REG_IOSTATE = 0x0B, // LCR[7] = 0
XR_REG_IOINTENA = 0x0C, // LCR[7] = 0
XR_REG_IOCTRL = 0x0E, // LCR[7] = 0
XR_REG_EFCR = 0x0F, // LCR[7] = 0
XR_REG_IOCTRL = 0x0E, // LCR[7] = 0
XR_REG_EFCR = 0x0F, // LCR[7] = 0
XR_REG_EFR = 0x02, // LCR = 0xBF
XR_REG_XON1 = 0x04, // LCR = 0xBF
XR_REG_XON2 = 0x05, // LCR = 0xBF
XR_REG_EFR = 0x02, // LCR = 0xBF
XR_REG_XON1 = 0x04, // LCR = 0xBF
XR_REG_XON2 = 0x05, // LCR = 0xBF
XR_REG_XOFF1 = 0x06, // LCR = 0xBF
XR_REG_XOFF2 = 0x07, // LCR = 0xBF
} XrRegister;
@@ -78,10 +78,10 @@ typedef enum XrChannel {
typedef struct PACKED XrSubAddress {
union PACKED {
struct PACKED {
uint8_t reserve1:1;
XrChannel channel:2;
uint8_t reg:4;
uint8_t reserve2:1;
uint8_t reserve1 : 1;
XrChannel channel : 2;
uint8_t reg : 4;
uint8_t reserve2 : 1;
};
uint8_t byte;
};
@@ -91,47 +91,47 @@ typedef uint8_t XrRegTxlvl;
typedef uint8_t XrRegRxlvl;
typedef enum XrWordLen {
XR_WORD_LEN_5 = 0x0, //!< Data length is 5 bits
XR_WORD_LEN_6 = 0x1, //!< Data length is 6 bits
XR_WORD_LEN_7 = 0x2, //!< Data length is 7 bits
XR_WORD_LEN_8 = 0x3, //!< Data length is 8 bits
XR_WORD_LEN_5 = 0x0, //!< Data length is 5 bits
XR_WORD_LEN_6 = 0x1, //!< Data length is 6 bits
XR_WORD_LEN_7 = 0x2, //!< Data length is 7 bits
XR_WORD_LEN_8 = 0x3, //!< Data length is 8 bits
} XrWordLen;
typedef enum XrStopBit {
XR_STOP_BIT_ONE = 0x0, //!< One stop bit
XR_STOP_BIT_TWO = 0x1, //!< Two stop bits
XR_STOP_BIT_ONE = 0x0, //!< One stop bit
XR_STOP_BIT_TWO = 0x1, //!< Two stop bits
} XrStopBit;
typedef enum XrParity {
XR_PARITY_NONE = 0x0, //!< No parity
XR_PARITY_ODD = 0x1, //!< Parity bit is odd
XR_PARITY_EVEN = 0x3, //!< Parity bit is even
XR_PARITY_ONE = 0x5, //!< Parity bit is always one
XR_PARITY_ZERO = 0x7, //!< Parity bit is always zero
XR_PARITY_NONE = 0x0, //!< No parity
XR_PARITY_ODD = 0x1, //!< Parity bit is odd
XR_PARITY_EVEN = 0x3, //!< Parity bit is even
XR_PARITY_ONE = 0x5, //!< Parity bit is always one
XR_PARITY_ZERO = 0x7, //!< Parity bit is always zero
} XrParity;
// TODO: a lot of these should be enums
typedef struct PACKED XrRegLcr {
XrWordLen wordLen:2; // Word length to be transmitted or received
XrStopBit stopBits:1; // Length of stop bit
XrParity parity:3; // Parity format
bool txBreak:1; // Causes a break condition to be transmitted
bool divisorEn:1; // Baud rate generator divisor (DLL, DLM and DLD)
XrWordLen wordLen : 2; // Word length to be transmitted or received
XrStopBit stopBits : 1; // Length of stop bit
XrParity parity : 3; // Parity format
bool txBreak : 1; // Causes a break condition to be transmitted
bool divisorEn : 1; // Baud rate generator divisor (DLL, DLM and DLD)
} XrRegLcr;
typedef struct PACKED XrRegDld {
uint8_t fracDivisor:4;
bool mode8x:1;
bool mode4x:1;
uint8_t reserved:2;
uint8_t fracDivisor : 4;
bool mode8x : 1;
bool mode4x : 1;
uint8_t reserved : 2;
} XrRegDld;
typedef struct PACKED XrRegEfr {
uint8_t swFlowCtl:4;
bool enhancedFunc:1;
bool specialCharDetect:1;
bool autoRts:1;
bool autoCts:1;
uint8_t swFlowCtl : 4;
bool enhancedFunc : 1;
bool specialCharDetect : 1;
bool autoRts : 1;
bool autoCts : 1;
} XrRegEfr;
typedef uint8_t XrRegDlm;
@@ -143,69 +143,69 @@ typedef enum XrClkPrescaler {
} XrClkPrescaler;
typedef struct PACKED XrRegMcr {
bool dtr:1;
bool rts:1;
bool op1:1;
bool op2:1;
bool loopbackEn:1;
bool xonAnyEn:1;
bool irModeEn:1;
XrClkPrescaler clkPrescaler:1;
bool dtr : 1;
bool rts : 1;
bool op1 : 1;
bool op2 : 1;
bool loopbackEn : 1;
bool xonAnyEn : 1;
bool irModeEn : 1;
XrClkPrescaler clkPrescaler : 1;
} XrRegMcr;
typedef enum RxTriggerLevel {
RX_TRIGGER_LEVEL_8 = 0x00,
RX_TRIGGER_LEVEL_8 = 0x00,
RX_TRIGGER_LEVEL_16 = 0x01,
RX_TRIGGER_LEVEL_56 = 0x02,
RX_TRIGGER_LEVEL_60 = 0x03,
} RxTriggerLevel;
typedef enum TxTriggerLevel {
TX_TRIGGER_LEVEL_8 = 0x00,
TX_TRIGGER_LEVEL_8 = 0x00,
TX_TRIGGER_LEVEL_16 = 0x01,
TX_TRIGGER_LEVEL_32 = 0x02,
TX_TRIGGER_LEVEL_56 = 0x03,
} TxTriggerLevel;
typedef struct PACKED XrRegFcr {
bool fifoEn:1;
bool rxRst:1;
bool txRst:1;
bool reserved:1;
TxTriggerLevel txTrigger:2; /*!< Overwridden if TLR value set */
RxTriggerLevel rxTrigger:2; /*!< Overwridden if TLR value set */
bool fifoEn : 1;
bool rxRst : 1;
bool txRst : 1;
bool reserved : 1;
TxTriggerLevel txTrigger : 2; /*!< Overwridden if TLR value set */
RxTriggerLevel rxTrigger : 2; /*!< Overwridden if TLR value set */
} XrRegFcr;
/* Transmission Control Register (TCR) */
typedef struct PACKED XrRegTcr {
uint8_t rxHaltLvl:4; /*!< x4, 0-60 - RTS goes high after this level */
uint8_t rxResumeLvl:4; /*!< x4, 0-60 - RTS returns low below this level */
uint8_t rxHaltLvl : 4; /*!< x4, 0-60 - RTS goes high after this level */
uint8_t rxResumeLvl : 4; /*!< x4, 0-60 - RTS returns low below this level */
} XrRegTcr;
/* Trigger Level Register (TLR) */
typedef struct PACKED XrRegTlr {
uint8_t txTrigger:4; /*!< x4, 4-60, If 0 (default), FCR value used */
uint8_t rxTrigger:4; /*!< x4, 4-60, If 0 (default), FCR value used */
uint8_t txTrigger : 4; /*!< x4, 4-60, If 0 (default), FCR value used */
uint8_t rxTrigger : 4; /*!< x4, 4-60, If 0 (default), FCR value used */
} XrRegTlr;
typedef struct PACKED XrRegIOCtrl {
bool ioLatch:1;
bool modemIf:1;
uint8_t res1:1;
bool uartReset:1;
uint8_t res2:4;
bool ioLatch : 1;
bool modemIf : 1;
uint8_t res1 : 1;
bool uartReset : 1;
uint8_t res2 : 4;
} XrRegIOCtrl;
// LCR[7] = 0
typedef struct PACKED XrRegIer {
bool rhrIntEn:1;
bool thrIntEn:1;
bool lsrIntEn:1;
bool msrIntEn:1;
bool sleepModeEn:1; //!< EFR[4] = 1 to modify
bool xoffIntEn:1; //!< EFR[4] = 1 to modify
bool rtsIntEn:1; //!< EFR[4] = 1 to modify
bool ctsIntEn:1; //!< EFR[4] = 1 to modify
bool rhrIntEn : 1;
bool thrIntEn : 1;
bool lsrIntEn : 1;
bool msrIntEn : 1;
bool sleepModeEn : 1; //!< EFR[4] = 1 to modify
bool xoffIntEn : 1; //!< EFR[4] = 1 to modify
bool rtsIntEn : 1; //!< EFR[4] = 1 to modify
bool ctsIntEn : 1; //!< EFR[4] = 1 to modify
} XrRegIer;
// Note: in order of priority
@@ -223,31 +223,32 @@ typedef enum ISR_SRC {
} ISR_SRC;
typedef struct PACKED XrRegIsr {
ISR_SRC source:6;
uint8_t fifo_en:2; // TODO: not sure why there's 2...datasheet doesn't elaborate - possibly TX vs RX, but it doesn't say
ISR_SRC source : 6;
uint8_t fifo_en : 2; // TODO: not sure why there's 2...datasheet doesn't
// elaborate - possibly TX vs RX, but it doesn't say
} XrRegIsr;
// General struct for configuring gpio pins
typedef struct PACKED XrGpioPins {
union {
struct PACKED {
bool p0:1;
bool p2:1;
bool p3:1;
bool p0 : 1;
bool p2 : 1;
bool p3 : 1;
bool p4:1;
bool p5:1;
bool p6:1;
bool p7:1;
bool p4 : 1;
bool p5 : 1;
bool p6 : 1;
bool p7 : 1;
} gpio;
struct PACKED {
char res:4;
char res : 4;
bool dsr:1;
bool dtr:1;
bool cd:1;
bool ri:1;
bool dsr : 1;
bool dtr : 1;
bool cd : 1;
bool ri : 1;
} modem;
};
} XrGpioPins;

22
firmware/ec/src/devices/i2c/threaded_int.c
View File

@@ -16,8 +16,8 @@
#include <ti/sysbios/knl/Task.h>
// Threaded interrupt info
#define TI_TASKSTACKSIZE 1024
#define TI_TASKPRIORITY 6
#define TI_TASKSTACKSIZE 1024
#define TI_TASKPRIORITY 6
// This number is fairly superficial - just used to keep track of the
// various tasks, it can be increased without much overhead
@@ -25,14 +25,15 @@
// Config simply to map context to our GPIO interrupts
typedef struct InterruptConfig {
Semaphore_Handle sem; //!< Semaphore to wake up INT thread
ThreadedInt_Callback cb; //!< Callback to run when interrupt occurs
void *context; //!< Pointer to pass to cb function
Semaphore_Handle sem; //!< Semaphore to wake up INT thread
ThreadedInt_Callback cb; //!< Callback to run when interrupt occurs
void *context; //!< Pointer to pass to cb function
} InterruptConfig;
static InterruptConfig s_intConfigs[MAX_DEVICES] = {};
static int s_numDevices = 0;
static void gpioIntFxn(const OcGpio_Pin *pin, void *context) {
static void gpioIntFxn(const OcGpio_Pin *pin, void *context)
{
Semaphore_Handle sem = context;
// TODO: this should probably be an assert
@@ -44,7 +45,8 @@ static void gpioIntFxn(const OcGpio_Pin *pin, void *context) {
Semaphore_post(sem);
}
static void ThreadedInt_Task(UArg arg0, UArg arg1) {
static void ThreadedInt_Task(UArg arg0, UArg arg1)
{
InterruptConfig *cfg = (InterruptConfig *)arg0;
if (!cfg) {
DEBUG("Threaded Int started without configuration???\n");
@@ -60,7 +62,8 @@ static void ThreadedInt_Task(UArg arg0, UArg arg1) {
// TODO: this function isn't thread safe at the moment
void ThreadedInt_Init(OcGpio_Pin *irqPin, ThreadedInt_Callback cb,
void *context) {
void *context)
{
// Build up table of all devices for interrupt handling. This is an ok
// workaround for TI RTOS GPIO interrupts for now (only using one device)
if (s_numDevices >= MAX_DEVICES) {
@@ -75,7 +78,7 @@ void ThreadedInt_Init(OcGpio_Pin *irqPin, ThreadedInt_Callback cb,
return;
}
s_intConfigs[devNum] = (InterruptConfig) {
s_intConfigs[devNum] = (InterruptConfig){
.sem = sem,
.cb = cb,
.context = context,
@@ -103,4 +106,3 @@ void ThreadedInt_Init(OcGpio_Pin *irqPin, ThreadedInt_Callback cb,
OcGpio_setCallback(irqPin, gpioIntFxn, sem);
OcGpio_enableInt(irqPin);
}

4
firmware/ec/src/devices/i2c/threaded_int.h
View File

@@ -10,9 +10,9 @@
#pragma once
#ifndef DEVICES_I2C_THREADED_INT_H_
#define DEVICES_I2C_THREADED_INT_H_
# define DEVICES_I2C_THREADED_INT_H_
#include "drivers/OcGpio.h"
# include "drivers/OcGpio.h"
typedef void (*ThreadedInt_Callback)(void *context);

38
firmware/ec/src/devices/i2cbus.c
View File

@@ -67,7 +67,7 @@ I2C_Handle i2c_open_bus(unsigned int index)
** RETURN TYPE : None
**
*****************************************************************************/
void i2c_close_bus(I2C_Handle* i2cHandle)
void i2c_close_bus(I2C_Handle *i2cHandle)
{
I2C_close(*i2cHandle);
i2cHandle = NULL;
@@ -83,29 +83,29 @@ void i2c_close_bus(I2C_Handle* i2cHandle)
** RETURN TYPE : Success or failure
**
*****************************************************************************/
ReturnStatus i2c_reg_write( I2C_Handle i2cHandle,
uint8_t deviceAddress,
uint8_t regAddress,
uint16_t value,
uint8_t numofBytes)
ReturnStatus i2c_reg_write(I2C_Handle i2cHandle, uint8_t deviceAddress,
uint8_t regAddress, uint16_t value,
uint8_t numofBytes)
{
ReturnStatus status = RETURN_OK;
uint8_t txBuffer[3];
I2C_Transaction i2cTransaction;
txBuffer[0] = regAddress;
memcpy(&txBuffer[1],&value,numofBytes);
memcpy(&txBuffer[1], &value, numofBytes);
i2cTransaction.slaveAddress = deviceAddress;
i2cTransaction.writeBuf = txBuffer;
i2cTransaction.writeCount = numofBytes + 1;
i2cTransaction.readBuf = NULL;
i2cTransaction.readCount = 0;
if (I2C_transfer(i2cHandle, &i2cTransaction)) {
//LOGGER_DEBUG("I2CBUS:INFO:: I2C write success for device: 0x%x reg Addr: 0x%x value: 0x%x.\n",
// LOGGER_DEBUG("I2CBUS:INFO:: I2C write success for device: 0x%x reg
// Addr: 0x%x value: 0x%x.\n",
// deviceAddress, regAddress, value);
status = RETURN_OK;
} else {
LOGGER_ERROR("I2CBUS:ERROR:: I2C write failed for for device: 0x%x reg Addr: 0x%x value: 0x%x.\n",
deviceAddress, regAddress, value);
LOGGER_ERROR(
"I2CBUS:ERROR:: I2C write failed for for device: 0x%x reg Addr: 0x%x value: 0x%x.\n",
deviceAddress, regAddress, value);
status = RETURN_NOTOK;
}
return status;
@@ -121,11 +121,9 @@ ReturnStatus i2c_reg_write( I2C_Handle i2cHandle,
** RETURN TYPE : Success or failure
**
*****************************************************************************/
ReturnStatus i2c_reg_read( I2C_Handle i2cHandle,
uint8_t deviceAddress,
uint8_t regAddress,
uint16_t *value,
uint8_t numofBytes)
ReturnStatus i2c_reg_read(I2C_Handle i2cHandle, uint8_t deviceAddress,
uint8_t regAddress, uint16_t *value,
uint8_t numofBytes)
{
ReturnStatus status = RETURN_OK;
uint8_t txBuffer[1] = { 0 };
@@ -138,13 +136,15 @@ ReturnStatus i2c_reg_read( I2C_Handle i2cHandle,
i2cTransaction.readBuf = rxBuffer;
i2cTransaction.readCount = numofBytes;
if (I2C_transfer(i2cHandle, &i2cTransaction)) {
memcpy(value,rxBuffer,numofBytes);
//LOGGER_DEBUG("I2CBUS:INFO:: I2C read success for device: 0x%x reg Addr: 0x%x value : 0x%x.\n",
memcpy(value, rxBuffer, numofBytes);
// LOGGER_DEBUG("I2CBUS:INFO:: I2C read success for device: 0x%x reg
// Addr: 0x%x value : 0x%x.\n",
// deviceAddress, regAddress, *value);
status = RETURN_OK;
} else {
LOGGER_ERROR("I2CBUS:ERROR:: I2C read failed for for device: 0x%x reg Addr: 0x%x.\n",
deviceAddress, regAddress);
LOGGER_ERROR(
"I2CBUS:ERROR:: I2C read failed for for device: 0x%x reg Addr: 0x%x.\n",
deviceAddress, regAddress);
status = RETURN_NOTOK;
}
return status;

108
firmware/ec/src/devices/ina226.c
View File

@@ -20,21 +20,21 @@
/*****************************************************************************
* REGISTER DEFINITIONS
*****************************************************************************/
#define INA_CONFIGURATION_REG 0x00
#define INA_SHUNTVOLTAGE_REG 0x01
#define INA_BUSVOLTAGE_REG 0x02
#define INA_POWER_REG 0x03
#define INA_CURRENT_REG 0x04
#define INA_CALIBRATION_REG 0x05
#define INA_MASKENABLE_REG 0x06
#define INA_ALERTLIMIT_REG 0x07
#define INA_MANUFACTUREID_REG 0xFE
#define INA_DIEID_REG 0xFF
#define INA_CONFIGURATION_REG 0x00
#define INA_SHUNTVOLTAGE_REG 0x01
#define INA_BUSVOLTAGE_REG 0x02
#define INA_POWER_REG 0x03
#define INA_CURRENT_REG 0x04
#define INA_CALIBRATION_REG 0x05
#define INA_MASKENABLE_REG 0x06
#define INA_ALERTLIMIT_REG 0x07
#define INA_MANUFACTUREID_REG 0xFE
#define INA_DIEID_REG 0xFF
/*INA226 Device Info */
#define INA226_MANFACTURE_ID 0x5449
#define INA226_DEVICE_ID 0x2260
#define INA226_DEV_VERSION 0x00
#define INA226_MANFACTURE_ID 0x5449
#define INA226_DEVICE_ID 0x2260
#define INA226_DEV_VERSION 0x00
/* Configuration Register Bits */
#define INA_CFG_RESET (1 << 15)
@@ -47,33 +47,35 @@
* Calculate Shunt Voltage Alert Limit Register Value
* ui16rfINARegValue = (ui16rfINARegValue * 2048)/INA226_CALIBRATION_REG_VALUE;
*/
#define CURRENT_TO_REG(x) ((2048 *(x/INA226_CURRENT_LSB)/INA226_CAL_REG_VALUE))
#define REG_TO_CURRENT(y) ((y * INA226_CURRENT_LSB * INA226_CAL_REG_VALUE)/2048)
#define CURRENT_TO_REG(x) \
((2048 * (x / INA226_CURRENT_LSB) / INA226_CAL_REG_VALUE))
#define REG_TO_CURRENT(y) \
((y * INA226_CURRENT_LSB * INA226_CAL_REG_VALUE) / 2048)
/*****************************************************************************
* CONSTANTS DEFINITIONS
*****************************************************************************/
/* INA226 LSB Values */
#define INA226_VSHUNT_LSB 2.5 /* 2.5uV or 2500nV (uV default) */
#define INA226_VBUS_LSB 1.25 /* 1.25mV or 1250uV (mV default) */
#define INA226_CURRENT_LSB 0.1 /* 0.100mA 0r 100uA (mA default) */
#define INA226_POWER_LSB 2.5 /* 2.5mW or 2500uW (mW default) */
#define INA226_VSHUNT_LSB 2.5 /* 2.5uV or 2500nV (uV default) */
#define INA226_VBUS_LSB 1.25 /* 1.25mV or 1250uV (mV default) */
#define INA226_CURRENT_LSB 0.1 /* 0.100mA 0r 100uA (mA default) */
#define INA226_POWER_LSB 2.5 /* 2.5mW or 2500uW (mW default) */
/* Configure the Configuration register with Number of Samples and Conversion
* Time for Shunt and Bus Voltage.
* Min(Default):0x4127; Max: 0x4FFF; Average: 0x476F
*/
#define INA226_CONFIG_REG_VALUE 0x476F
#define INA226_CONFIG_REG_VALUE 0x476F
/* Configure Calibration register with shunt resistor value and current LSB.
Current_LSB = Maximum Expected Current/2^15
Current_LSB = 2A/2^15 = 0.00006103515625 = 61uA ~ 100uA(Maximum Expected Current = 2A)
Calibration Register(CAL) = 0.00512/(Current_LSB*RSHUNT)
CAL = 0.00512/(100uA*2mOhm) = = 25600 = 0x6400.(RSHUNT = 2mohm)
Current_LSB = 2A/2^15 = 0.00006103515625 = 61uA ~ 100uA(Maximum Expected
Current = 2A) Calibration Register(CAL) = 0.00512/(Current_LSB*RSHUNT) CAL =
0.00512/(100uA*2mOhm) = = 25600 = 0x6400.(RSHUNT = 2mohm)
*/
#define INA226_CAL_REG_VALUE 0x6400
#define INA226_CAL_REG_VALUE 0x6400
#define INA226_MASKEN_REG_VALUE 0x8001
#define INA226_MASKEN_REG_VALUE 0x8001
/*****************************************************************************
** FUNCTION NAME : read_ina_reg
@@ -86,16 +88,15 @@
** RETURN TYPE : Success or failure
**
*****************************************************************************/
static ReturnStatus read_ina_reg(const INA226_Dev *dev,
uint8_t regAddress,
static ReturnStatus read_ina_reg(const INA226_Dev *dev, uint8_t regAddress,
uint16_t *regValue)
{
ReturnStatus status = RETURN_NOTOK;
I2C_Handle inaHandle = i2c_get_handle(dev->cfg.dev.bus);
if (!inaHandle) {
LOGGER_ERROR("INASENSOR:ERROR:: Failed to get I2C Bus for INA sensor "
"0x%x on bus 0x%x.\n", dev->cfg.dev.slave_addr,
dev->cfg.dev.bus);
"0x%x on bus 0x%x.\n",
dev->cfg.dev.slave_addr, dev->cfg.dev.bus);
} else {
status = i2c_reg_read(inaHandle, dev->cfg.dev.slave_addr, regAddress,
regValue, 2);
@@ -115,16 +116,15 @@ static ReturnStatus read_ina_reg(const INA226_Dev *dev,
** RETURN TYPE : Success or failure
**
*****************************************************************************/
static ReturnStatus write_ina_reg(const INA226_Dev *dev,
uint8_t regAddress,
static ReturnStatus write_ina_reg(const INA226_Dev *dev, uint8_t regAddress,
uint16_t regValue)
{
ReturnStatus status = RETURN_NOTOK;
I2C_Handle inaHandle = i2c_get_handle(dev->cfg.dev.bus);
if (!inaHandle) {
LOGGER_ERROR("INASENSOR:ERROR:: Failed to get I2C Bus for INA sensor "
"0x%x on bus 0x%x.\n", dev->cfg.dev.slave_addr,
dev->cfg.dev.bus);
"0x%x on bus 0x%x.\n",
dev->cfg.dev.slave_addr, dev->cfg.dev.bus);
} else {
regValue = htobe16(regValue);
status = i2c_reg_write(inaHandle, dev->cfg.dev.slave_addr, regAddress,
@@ -204,7 +204,7 @@ static ReturnStatus _set_cal_reg(INA226_Dev *dev, uint16_t regValue)
** RETURN TYPE : Success or failure
**
*****************************************************************************/
ReturnStatus ina226_readCurrentLim(INA226_Dev *dev, uint16_t* currLimit)
ReturnStatus ina226_readCurrentLim(INA226_Dev *dev, uint16_t *currLimit)
{
uint16_t regValue = 0x0000;
ReturnStatus status = read_ina_reg(dev, INA_ALERTLIMIT_REG, &regValue);
@@ -243,7 +243,7 @@ ReturnStatus ina226_setCurrentLim(INA226_Dev *dev, uint16_t currLimit)
** RETURN TYPE : Success or failure
**
*****************************************************************************/
static ReturnStatus _read_alert_reg(INA226_Dev *dev, uint16_t* regValue)
static ReturnStatus _read_alert_reg(INA226_Dev *dev, uint16_t *regValue)
{
return read_ina_reg(dev, INA_MASKENABLE_REG, regValue);
}
@@ -273,8 +273,7 @@ static ReturnStatus _enable_alert(INA226_Dev *dev, uint16_t regValue)
** RETURN TYPE : Success or failure
**
*****************************************************************************/
ReturnStatus ina226_readBusVoltage(INA226_Dev *dev,
uint16_t* busVoltValue)
ReturnStatus ina226_readBusVoltage(INA226_Dev *dev, uint16_t *busVoltValue)
{
uint16_t regValue;
ReturnStatus status = read_ina_reg(dev, INA_BUSVOLTAGE_REG, &regValue);
@@ -298,8 +297,7 @@ ReturnStatus ina226_readBusVoltage(INA226_Dev *dev,
** RETURN TYPE : Success or failure
**
*****************************************************************************/
ReturnStatus ina226_readShuntVoltage(INA226_Dev *dev,
uint16_t* shuntVoltValue)
ReturnStatus ina226_readShuntVoltage(INA226_Dev *dev, uint16_t *shuntVoltValue)
{
uint16_t regValue;
ReturnStatus status = read_ina_reg(dev, INA_SHUNTVOLTAGE_REG, &regValue);
@@ -308,7 +306,8 @@ ReturnStatus ina226_readShuntVoltage(INA226_Dev *dev,
*shuntVoltValue = regValue * INA226_VSHUNT_LSB;
LOGGER_DEBUG("INASENSOR:INFO:: INA sensor 0x%x on bus 0x%x is "
"reporting shunt voltage value of %d uV.\n",
dev->cfg.dev.slave_addr, dev->cfg.dev.bus, *shuntVoltValue);
dev->cfg.dev.slave_addr, dev->cfg.dev.bus,
*shuntVoltValue);
}
return status;
}
@@ -323,7 +322,7 @@ ReturnStatus ina226_readShuntVoltage(INA226_Dev *dev,
** RETURN TYPE : Success or failure
**
*****************************************************************************/
ReturnStatus ina226_readCurrent(INA226_Dev *dev, uint16_t* currValue)
ReturnStatus ina226_readCurrent(INA226_Dev *dev, uint16_t *currValue)
{
uint16_t regValue;
ReturnStatus status = read_ina_reg(dev, INA_CURRENT_REG, &regValue);
@@ -347,7 +346,7 @@ ReturnStatus ina226_readCurrent(INA226_Dev *dev, uint16_t* currValue)
** RETURN TYPE : Success or failure
**
*****************************************************************************/
ReturnStatus ina226_readPower(INA226_Dev *dev, uint16_t* powValue)
ReturnStatus ina226_readPower(INA226_Dev *dev, uint16_t *powValue)
{
uint16_t regValue;
ReturnStatus status = read_ina_reg(dev, INA_POWER_REG, &regValue);
@@ -363,7 +362,8 @@ ReturnStatus ina226_readPower(INA226_Dev *dev, uint16_t* powValue)
/*****************************************************************************
* Internal IRQ handler - reads in triggered interrupts and dispatches CBs
*****************************************************************************/
static void _ina226_isr(void *context) {
static void _ina226_isr(void *context)
{
INA226_Dev *dev = context;
/* Read the alert mask register (will clear the alert bit if set) */
@@ -404,7 +404,7 @@ static void _ina226_isr(void *context) {
if (alert_mask & INA_MSK_SOL) {
if (dev->obj.evt_to_monitor == INA226_EVT_COL ||
dev->obj.evt_to_monitor == INA226_EVT_CUL) {
dev->obj.evt_to_monitor == INA226_EVT_CUL) {
if (ina226_readCurrent(dev, &value) != RETURN_OK) {
value = UINT16_MAX;
}
@@ -419,7 +419,7 @@ static void _ina226_isr(void *context) {
new_mask |= INA_MSK_SUL;
} else if (alert_mask & INA_MSK_SUL) {
if (dev->obj.evt_to_monitor == INA226_EVT_CUL ||
dev->obj.evt_to_monitor == INA226_EVT_COL) {
dev->obj.evt_to_monitor == INA226_EVT_COL) {
if (ina226_readCurrent(dev, &value) != RETURN_OK) {
value = UINT16_MAX;
}
@@ -502,13 +502,14 @@ ReturnStatus ina226_init(INA226_Dev *dev)
}
/* Make sure we're talking to the right device */
// if (ina226_probe(dev) != POST_DEV_FOUND) {
// return RETURN_NOTOK;
// }
// if (ina226_probe(dev) != POST_DEV_FOUND) {
// return RETURN_NOTOK;
// }
if (dev->cfg.pin_alert) {
const uint32_t pin_evt_cfg = OCGPIO_CFG_INPUT | OCGPIO_CFG_INT_FALLING;
if (OcGpio_configure(dev->cfg.pin_alert, pin_evt_cfg) < OCGPIO_SUCCESS) {
if (OcGpio_configure(dev->cfg.pin_alert, pin_evt_cfg) <
OCGPIO_SUCCESS) {
return RETURN_NOTOK;
}
@@ -521,7 +522,8 @@ ReturnStatus ina226_init(INA226_Dev *dev)
/*****************************************************************************
*****************************************************************************/
void ina226_setAlertHandler(INA226_Dev *dev, INA226_CallbackFn alert_cb,
void *cb_context) {
void *cb_context)
{
dev->obj.alert_cb = alert_cb;
dev->obj.cb_context = cb_context;
}
@@ -541,7 +543,8 @@ ReturnStatus ina226_enableAlert(INA226_Dev *dev, INA226_Event evt)
}
alert_mask &= (~INA_ALERT_EN_MASK); /* Wipe out previous alert EN bits */
//alert_mask |= (INA_MSK_LEN); /* Enable latch mode (never miss an alert) */
// alert_mask |= (INA_MSK_LEN); /* Enable latch mode (never miss an alert)
// */
dev->obj.evt_to_monitor = evt;
switch (evt) {
case INA226_EVT_COL:
@@ -575,6 +578,7 @@ ePostCode ina226_probe(INA226_Dev *dev, POSTData *postData)
if (manfId != INA226_MANFACTURE_ID) {
return POST_DEV_ID_MISMATCH;
}
post_update_POSTData(postData, dev->cfg.dev.bus, dev->cfg.dev.slave_addr,manfId, devId);
post_update_POSTData(postData, dev->cfg.dev.bus, dev->cfg.dev.slave_addr,
manfId, devId);
return POST_DEV_FOUND;
}

273
firmware/ec/src/devices/led.c
View File

@@ -47,8 +47,9 @@
*/
/* LED arrangements
Left: D8 => D17 => D18 => D19 => D20 => D21 => D22 ( From Left Bottom to Top Centre)
Right: D23 => D31 => D24 => D25 => D26 => D27 => D28 ( From Top centre to Right Bottom)
Left: D8 => D17 => D18 => D19 => D20 => D21 => D22 ( From Left Bottom to Top
Centre) Right: D23 => D31 => D24 => D25 => D26 => D27 => D28 ( From Top centre
to Right Bottom)
Green from D8 to D28:
Left: IO5 => IO3 => IO13 => IO1 => IO7 => IO9 => IO11
@@ -63,106 +64,118 @@
IO14 & IO15 = 1(Not connected IOs; Reg Data should be 11xxxxxx).
*/
static const hciLedData ledData[HCI_LED_TOTAL_NOS] = {
[HCI_LED_1] = {
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_5, // IO5
.ledRed = ~SX1509_IO_PIN_4, // IO4
.ledOff = SX1509_IO_PIN_5 | SX1509_IO_PIN_4,
},
[HCI_LED_2] = {
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_3, // IO3
.ledRed = ~SX1509_IO_PIN_2, // IO2
.ledOff = SX1509_IO_PIN_3 | SX1509_IO_PIN_2,
},
[HCI_LED_3] = {
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_B,
.ledGreen = ~SX1509_IO_PIN_13, // IO13
.ledRed = ~SX1509_IO_PIN_12, // IO12
.ledOff = SX1509_IO_PIN_13 | SX1509_IO_PIN_12,
},
[HCI_LED_4] = {
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_1, // IO1
.ledRed = ~SX1509_IO_PIN_0, // IO0
.ledOff = SX1509_IO_PIN_1 | SX1509_IO_PIN_0,
},
[HCI_LED_5] = {
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_7, // IO7
.ledRed = ~SX1509_IO_PIN_6, // IO6
.ledOff = SX1509_IO_PIN_7 | SX1509_IO_PIN_6,
},
[HCI_LED_6] = {
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_B,
.ledGreen = ~SX1509_IO_PIN_9, // IO9
.ledRed = ~SX1509_IO_PIN_8, // IO8
.ledOff = SX1509_IO_PIN_9 | SX1509_IO_PIN_8,
},
[HCI_LED_7] = {
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_B,
.ledGreen = ~SX1509_IO_PIN_11, // IO11
.ledRed = ~SX1509_IO_PIN_10, // I010
.ledOff = SX1509_IO_PIN_11 | SX1509_IO_PIN_10,
},
[HCI_LED_8] = {
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_5, // IO5
.ledRed = ~SX1509_IO_PIN_4, // IO4
.ledOff = SX1509_IO_PIN_5 | SX1509_IO_PIN_4,
},
[HCI_LED_9] = {
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_3, // IO3
.ledRed = ~SX1509_IO_PIN_2, // IO2
.ledOff = SX1509_IO_PIN_3 | SX1509_IO_PIN_2,
},
[HCI_LED_10] = {
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_1, // IO1
.ledRed = ~SX1509_IO_PIN_0, // IO0
.ledOff = SX1509_IO_PIN_1 | SX1509_IO_PIN_0,
},
[HCI_LED_11] = {
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_7, // IO7
.ledRed = ~SX1509_IO_PIN_6, // IO6
.ledOff = SX1509_IO_PIN_7 | SX1509_IO_PIN_6,
},
[HCI_LED_12] = {
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_B,
.ledGreen = ~SX1509_IO_PIN_9, // IO9
.ledRed = ~SX1509_IO_PIN_8, // IO8
.ledOff = SX1509_IO_PIN_9 | SX1509_IO_PIN_8,
},
[HCI_LED_13] = {
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_B,
.ledGreen = ~SX1509_IO_PIN_11, // IO11
.ledRed = ~SX1509_IO_PIN_10, // IO10
.ledOff = SX1509_IO_PIN_11 | SX1509_IO_PIN_10,
},
[HCI_LED_14] = {
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_B,
.ledGreen = ~SX1509_IO_PIN_13, // IO13
.ledRed = ~SX1509_IO_PIN_12, // IO12
.ledOff = SX1509_IO_PIN_13 | SX1509_IO_PIN_12,
}
};
static const hciLedData ledData[HCI_LED_TOTAL_NOS] =
{ [HCI_LED_1] =
{
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_5, // IO5
.ledRed = ~SX1509_IO_PIN_4, // IO4
.ledOff = SX1509_IO_PIN_5 | SX1509_IO_PIN_4,
},
[HCI_LED_2] =
{
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_3, // IO3
.ledRed = ~SX1509_IO_PIN_2, // IO2
.ledOff = SX1509_IO_PIN_3 | SX1509_IO_PIN_2,
},
[HCI_LED_3] =
{
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_B,
.ledGreen = ~SX1509_IO_PIN_13, // IO13
.ledRed = ~SX1509_IO_PIN_12, // IO12
.ledOff = SX1509_IO_PIN_13 | SX1509_IO_PIN_12,
},
[HCI_LED_4] =
{
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_1, // IO1
.ledRed = ~SX1509_IO_PIN_0, // IO0
.ledOff = SX1509_IO_PIN_1 | SX1509_IO_PIN_0,
},
[HCI_LED_5] =
{
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_7, // IO7
.ledRed = ~SX1509_IO_PIN_6, // IO6
.ledOff = SX1509_IO_PIN_7 | SX1509_IO_PIN_6,
},
[HCI_LED_6] =
{
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_B,
.ledGreen = ~SX1509_IO_PIN_9, // IO9
.ledRed = ~SX1509_IO_PIN_8, // IO8
.ledOff = SX1509_IO_PIN_9 | SX1509_IO_PIN_8,
},
[HCI_LED_7] =
{
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_B,
.ledGreen = ~SX1509_IO_PIN_11, // IO11
.ledRed = ~SX1509_IO_PIN_10, // I010
.ledOff = SX1509_IO_PIN_11 | SX1509_IO_PIN_10,
},
[HCI_LED_8] =
{
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_5, // IO5
.ledRed = ~SX1509_IO_PIN_4, // IO4
.ledOff = SX1509_IO_PIN_5 | SX1509_IO_PIN_4,
},
[HCI_LED_9] =
{
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_3, // IO3
.ledRed = ~SX1509_IO_PIN_2, // IO2
.ledOff = SX1509_IO_PIN_3 | SX1509_IO_PIN_2,
},
[HCI_LED_10] =
{
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_1, // IO1
.ledRed = ~SX1509_IO_PIN_0, // IO0
.ledOff = SX1509_IO_PIN_1 | SX1509_IO_PIN_0,
},
[HCI_LED_11] =
{
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_7, // IO7
.ledRed = ~SX1509_IO_PIN_6, // IO6
.ledOff = SX1509_IO_PIN_7 | SX1509_IO_PIN_6,
},
[HCI_LED_12] =
{
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_B,
.ledGreen = ~SX1509_IO_PIN_9, // IO9
.ledRed = ~SX1509_IO_PIN_8, // IO8
.ledOff = SX1509_IO_PIN_9 | SX1509_IO_PIN_8,
},
[HCI_LED_13] =
{
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_B,
.ledGreen = ~SX1509_IO_PIN_11, // IO11
.ledRed = ~SX1509_IO_PIN_10, // IO10
.ledOff = SX1509_IO_PIN_11 | SX1509_IO_PIN_10,
},
[HCI_LED_14] = {
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_B,
.ledGreen = ~SX1509_IO_PIN_13, // IO13
.ledRed = ~SX1509_IO_PIN_12, // IO12
.ledOff = SX1509_IO_PIN_13 | SX1509_IO_PIN_12,
} };
/*****************************************************************************
** FUNCTION NAME : hci_led_turnon_green
@@ -286,11 +299,12 @@ static ReturnStatus hci_led_configure_onofftime(const HciLedCfg *driver)
/* Configure LED driver parameters(RegTOn, RegOff) for Left side LEDs */
status = hci_led_configure_sx1509_onofftime(
&driver->sx1509_dev[HCI_LED_DRIVER_LEFT]);
&driver->sx1509_dev[HCI_LED_DRIVER_LEFT]);
if (status == RETURN_OK) {
/* Configure LED driver parameters(RegTOn, RegOff) for Right side LEDs */
/* Configure LED driver parameters(RegTOn, RegOff) for Right side LEDs
*/
hci_led_configure_sx1509_onofftime(
&driver->sx1509_dev[HCI_LED_DRIVER_RIGHT]);
&driver->sx1509_dev[HCI_LED_DRIVER_RIGHT]);
}
return status;
}
@@ -319,17 +333,15 @@ ReturnStatus hci_led_system_boot(const HciLedCfg *driver)
}
/* Turn on the LEDs one by one from Left to Right of LED Board */
for (index = 0; index < HCI_LED_TOTAL_NOS; index++) {
status = ioexp_led_get_data(
&driver->sx1509_dev[ledData[index].ioexpDev],
ledData[index].ledReg,
&regValue);
status =
ioexp_led_get_data(&driver->sx1509_dev[ledData[index].ioexpDev],
ledData[index].ledReg, &regValue);
regValue &= ledData[index].ledGreen;
status = ioexp_led_set_data(
&driver->sx1509_dev[ledData[index].ioexpDev],
ledData[index].ledReg, regValue,
0);
status =
ioexp_led_set_data(&driver->sx1509_dev[ledData[index].ioexpDev],
ledData[index].ledReg, regValue, 0);
if (status != RETURN_OK) {
break;
}
@@ -424,7 +436,8 @@ ReturnStatus hci_led_radio_failure(const HciLedCfg *driver)
status = hci_led_turnoff_all(driver);
if (status == RETURN_OK) {
/* Turn On Left side Red LEDs */
status = ioexp_led_set_data(HCI_LED_DRIVER_LEFT, SX1509_REG_AB, 0xAA, 0xAA);
status =
ioexp_led_set_data(HCI_LED_DRIVER_LEFT, SX1509_REG_AB, 0xAA, 0xAA);
}
return status;
@@ -475,17 +488,19 @@ ReturnStatus led_init(const HciLedCfg *driver)
- Disable input buffer (RegInputDisable)
- Disable pull-up (RegPullUp)
- Enable open drain (RegOpenDrain)
- Set direction to output (RegDir) <20> by default RegData is set high => LED OFF
- Set direction to output (RegDir) <20> by default RegData is set high => LED
OFF
- Enable oscillator (RegClock)
- Configure LED driver clock and mode if relevant (RegMisc)
- Enable LED driver operation (RegLEDDriverEnable)
- Configure LED driver parameters (RegTOn, RegIOn, RegOff, RegTRise, RegTFall)
- Configure LED driver parameters (RegTOn, RegIOn, RegOff, RegTRise,
RegTFall)
- Set RegData bit low => LED driver started
*/
/* Initilaize Left and Right LED driver SX1509 to turn on LED */
for (index = 0; index < HCI_LED_DRIVER_COUNT; index++) {
DEBUG("HCILED:INFO:: Initilaizing LED driver SX1509 0x%x.\n",\
DEBUG("HCILED:INFO:: Initilaizing LED driver SX1509 0x%x.\n",
driver->sx1509_dev[index].slave_addr);
/* Do software reset for LED driver */
@@ -532,8 +547,8 @@ ReturnStatus led_init(const HciLedCfg *driver)
}
/* Configure LED driver clock and mode if relevant (RegMisc) */
status = ioexp_led_config_misc(&driver->sx1509_dev[index],
REG_MISC_VALUE);
status =
ioexp_led_config_misc(&driver->sx1509_dev[index], REG_MISC_VALUE);
if (status != RETURN_OK) {
return status;
}
@@ -551,10 +566,11 @@ ReturnStatus led_init(const HciLedCfg *driver)
return status;
}
void led_configure(HciLedCfg* driver) {
void led_configure(HciLedCfg *driver)
{
/* Initialize IO pins */
OcGpio_configure(&driver->pin_ec_gpio, OCGPIO_CFG_OUTPUT |
OCGPIO_CFG_OUT_HIGH);
OcGpio_configure(&driver->pin_ec_gpio,
OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_HIGH);
}
/*****************************************************************************
** FUNCTION NAME : led_probe
@@ -567,24 +583,27 @@ void led_configure(HciLedCfg* driver) {
** RETURN TYPE : Success or Failure
**
*****************************************************************************/
ePostCode led_probe(const HciLedCfg *driver, POSTData* postData)
ePostCode led_probe(const HciLedCfg *driver, POSTData *postData)
{
ReturnStatus status = RETURN_NOTOK;
uint8_t regValue = 0x00;
/* Read Test Register 1 of LED driver SX1509 of Left LED Module(RegTest1) */
status = ioexp_led_read_testregister_1(
&driver->sx1509_dev[HCI_LED_DRIVER_LEFT], &regValue);
&driver->sx1509_dev[HCI_LED_DRIVER_LEFT], &regValue);
if (status != RETURN_OK) {
return POST_DEV_MISSING;
}
/* Read Test Register 1 of LED driver SX1509 of Right LED Module(RegTest1) */
/* Read Test Register 1 of LED driver SX1509 of Right LED Module(RegTest1)
*/
status |= ioexp_led_read_testregister_1(
&driver->sx1509_dev[HCI_LED_DRIVER_RIGHT], &regValue);
&driver->sx1509_dev[HCI_LED_DRIVER_RIGHT], &regValue);
if (status != RETURN_OK) {
return POST_DEV_MISSING;
}
post_update_POSTData(postData, &driver->sx1509_dev[HCI_LED_DRIVER_LEFT].bus, &driver->sx1509_dev[HCI_LED_DRIVER_LEFT].slave_addr,0xFF, 0xFF);
post_update_POSTData(postData, &driver->sx1509_dev[HCI_LED_DRIVER_LEFT].bus,
&driver->sx1509_dev[HCI_LED_DRIVER_LEFT].slave_addr,
0xFF, 0xFF);
return POST_DEV_FOUND;
}

223
firmware/ec/src/devices/ltc4015.c
View File

@@ -24,14 +24,14 @@
#define WTF abort()
static ReturnStatus LTC4015_reg_write(const LTC4015_Dev *dev,
uint8_t regAddress,
uint16_t regValue)
uint8_t regAddress, uint16_t regValue)
{
ReturnStatus status = RETURN_NOTOK;
I2C_Handle battHandle = i2c_get_handle(dev->cfg.i2c_dev.bus);
if (!battHandle) {
LOGGER_ERROR("LTC4015:ERROR:: Failed to open I2C bus for battery "
"charge controller 0x%x.\n", dev->cfg.i2c_dev.slave_addr);
"charge controller 0x%x.\n",
dev->cfg.i2c_dev.slave_addr);
} else {
regValue = htole16(regValue);
status = i2c_reg_write(battHandle, dev->cfg.i2c_dev.slave_addr,
@@ -40,15 +40,15 @@ static ReturnStatus LTC4015_reg_write(const LTC4015_Dev *dev,
return status;
}
static ReturnStatus LTC4015_reg_read(const LTC4015_Dev *dev,
uint8_t regAddress,
static ReturnStatus LTC4015_reg_read(const LTC4015_Dev *dev, uint8_t regAddress,
uint16_t *regValue)
{
ReturnStatus status = RETURN_NOTOK;
I2C_Handle battHandle = i2c_get_handle(dev->cfg.i2c_dev.bus);
if (!battHandle) {
LOGGER_ERROR("LTC4015:ERROR:: Failed to open I2C bus for battery "
"charge controller 0x%x.\n", dev->cfg.i2c_dev.slave_addr);
"charge controller 0x%x.\n",
dev->cfg.i2c_dev.slave_addr);
} else {
status = i2c_reg_read(battHandle, dev->cfg.i2c_dev.slave_addr,
regAddress, regValue, 2);
@@ -62,8 +62,8 @@ ReturnStatus LTC4015_cfg_icharge(LTC4015_Dev *dev,
{
/* Maximum charge current target = (ICHARGE_TARGET + 1) * 1mV/RSNSB
=> ICHARGE_TARGET = (target*RSNSB/1mV)-1 */
int icharge_target = round((max_chargeCurrent * dev->cfg.r_snsb) / 1000.0)
- 1;
int icharge_target =
round((max_chargeCurrent * dev->cfg.r_snsb) / 1000.0) - 1;
icharge_target = MAX(0, icharge_target);
return LTC4015_reg_write(dev, LTC4015_ICHARGE_TARGET_SUBADDR,
icharge_target);
@@ -74,15 +74,14 @@ ReturnStatus LTC4015_get_cfg_icharge(LTC4015_Dev *dev,
{
/* Maximum charge current target = (ICHARGE_TARGET + 1) * 1mV/RSNSB */
uint16_t ichargeCurrent = 0x0000;
ReturnStatus status = LTC4015_reg_read(dev,
LTC4015_ICHARGE_TARGET_SUBADDR,
&ichargeCurrent);
ReturnStatus status =
LTC4015_reg_read(dev, LTC4015_ICHARGE_TARGET_SUBADDR, &ichargeCurrent);
*max_chargeCurrent = (ichargeCurrent + 1) * 1000 / dev->cfg.r_snsb;
return status;
}
ReturnStatus LTC4015_cfg_vcharge(LTC4015_Dev *dev,
uint16_t charge_voltageLevel) // millivolts
uint16_t charge_voltageLevel) // millivolts
{
/* See datasheet, page 61:VCHARGE_SETTING */
const double target_v = charge_voltageLevel / (1000.0 * dev->cfg.cellcount);
@@ -106,29 +105,26 @@ ReturnStatus LTC4015_cfg_vcharge(LTC4015_Dev *dev,
vchargeSetting);
}
ReturnStatus LTC4015_get_cfg_vcharge(LTC4015_Dev *dev,
uint16_t *charge_voltageLevel) // millivolts
ReturnStatus
LTC4015_get_cfg_vcharge(LTC4015_Dev *dev,
uint16_t *charge_voltageLevel) // millivolts
{
/* See datasheet, page 61:VCHARGE_SETTING */
uint16_t vchargeSetting = 0x0000;
ReturnStatus status = LTC4015_reg_read(dev,
LTC4015_VCHARGE_SETTING_SUBADDR,
&vchargeSetting);
ReturnStatus status =
LTC4015_reg_read(dev, LTC4015_VCHARGE_SETTING_SUBADDR, &vchargeSetting);
switch (dev->cfg.chem) {
case LTC4015_CHEM_LEAD_ACID:
*charge_voltageLevel =
round(((vchargeSetting / 105.0) + 2.0) *
dev->cfg.cellcount * 1000.0);
*charge_voltageLevel = round(((vchargeSetting / 105.0) + 2.0) *
dev->cfg.cellcount * 1000.0);
break;
case LTC4015_CHEM_LI_FE_PO4:
*charge_voltageLevel =
round(((vchargeSetting / 80.0) + 3.4125) *
dev->cfg.cellcount * 1000.0);
*charge_voltageLevel = round(((vchargeSetting / 80.0) + 3.4125) *
dev->cfg.cellcount * 1000.0);
break;
case LTC4015_CHEM_LI_ION:
*charge_voltageLevel =
round(((vchargeSetting / 80.0) + 3.8125) *
dev->cfg.cellcount * 1000.0);
*charge_voltageLevel = round(((vchargeSetting / 80.0) + 3.8125) *
dev->cfg.cellcount * 1000.0);
break;
default:
WTF;
@@ -140,8 +136,7 @@ ReturnStatus LTC4015_get_cfg_vcharge(LTC4015_Dev *dev,
}
/* Convert a voltage to a valid vbat register value */
static uint16_t voltage_to_vbat_reg(LTC4015_Dev *dev,
int16_t voltage)
static uint16_t voltage_to_vbat_reg(LTC4015_Dev *dev, int16_t voltage)
{
switch (dev->cfg.chem) {
case LTC4015_CHEM_LEAD_ACID:
@@ -157,7 +152,7 @@ static uint16_t voltage_to_vbat_reg(LTC4015_Dev *dev,
}
ReturnStatus LTC4015_cfg_battery_voltage_low(LTC4015_Dev *dev,
int16_t underVoltage) //millivolts
int16_t underVoltage) // millivolts
{
/* See datasheet, page 56:VBAT_LO_ALERT_LIMIT
under voltage limit = [VBAT_*_ALERT_LIMIT] • x(uV) */
@@ -166,15 +161,16 @@ ReturnStatus LTC4015_cfg_battery_voltage_low(LTC4015_Dev *dev,
}
/* Convert a voltage to a valid vbat register value */
static int16_t vbat_reg_to_voltage(LTC4015_Dev *dev,
uint16_t vbat_reg)
static int16_t vbat_reg_to_voltage(LTC4015_Dev *dev, uint16_t vbat_reg)
{
switch (dev->cfg.chem) {
case LTC4015_CHEM_LEAD_ACID:
return ((int16_t) vbat_reg / 1000.0) * (128.176 * dev->cfg.cellcount);
return ((int16_t)vbat_reg / 1000.0) *
(128.176 * dev->cfg.cellcount);
case LTC4015_CHEM_LI_FE_PO4:
case LTC4015_CHEM_LI_ION:
return ((int16_t) vbat_reg / 1000.0) * (192.264 * dev->cfg.cellcount);
return ((int16_t)vbat_reg / 1000.0) *
(192.264 * dev->cfg.cellcount);
default:
WTF;
break;
@@ -182,20 +178,20 @@ static int16_t vbat_reg_to_voltage(LTC4015_Dev *dev,
return 0; /* Should never get here, but keeps compiler happy */
}
ReturnStatus LTC4015_get_cfg_battery_voltage_low(LTC4015_Dev *dev,
int16_t *underVolatage) //millivolts
ReturnStatus
LTC4015_get_cfg_battery_voltage_low(LTC4015_Dev *dev,
int16_t *underVolatage) // millivolts
{
/* See datasheet, page 56 */
uint16_t vbatLoLimit = 0x0000;
ReturnStatus status = LTC4015_reg_read(dev,
LTC4015_VBAT_LO_ALERT_LIMIT_SUBADDR,
&vbatLoLimit);
ReturnStatus status = LTC4015_reg_read(
dev, LTC4015_VBAT_LO_ALERT_LIMIT_SUBADDR, &vbatLoLimit);
*underVolatage = vbat_reg_to_voltage(dev, vbatLoLimit);
return status;
}
ReturnStatus LTC4015_cfg_battery_voltage_high(LTC4015_Dev *dev,
int16_t overVoltage) //millivolts
int16_t overVoltage) // millivolts
{
/* See datasheet, page 56:VBAT_HI_ALERT_LIMIT
under voltage limit = [VBAT_*_ALERT_LIMIT] • x(uV) */
@@ -203,21 +199,21 @@ ReturnStatus LTC4015_cfg_battery_voltage_high(LTC4015_Dev *dev,
voltage_to_vbat_reg(dev, overVoltage));
}
ReturnStatus LTC4015_get_cfg_battery_voltage_high(LTC4015_Dev *dev,
int16_t *overVoltage) //millivolts
ReturnStatus
LTC4015_get_cfg_battery_voltage_high(LTC4015_Dev *dev,
int16_t *overVoltage) // millivolts
{
/* See datasheet, page 56 */
uint16_t vbatHiLimit = 0x0000;
ReturnStatus status = LTC4015_reg_read(dev,
LTC4015_VBAT_HI_ALERT_LIMIT_SUBADDR,
&vbatHiLimit);
ReturnStatus status = LTC4015_reg_read(
dev, LTC4015_VBAT_HI_ALERT_LIMIT_SUBADDR, &vbatHiLimit);
*overVoltage = vbat_reg_to_voltage(dev, vbatHiLimit);
return status;
}
ReturnStatus LTC4015_cfg_input_voltage_low(LTC4015_Dev *dev,
int16_t inputUnderVoltage) // millivolts
ReturnStatus
LTC4015_cfg_input_voltage_low(LTC4015_Dev *dev,
int16_t inputUnderVoltage) // millivolts
{
/* See datasheet, page 56:VIN_LO_ALERT_LIMIT
VIN_LO_ALERT_LIMIT = limit/1.648mV */
@@ -226,21 +222,22 @@ ReturnStatus LTC4015_cfg_input_voltage_low(LTC4015_Dev *dev,
vinLoLimit);
}
ReturnStatus LTC4015_get_cfg_input_voltage_low(LTC4015_Dev *dev,
int16_t *inpUnderVoltage) //millivolts
ReturnStatus
LTC4015_get_cfg_input_voltage_low(LTC4015_Dev *dev,
int16_t *inpUnderVoltage) // millivolts
{
/* See datasheet, page 56
* VIN_LO_ALERT_LIMIT = (inpUnderVoltage/(1.648)) */
uint16_t vInLoAlertLimit = 0x0000;
ReturnStatus status = LTC4015_reg_read(dev,
LTC4015_VIN_LO_ALERT_LIMIT_SUBADDR,
&vInLoAlertLimit);
*inpUnderVoltage = (int16_t) vInLoAlertLimit * 1.648;
ReturnStatus status = LTC4015_reg_read(
dev, LTC4015_VIN_LO_ALERT_LIMIT_SUBADDR, &vInLoAlertLimit);
*inpUnderVoltage = (int16_t)vInLoAlertLimit * 1.648;
return status;
}
ReturnStatus LTC4015_cfg_input_current_high(LTC4015_Dev *dev,
int16_t inputOvercurrent) // milliAmps
ReturnStatus
LTC4015_cfg_input_current_high(LTC4015_Dev *dev,
int16_t inputOvercurrent) // milliAmps
{
/* See datasheet, page 56:IIN_HI_ALERT_LIMIT
IIN_HI_ALERT_LIMIT = (limit*RSNSI)/1.46487uV */
@@ -255,10 +252,9 @@ ReturnStatus LTC4015_get_cfg_input_current_high(LTC4015_Dev *dev,
/* See datasheet, page 56
* IIN_HI_ALERT_LIMIT = ((inpOverCurrent*PWR_INT_BATT_RSNSI)/(1.46487)) */
uint16_t iInHiALertLimit = 0x0000;
ReturnStatus status = LTC4015_reg_read(dev,
LTC4015_IIN_HI_ALERT_LIMIT_SUBADDR,
&iInHiALertLimit);
*inpOverCurrent = ((int16_t) iInHiALertLimit * 1.46487) / dev->cfg.r_snsi;
ReturnStatus status = LTC4015_reg_read(
dev, LTC4015_IIN_HI_ALERT_LIMIT_SUBADDR, &iInHiALertLimit);
*inpOverCurrent = ((int16_t)iInHiALertLimit * 1.46487) / dev->cfg.r_snsi;
return status;
}
@@ -278,15 +274,14 @@ ReturnStatus LTC4015_get_cfg_battery_current_low(LTC4015_Dev *dev,
/* See datasheet, page 56
* IBAT_LO_ALERT_LIMIT = ((current*PWR_INT_BATT_RSNSB)/(1.46487)) */
uint16_t iBatLoAlertLimit = 0x0000;
ReturnStatus status = LTC4015_reg_read(dev,
LTC4015_IBAT_LO_ALERT_LIMIT_SUBADDR,
&iBatLoAlertLimit);
*lowbattCurrent = ((int16_t) iBatLoAlertLimit * 1.46487) / dev->cfg.r_snsb;
ReturnStatus status = LTC4015_reg_read(
dev, LTC4015_IBAT_LO_ALERT_LIMIT_SUBADDR, &iBatLoAlertLimit);
*lowbattCurrent = ((int16_t)iBatLoAlertLimit * 1.46487) / dev->cfg.r_snsb;
return status;
}
ReturnStatus LTC4015_cfg_die_temperature_high(LTC4015_Dev *dev,
int16_t dieTemp) // Degrees C
int16_t dieTemp) // Degrees C
{
/* See datasheet, page 57:DIE_TEMP_HI_ALERT_LIMIT
DIE_TEMP_HI_ALERT_LIMIT = (DIE_TEMP • 12010)/45.6°C */
@@ -296,38 +291,39 @@ ReturnStatus LTC4015_cfg_die_temperature_high(LTC4015_Dev *dev,
}
ReturnStatus LTC4015_get_cfg_die_temperature_high(LTC4015_Dev *dev,
int16_t *dieTemp) // Degrees C
int16_t *dieTemp) // Degrees C
{
/* See datasheet, page 57
* DIE_TEMP_HI_ALERT_LIMIT = (dieTemp • 12010)/45.6°C */
uint16_t dieTempAlertLimit = 0x0000;
ReturnStatus status = LTC4015_reg_read(dev,
LTC4015_DIE_TEMP_HI_ALERT_LIMIT_SUBADDR,
&dieTempAlertLimit);
*dieTemp = (((int16_t) dieTempAlertLimit - 12010) / 45.6);
ReturnStatus status = LTC4015_reg_read(
dev, LTC4015_DIE_TEMP_HI_ALERT_LIMIT_SUBADDR, &dieTempAlertLimit);
*dieTemp = (((int16_t)dieTempAlertLimit - 12010) / 45.6);
return status;
}
ReturnStatus LTC4015_cfg_input_current_limit(LTC4015_Dev *dev,
uint16_t inputCurrentLimit) // milliAmps
ReturnStatus
LTC4015_cfg_input_current_limit(LTC4015_Dev *dev,
uint16_t inputCurrentLimit) // milliAmps
{
/* See datasheet, page 61:IIN_LIMIT_SETTING
IIN_LIMIT_SETTING = (limit * RSNSI / 500uV) - 1 */
/* TODO: range check? this is only a 6-bit register */
uint16_t iInLimitSetting = ((inputCurrentLimit * dev->cfg.r_snsi) / 500) - 1;
uint16_t iInLimitSetting =
((inputCurrentLimit * dev->cfg.r_snsi) / 500) - 1;
return LTC4015_reg_write(dev, LTC4015_IIN_LIMIT_SETTING_SUBADDR,
iInLimitSetting);
}
ReturnStatus LTC4015_get_cfg_input_current_limit(LTC4015_Dev *dev,
uint16_t *currentLimit) //milli Amps
ReturnStatus
LTC4015_get_cfg_input_current_limit(LTC4015_Dev *dev,
uint16_t *currentLimit) // milli Amps
{
/* See datasheet, page 56
* Input current limit setting = (IIN_LIMIT_SETTING + 1) • 500uV / RSNSI */
uint16_t iInlimitSetting = 0x0000;
ReturnStatus status = LTC4015_reg_read(dev,
LTC4015_IIN_LIMIT_SETTING_SUBADDR,
&iInlimitSetting);
ReturnStatus status = LTC4015_reg_read(
dev, LTC4015_IIN_LIMIT_SETTING_SUBADDR, &iInlimitSetting);
*currentLimit = ((iInlimitSetting + 1) * 500.0) / dev->cfg.r_snsi;
return status;
}
@@ -337,74 +333,74 @@ ReturnStatus LTC4015_get_die_temperature(LTC4015_Dev *dev,
{
/* Datasheet page 71: temperature = (DIE_TEMP • 12010)/45.6°C */
uint16_t dieTemperature = 0x0000;
ReturnStatus status = LTC4015_reg_read(dev, LTC4015_DIE_TEMP_SUBADDR,
&dieTemperature);
*dieTemp = (((int16_t) dieTemperature - 12010) / 45.6);
ReturnStatus status =
LTC4015_reg_read(dev, LTC4015_DIE_TEMP_SUBADDR, &dieTemperature);
*dieTemp = (((int16_t)dieTemperature - 12010) / 45.6);
return status;
}
ReturnStatus LTC4015_get_battery_current(LTC4015_Dev *dev,
int16_t *iBatt) //milliAmps
int16_t *iBatt) // milliAmps
{
/* Page 70: Battery current = [IBAT] * 1.46487uV/Rsnsb */
uint16_t batteryCurrent = 0x0000;
ReturnStatus status = LTC4015_reg_read(dev, LTC4015_IBAT_SUBADDR,
&batteryCurrent);
*iBatt = ((float) ((int16_t) batteryCurrent * 1.46487)) / (dev->cfg.r_snsb);
ReturnStatus status =
LTC4015_reg_read(dev, LTC4015_IBAT_SUBADDR, &batteryCurrent);
*iBatt = ((float)((int16_t)batteryCurrent * 1.46487)) / (dev->cfg.r_snsb);
return status;
}
ReturnStatus LTC4015_get_input_current(LTC4015_Dev *dev,
int16_t *iIn) //milliAmps
int16_t *iIn) // milliAmps
{
/* Page 71: Input current = [IIN] • 1.46487uV/Rsnsi */
uint16_t inputCurrent = 0x0000;
ReturnStatus status = LTC4015_reg_read(dev, LTC4015_IIN_SUBADDR,
&inputCurrent);
*iIn = ((float) ((int16_t) inputCurrent * 1.46487)) / (dev->cfg.r_snsi);
ReturnStatus status =
LTC4015_reg_read(dev, LTC4015_IIN_SUBADDR, &inputCurrent);
*iIn = ((float)((int16_t)inputCurrent * 1.46487)) / (dev->cfg.r_snsi);
return status;
}
ReturnStatus LTC4015_get_battery_voltage(LTC4015_Dev *dev,
int16_t *vbat) //milliVolts
int16_t *vbat) // milliVolts
{
/* Page 71: 2's compliment VBATSENS/cellcount = [VBAT] • [x]uV */
uint16_t batteryVoltage = 0x0000;
ReturnStatus status = LTC4015_reg_read(dev, LTC4015_VBAT_SUBADDR,
&batteryVoltage);
ReturnStatus status =
LTC4015_reg_read(dev, LTC4015_VBAT_SUBADDR, &batteryVoltage);
*vbat = vbat_reg_to_voltage(dev, batteryVoltage);
return status;
}
ReturnStatus LTC4015_get_input_voltage(LTC4015_Dev *dev,
int16_t *vIn) //milliVolts
int16_t *vIn) // milliVolts
{
/* Page 71: 2's compliment Input voltage = [VIN] • 1.648mV */
uint16_t inputVoltage = 0x0000;
ReturnStatus status = LTC4015_reg_read(dev, LTC4015_VIN_SUBADDR,
&inputVoltage);
*vIn = (int16_t) inputVoltage * 1.648;
ReturnStatus status =
LTC4015_reg_read(dev, LTC4015_VIN_SUBADDR, &inputVoltage);
*vIn = (int16_t)inputVoltage * 1.648;
return status;
}
ReturnStatus LTC4015_get_system_voltage(LTC4015_Dev *dev,
int16_t *vSys) //milliVolts
int16_t *vSys) // milliVolts
{
/* Page 71: 2's compliment system voltage = [VSYS] • 1.648mV */
uint16_t sysVoltage = 0x0000;
ReturnStatus status = LTC4015_reg_read(dev, LTC4015_VSYS_SUBADDR,
&sysVoltage);
*vSys = (int16_t) sysVoltage * 1.648;
ReturnStatus status =
LTC4015_reg_read(dev, LTC4015_VSYS_SUBADDR, &sysVoltage);
*vSys = (int16_t)sysVoltage * 1.648;
return status;
}
ReturnStatus LTC4015_get_icharge_dac(LTC4015_Dev *dev,
int16_t *icharge) //milliAmps
int16_t *icharge) // milliAmps
{
/* Page 72: (ICHARGE_DAC + 1) • 1mV/RSNSB */
uint16_t ichargeDAC = 0x0000;
ReturnStatus status = LTC4015_reg_read(dev, LTC4015_ICHARGE_DAC_SUBADDR,
&ichargeDAC);
ReturnStatus status =
LTC4015_reg_read(dev, LTC4015_ICHARGE_DAC_SUBADDR, &ichargeDAC);
*icharge = (int16_t)((ichargeDAC + 1) / dev->cfg.r_snsb);
return status;
}
@@ -414,12 +410,13 @@ static ReturnStatus _enable_limit_alerts(LTC4015_Dev *dev, uint16_t alertConfig)
return LTC4015_reg_write(dev, LTC4015_EN_LIMIT_ALERTS_SUBADDR, alertConfig);
}
static ReturnStatus _read_enable_limit_alerts(LTC4015_Dev *dev, uint16_t* regValue)
static ReturnStatus _read_enable_limit_alerts(LTC4015_Dev *dev,
uint16_t *regValue)
{
return LTC4015_reg_read(dev, LTC4015_EN_LIMIT_ALERTS_SUBADDR, regValue);
}
static ReturnStatus _read_limit_alerts(LTC4015_Dev *dev, uint16_t* regValue)
static ReturnStatus _read_limit_alerts(LTC4015_Dev *dev, uint16_t *regValue)
{
return LTC4015_reg_read(dev, LTC4015_LIMIT_ALERTS_SUBADDR, regValue);
}
@@ -432,7 +429,7 @@ static ReturnStatus _enable_charger_state_alerts(LTC4015_Dev *dev,
}
static ReturnStatus _read_enable_charger_state_alerts(LTC4015_Dev *dev,
uint16_t* regValue)
uint16_t *regValue)
{
return LTC4015_reg_read(dev, LTC4015_EN_CHARGER_STATE_ALERTS_SUBADDR,
regValue);
@@ -447,8 +444,8 @@ static ReturnStatus _read_charger_state_alerts(LTC4015_Dev *dev,
static ReturnStatus _read_system_status(LTC4015_Dev *dev, uint16_t *regValue)
{
ReturnStatus status = LTC4015_reg_read(dev, LTC4015_SYSTEM_STATUS_SUBADDR,
regValue);
ReturnStatus status =
LTC4015_reg_read(dev, LTC4015_SYSTEM_STATUS_SUBADDR, regValue);
return status;
}
@@ -461,7 +458,8 @@ ReturnStatus LTC4015_get_bat_presence(LTC4015_Dev *dev, bool *present)
return status;
}
static void _ltc4015_isr(void *context) {
static void _ltc4015_isr(void *context)
{
LTC4015_Dev *dev = context;
ReturnStatus status = RETURN_OK;
uint16_t alert_status = 0;
@@ -525,7 +523,8 @@ ReturnStatus LTC4015_init(LTC4015_Dev *dev)
if (dev->cfg.pin_alert) {
const uint32_t pin_evt_cfg = OCGPIO_CFG_INPUT | OCGPIO_CFG_INT_FALLING;
if (OcGpio_configure(dev->cfg.pin_alert, pin_evt_cfg) < OCGPIO_SUCCESS) {
if (OcGpio_configure(dev->cfg.pin_alert, pin_evt_cfg) <
OCGPIO_SUCCESS) {
return RETURN_NOTOK;
}
@@ -536,7 +535,8 @@ ReturnStatus LTC4015_init(LTC4015_Dev *dev)
}
void LTC4015_setAlertHandler(LTC4015_Dev *dev, LTC4015_CallbackFn alert_cb,
void *cb_context) {
void *cb_context)
{
dev->obj.alert_cb = alert_cb;
dev->obj.cb_context = cb_context;
}
@@ -600,6 +600,7 @@ ePostCode LTC4015_probe(LTC4015_Dev *dev, POSTData *postData)
if (!(ltcStatusReg & LTC4015_CHARGER_ENABLED)) {
return POST_DEV_MISSING;
}
post_update_POSTData(postData, dev->cfg.i2c_dev.bus, dev->cfg.i2c_dev.slave_addr,0xFF, 0xFF);
post_update_POSTData(postData, dev->cfg.i2c_dev.bus,
dev->cfg.i2c_dev.slave_addr, 0xFF, 0xFF);
return POST_DEV_FOUND;
}

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