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npcx/flash: not enable the flash pinmux when using internal flash

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In npcx5, the flash interface pinmux should be turned on in order to
access the external flash. However, in npcx7, the internal flash is
used. It is meaningless to turn the pinmux on. And it also causes the
alternative function of these pins not work normally(such as
GPIOA0/GPIOA2) if the pinmux is enabled. This CL uses the preprocessor
flag NPCX_INT_FLASH_SUPPORT to conditionally prohibit the execution of
flash pinmux code.

BRANCH=none
BUG=none
TEST=No build errors for "make buildall". Build npcx_evb and npcx7_evb
boards, make sure the pinmux are correctly configured seperately.

Change-Id: Iba2300159f204b65d15852ec1755714df0c64816
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/704316
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This commit is contained in:
CHLin
2017-10-06 16:13:07 +08:00
committed by chrome-bot
parent 828da3d556
commit 72d91062f4
2 changed files with 6 additions and 0 deletions
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4
chip/npcx/flash.c
View File

@@ -40,6 +40,7 @@ static struct mutex flash_lock;
/*****************************************************************************/
/* flash internal functions */
#if !defined(NPCX_INT_FLASH_SUPPORT)
static void flash_pinmux(int enable)
{
/* Select pin-mux for FIU*/
@@ -57,6 +58,7 @@ static void flash_pinmux(int enable)
CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_2);
}
}
#endif
static void flash_execute_cmd(uint8_t code, uint8_t cts)
{
@@ -683,8 +685,10 @@ int flash_pre_init(void)
flash_protect_int_flash(!gpio_get_level(GPIO_WP_L));
#endif
#if !defined(NPCX_INT_FLASH_SUPPORT)
/* Enable FIU interface */
flash_pinmux(1);
#endif
#ifdef CONFIG_EXTERNAL_STORAGE
/* Disable tristate all the time */

2
chip/npcx/gpio.c
View File

@@ -367,7 +367,9 @@ void gpio_pre_init(void)
/* Pin_Mux for FIU/SPI (set to GPIO) */
SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_GPIO_NO_SPIP);
#if defined(NPCX_INT_FLASH_SUPPORT)
SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
#endif
/* Pin_Mux for PWRGD */
SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_NO_PWRGD);