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reef: keep analogix pd chip in reset

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The gpio settings for the USB_PD_RST_ODL signal had the default
state high while the power enable, EN_USB_TCPC_PWR, was low. This
is combination of settings is invalid for the part. Therefore,
keep USB_PD_RST_ODL low until board_set_tcpc_power_mode() is called
to bring the pd chip online.

BUG=chrome-os-partner:53035
BRANCH=None
TEST=Rachel confirmed things still working.

Change-Id: I8b6b54a474c00165a4d0af944fb60f2923b9ef5c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347000
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Aaron Durbin
2016-05-24 10:49:27 -05:00
committed by chrome-bot
parent c8a4948417
commit 90b934d4e9
1 changed files with 1 additions and 1 deletions
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2
board/reef/gpio.inc
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@@ -109,7 +109,7 @@ GPIO(PCH_RCIN_L, PIN(6, 1), GPIO_ODR_HIGH) /* SYS_RST_ODL */
GPIO(CHARGER_RST_ODL, PIN(C, 0), GPIO_ODR_HIGH)
GPIO(USB_A_CHARGE_EN_L, PIN(4, 2), GPIO_OUT_HIGH)
GPIO(EN_USB_TCPC_PWR, PIN(C, 3), GPIO_OUT_LOW)
GPIO(USB_PD_RST_ODL, PIN(0, 3), GPIO_ODR_HIGH)
GPIO(USB_PD_RST_ODL, PIN(0, 3), GPIO_ODR_LOW)
GPIO(EN_USB_A_5V, PIN(4, 1), GPIO_OUT_LOW)
GPIO(USB_C0_5V_EN, PIN(D, 3), GPIO_OUT_LOW) /* EN_USB_CN_5V_OUT, Enable C0 */
GPIO(USB_C1_5V_EN, PIN(B, 1), GPIO_OUT_LOW) /* EN_USB_C1_5V_OUT, Enable C1 */