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npcx: gpio: Don't increase priority of SHI_CS for non-SHI boards

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Systems that don't use SHI don't need elevated SHI_CS interrupt
priority.

BUG=None
TEST=`make buildall -j`
BRANCH=None

Change-Id: Ica6e82332bc7ef8f92c00d847cd3ff0df7ede429
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/350570
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit is contained in:
Shawn Nematbakhsh
2016-06-07 17:11:51 -07:00
committed by chrome-bot
parent 07e4b2087f
commit 99515baf0b
1 changed files with 4 additions and 0 deletions
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4
chip/npcx/gpio.c
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@@ -832,12 +832,16 @@ DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 1);
DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 1);
DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 1);
DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 1);
#ifdef CONFIG_HOSTCMD_SPS
/*
* HACK: Make CS GPIO P0 to improve SHI reliability.
* TODO: Increase CS-assertion-to-transaction-start delay on host to
* accommodate P1 CS interrupt.
*/
DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 0);
#else
DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 1);
#endif
DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 1);
DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 1);