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STM32F0 SPI Fixes: 4x Dummy Bytes

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Seems like STM32_SPI_CR2_FRXTH from 5d208b99(STM32F0 SPI Fixes) was not enough
to "disable" RX FIFO from the F0 series. There were still a few bytes stuck in
the FIFO just after a command with a long sequence of 00 bytes.

This increases the dummy bytes read just before a DMA transfer to 4(size of the
FIFO).

BUG=none
BRANCH=none
TEST=Veyron with the new EC should survive the AP booting. ectool version will
work right away after boot. This change should not affect other STM32 chips
because reading dummy bytes from an empty register is essentially a NOP.

Change-Id: I812208622a75ecce82433eb6c12595fee3c1428b
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212297
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit is contained in:
Alexandru M Stan
2014-08-13 13:42:07 -07:00
committed by chrome-internal-fetch
parent cb7468744d
commit aa3ca9bc53
1 changed files with 6 additions and 2 deletions
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8
chip/stm32/spi.c
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@@ -255,10 +255,14 @@ static void setup_for_transaction(void)
dma_disable(STM32_DMAC_SPI1_TX);
/*
* Read a byte in case there is one pending; this prevents the receive
* DMA from getting that byte right when we start it
* Read dummy bytes in case there are some pending; this prevents the
* receive DMA from getting that byte right when we start it. 4 Bytes
* makes sure the RX FIFO on the F0 is empty as well.
*/
dummy = spi->dr;
dummy = spi->dr;
dummy = spi->dr;
dummy = spi->dr;
/* Start DMA */
dma_start_rx(&dma_rx_option, sizeof(in_msg), in_msg);