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aa3ca9bc53
Seems like STM32_SPI_CR2_FRXTH from 5d208b99(STM32F0 SPI Fixes) was not enough to "disable" RX FIFO from the F0 series. There were still a few bytes stuck in the FIFO just after a command with a long sequence of 00 bytes. This increases the dummy bytes read just before a DMA transfer to 4(size of the FIFO). BUG=none BRANCH=none TEST=Veyron with the new EC should survive the AP booting. ectool version will work right away after boot. This change should not affect other STM32 chips because reading dummy bytes from an empty register is essentially a NOP. Change-Id: I812208622a75ecce82433eb6c12595fee3c1428b Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/212297 Reviewed-by: Randall Spangler <rspangler@chromium.org>
For an overview of the Embedded Controller firmware, refer to http://www.chromium.org/chromium-os/2014-firmware-summit