scottk/OpenCellular
1
0
Fork 0
mirror of https://github.com/Telecominfraproject/OpenCellular.git synced 2026-01-08 16:41:55 +00:00
Code Issues Packages Projects Releases Wiki Activity

mec1322: clocks: Don't squash reserved bits in sleep / wake

Browse Source 
Keep the state of reserved bits in SLP_EN registers when sleeping and
waking from sleep.

BUG=chrome-os-partner:45003
TEST=Manual on glados. Go to S3 and measure EC power. Go to deep sleep
and wake. Re-measure power and verify that it is not ~60% higher than
originally measured.
BRANCH=Strago

Change-Id: I6b6b0efcd146fe1a68b41b9b33b25740090dc08f
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/298655
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This commit is contained in:
Shawn Nematbakhsh
2015-09-09 17:24:17 -07:00
committed by chrome-bot
parent 4b633da7b9
commit b0c82fb8a8
3 changed files with 24 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
chip/mec1322/clock.c
View File

@@ -178,9 +178,9 @@ static void prepare_for_deep_sleep(void)
MEC1322_TMR16_CTL(0) &= ~1;
MEC1322_PCR_CHIP_SLP_EN |= 0x3;
MEC1322_PCR_EC_SLP_EN = 0xFFFFFFFF;
MEC1322_PCR_HOST_SLP_EN = 0xFFFFFFFF;
MEC1322_PCR_EC_SLP_EN2 = 0xFFFFFFFF;
MEC1322_PCR_EC_SLP_EN |= MEC1322_PCR_EC_SLP_EN_SLEEP;
MEC1322_PCR_HOST_SLP_EN |= MEC1322_PCR_HOST_SLP_EN_SLEEP;
MEC1322_PCR_EC_SLP_EN2 |= MEC1322_PCR_EC_SLP_EN2_SLEEP;
MEC1322_LPC_ACT = 0x0;
MEC1322_LPC_CLK_CTRL |= 0x2;
@@ -211,9 +211,9 @@ static void resume_from_deep_sleep(void)
MEC1322_PCR_SLOW_CLK_CTL |= 0x1e0;
MEC1322_PCR_CHIP_SLP_EN &= ~0x3;
MEC1322_PCR_EC_SLP_EN &= ~0xe0700ff7;
MEC1322_PCR_HOST_SLP_EN &= ~0x5f003;
MEC1322_PCR_EC_SLP_EN2 &= ~0x1ffffff8;
MEC1322_PCR_EC_SLP_EN &= MEC1322_PCR_EC_SLP_EN_WAKE;
MEC1322_PCR_HOST_SLP_EN &= MEC1322_PCR_HOST_SLP_EN_WAKE;
MEC1322_PCR_EC_SLP_EN2 &= MEC1322_PCR_EC_SLP_EN2_WAKE;
MEC1322_PCR_SYS_SLP_CTL = 0xF8; /* default */

12
chip/mec1322/registers.h
View File

@@ -25,12 +25,24 @@
#define MEC1322_PCR_CHIP_SLP_EN REG32(MEC1322_PCR_BASE + 0x0)
#define MEC1322_PCR_CHIP_CLK_REQ REG32(MEC1322_PCR_BASE + 0x4)
#define MEC1322_PCR_EC_SLP_EN REG32(MEC1322_PCR_BASE + 0x8)
/* Command all blocks to sleep */
#define MEC1322_PCR_EC_SLP_EN_SLEEP 0xe0700ff7
/* Allow all blocks to request clocks */
#define MEC1322_PCR_EC_SLP_EN_WAKE (~0xe0700ff7)
#define MEC1322_PCR_EC_CLK_REQ REG32(MEC1322_PCR_BASE + 0xc)
#define MEC1322_PCR_HOST_SLP_EN REG32(MEC1322_PCR_BASE + 0x10)
/* Command all blocks to sleep */
#define MEC1322_PCR_HOST_SLP_EN_SLEEP 0x5f003
/* Allow all blocks to request clocks */
#define MEC1322_PCR_HOST_SLP_EN_WAKE (~0x5f003)
#define MEC1322_PCR_HOST_CLK_REQ REG32(MEC1322_PCR_BASE + 0x14)
#define MEC1322_PCR_SYS_SLP_CTL REG32(MEC1322_PCR_BASE + 0x18)
#define MEC1322_PCR_PROC_CLK_CTL REG32(MEC1322_PCR_BASE + 0x20)
#define MEC1322_PCR_EC_SLP_EN2 REG32(MEC1322_PCR_BASE + 0x24)
/* Mask to command all blocks to sleep */
#define MEC1322_PCR_EC_SLP_EN2_SLEEP 0x1ffffff8
/* Allow all blocks to request clocks */
#define MEC1322_PCR_EC_SLP_EN2_WAKE (~0x03fffff8)
#define MEC1322_PCR_EC_CLK_REQ2 REG32(MEC1322_PCR_BASE + 0x28)
#define MEC1322_PCR_SLOW_CLK_CTL REG32(MEC1322_PCR_BASE + 0x2c)
#define MEC1322_PCR_CHIP_OSC_ID REG32(MEC1322_PCR_BASE + 0x30)

12
chip/mec1322/system.c
View File

@@ -329,9 +329,9 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds)
/* Disable blocks */
MEC1322_PCR_CHIP_SLP_EN |= 0x3;
MEC1322_PCR_EC_SLP_EN |= 0xe0700ff7;
MEC1322_PCR_HOST_SLP_EN |= 0x5f003;
MEC1322_PCR_EC_SLP_EN2 |= 0x1ffffff8;
MEC1322_PCR_EC_SLP_EN |= MEC1322_PCR_EC_SLP_EN_SLEEP;
MEC1322_PCR_HOST_SLP_EN |= MEC1322_PCR_HOST_SLP_EN_SLEEP;
MEC1322_PCR_EC_SLP_EN2 |= MEC1322_PCR_EC_SLP_EN2_SLEEP;
MEC1322_PCR_SLOW_CLK_CTL &= 0xfffffc00;
/* Set sleep state */
@@ -394,9 +394,9 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds)
/* Enable blocks */
MEC1322_PCR_SLOW_CLK_CTL |= 0x1e0;
MEC1322_PCR_CHIP_SLP_EN &= ~0x3;
MEC1322_PCR_EC_SLP_EN &= ~0xe0700ff7;
MEC1322_PCR_HOST_SLP_EN &= ~0x5f003;
MEC1322_PCR_EC_SLP_EN2 &= ~0x1ffffff8;
MEC1322_PCR_EC_SLP_EN &= MEC1322_PCR_EC_SLP_EN_WAKE;
MEC1322_PCR_HOST_SLP_EN &= MEC1322_PCR_HOST_SLP_EN_WAKE;
MEC1322_PCR_EC_SLP_EN2 &= MEC1322_PCR_EC_SLP_EN2_WAKE;
/* Enable timer */
MEC1322_TMR32_CTL(0) |= 1;