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cortex-m0: add more constraints on atomic implementation

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In ARMv6-m instruction set, the load/store address register can only be
a "low" register : r0..r7.
Update the inline assembly constraints to match the hardware.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=make buildall

Change-Id: I9872aeb437b2bb6401bed8076348e26d434320dd
Reviewed-on: https://chromium-review.googlesource.com/224582
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Vincent Palatin
2014-10-20 15:17:57 -07:00
committed by chrome-internal-fetch
parent cefb58066d
commit ba98b92bbb
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
core/cortex-m0/atomic.h
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@@ -24,7 +24,7 @@
" str %0, [%1]\n" \
" cpsie i\n" \
: "=&r" (reg0) \
: "r" (a), "r" (v) : "cc"); \
: "b" (a), "r" (v) : "cc"); \
} while (0)
static inline void atomic_clear(uint32_t *addr, uint32_t bits)
@@ -57,7 +57,7 @@ static inline uint32_t atomic_read_clear(uint32_t *addr)
" str %2, [%1]\n"
" cpsie i\n"
: "=&r" (ret)
: "r" (addr), "r" (0) : "cc");
: "b" (addr), "r" (0) : "cc");
return ret;
}