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chip/npcx: interrupt on both edges of PLTRST_L

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Different actions need to be taken on PLTRST_L depending on
if it is asserted or deasserted. The vstore module needs to
reset its locks when PLTRST_L is asserted (host is in reset).
The interrupt was previously on occurring on a deassertion of
PLTRST_L (rising edge). That's not conducive for handling
actions which are required for assertion (falling edge).
Lastly, fix the CONFIG_CHIPSET_RESET_HOOK logic to be
called when PLTRST_L is asserted.

BUG=chrome-os-partner:55471
BRANCH=None
TEST=Able to boot and reboot without getting vboot hash saving
errors. Also am able to see the assertion/deassertion messages
on the console.

Change-Id: I70eac3309a5876de775ec5c34dab2e9aa8bbb42c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362000
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Aaron Durbin
2016-07-20 13:47:01 -05:00
committed by chrome-bot
parent 8162f744e0
commit bf64fc0758
1 changed files with 12 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
chip/npcx/lpc.c
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@@ -754,6 +754,8 @@ int lpc_get_pltrst_asserted(void)
/* Initialize host settings by interrupt */
void lpc_lreset_pltrst_handler(void)
{
int pltrst_asserted;
/* Clear pending bit of WUI */
SET_BIT(NPCX_WKPCL(MIWU_TABLE_0 , MIWU_GROUP_5), 7);
@@ -761,21 +763,24 @@ void lpc_lreset_pltrst_handler(void)
if (chipset_pltrst_is_valid && !chipset_pltrst_is_valid())
return;
ccprintf("[%T PLTRST deasserted]\n");
pltrst_asserted = lpc_get_pltrst_asserted();
ccprintf("LPC RESET# %sasserted",
pltrst_asserted ? "" : "de");
/*
* Once LRESET is de-asserted (low -> high), we need to intialize lpc
* settings once. If RSTCTL_LRESET_PLTRST_MODE is active, LPC registers
* won't be reset by Host domain reset but Core domain does.
*/
lpc_host_register_init();
if (!pltrst_asserted)
lpc_host_register_init();
else {
#ifdef CONFIG_CHIPSET_RESET_HOOK
if (lpc_get_pltrst_asserted()) {
/* Notify HOOK_CHIPSET_RESET */
hook_call_deferred(&lpc_chipset_reset_data, MSEC);
}
#endif
}
}
static void lpc_init(void)
@@ -897,9 +902,8 @@ static void lpc_init(void)
/* Initialize LRESET# interrupt */
/* Set detection mode to edge */
CLEAR_BIT(NPCX_WKMOD(MIWU_TABLE_0, MIWU_GROUP_5), 7);
/* Handle interrupting on rising edge */
CLEAR_BIT(NPCX_WKAEDG(MIWU_TABLE_0, MIWU_GROUP_5), 7);
SET_BIT(NPCX_WKEDG(MIWU_TABLE_0, MIWU_GROUP_5), 7);
/* Handle interrupting on any edge */
SET_BIT(NPCX_WKAEDG(MIWU_TABLE_0, MIWU_GROUP_5), 7);
/* Enable wake-up input sources */
SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7);
#endif