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glados: Add pullup to SPI MISO GPIO

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When SPI CS is deasserted, SPI MISO is floating, which leads to leakage.

BUG=chrome-os-partner:42104
BRANCH=None
TEST=Manual on glados. Verify S5 power drops by ~1.5mW and sysjump / EC
RW hashing continues to function.

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0ba8fcab1618f396adc32984da93e37c5ff770a4
Reviewed-on: https://chromium-review.googlesource.com/311821
Commit-Ready: Shawn N <shawnn@gmail.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This commit is contained in:
Shawn Nematbakhsh
2015-11-09 15:27:52 -08:00
committed by chrome-bot
parent b83dbc3199
commit c391492dca
1 changed files with 1 additions and 1 deletions
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2
board/glados/gpio.inc
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@@ -148,7 +148,7 @@ ALTERNATE(PIN_MASK(12, 0x01), 1, MODULE_LPC, 0)
/* MOSI - GPIO054 */
ALTERNATE(PIN_MASK(5, 0x10), 1, MODULE_SPI, 0)
/* MISO - GPIO164 */
ALTERNATE(PIN_MASK(16, 0x10), 1, MODULE_SPI, 0)
ALTERNATE(PIN_MASK(16, 0x10), 1, MODULE_SPI, GPIO_PULL_UP)
/* PVT_SCLK - GPIO153 */
ALTERNATE(PIN_MASK(15, 0x08), 1, MODULE_SPI, 0)
/* SHD_CS0# - GPIO150. Shared SPI chip select */