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chip/stm32/registers.h: Fix STM32_FLASH_OPT_LOCKED polarity

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We currently set STM32_FLASH_OPT_LOCKED
to (STM32_FLASH_CR & FLASH_CR_OPTWRE), however the bit is set
when option byte are _unlocked_.

From STM32F0 Reference Manual:

Bit 9 OPTWRE: Option byte write enable
  When set, the option byte can be programmed. This bit is set
  on writing the correct key sequence to the FLASH_OPTKEYR register.
  This bit can be reset by software

BRANCH=none
BUG=chromium:739608
TEST=Flash hammer, flashwp true; reboot; flashinfo
     => hammer does not hang on reboot, RO is protected

Change-Id: I1b6eb5d638534ece90d6d5164586f49bdb0c151d
Reviewed-on: https://chromium-review.googlesource.com/561036
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Nicolas Boichat
2017-07-06 14:43:16 +08:00
committed by chrome-bot
parent d33618ce9f
commit c869b0f15c
1 changed files with 1 additions and 1 deletions
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2
chip/stm32/registers.h
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@@ -1347,7 +1347,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
#define FLASH_CR_LOCK (1 << 7)
#define FLASH_CR_OPTWRE (1 << 9)
#define FLASH_CR_OBL_LAUNCH (1 << 13)
#define STM32_FLASH_OPT_LOCKED (STM32_FLASH_CR & FLASH_CR_OPTWRE)
#define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE))
#define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14)
#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c)
#define STM32_FLASH_OBR_RDP_MASK (3 << 1)