The yabel emulator depends on IO ports, that aren't available on
ARM and MIPS. Add additional dependencies to fix compilation errors
with the default configuration.
Change-Id: If0e28b356c01cb3ae0739a54aa3531a2acedbfbb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26754
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Name the CPU device structure as per processor brand string.
Before logs use to look like:
APIC: 01 (unknown)
Now logs looks like(depending on CPU on which it is tested):
APIC: 01 (Intel(R) Core(TM) m3-7Y30 CPU @ 1.00GHz)
BUG=None
BRANCH=None
TEST= Build & boot Soraka.
Change-Id: I6af0e29bbbdb59406baeae32f7874ff9036a9c81
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/26740
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If we have POSTCAR_STAGE there is no need for
romstage to include LZMA decompression code.
Reduces romstage by about 4 kiB on x86.
Change-Id: I4c475986b2a94e5cd540c3eead433ed6c0a815ed
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Non of the .c files is using a function from console.h directly.
Include console.h is moved to sd_mmc.h, where sdhc_error("msg..") is
defined.
Change-Id: Ic9283f227a37785056b9fac216fabcac054066a0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26752
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
G45 provides only a single panel fitter. Therefore, we can only enable
a single pipe that requires scaling. Scaler_Available() tells us if a
panel fitter is available for a given pipe. We use the result to filter
invalid configurations early.
Change-Id: Ie05bfb58318e79edc8ab81598458e620ffdcb2ab
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26768
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The G45 panel fitter needs a hint how the resulting image will be boxed
to keep aspect ratio. As we can't change the panel fitter configuration
while the pipe is enabled, we always tear the whole pipe down when the
configuration changes.
Change-Id: Ifedc19abbadcbae61892d0051f08592637f90fd7
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26767
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add Update_Cursor() that allows updates to all cursor parameters,
Place_Cursor() and Move_Cursor() to update the position only.
Change-Id: I6e97442847ea42662214390d80aaf634a4b1ab5a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/23216
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: Nico Huber <nico.h@gmx.de>
Programming the cursor plane registers is straight forward.
On newer hardware, we also have to account for the cursor in GPU
internal buffer allocation. Fortunately, we have enough resources
for a static configuration that always accounts for a cursor.
Cursors with a location that is off limits are placed off-screen
in the top-left corner, hence, are invisible.
Change-Id: I08ffd81d524e14e464af6e6f6fb5effbd4890d8a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/23204
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Allow ARGB cursors of 64x64, 128x128 or 256x256 pixels. Valid positions
depend a lot on the hardware generation, so we'll accept arbitrary
integer values in the interface and filter them internally. An out of
bounds cursor will simply be invisible.
It's unclear if the parameters also apply to other GFX hardware. Thus,
we keep the types in the GMA sub-package for now.
Change-Id: I1a380037ac91ba2beeb33c27a6882eb5caa126f9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/23185
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Yet after few months, it's already too confusing to me. Let's reserve
`Pos` for `Positive` and spell out `Position`.
Change-Id: I3445d20665ae6a993cb0e46d08e8f3148abef40e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26696
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
If scaling is required, always drive DDI A through the Power Down Well
(PDW) path. If not, keep the current "always on" path to allow power
saving.
Hopefully, this also enables us to use the eDP in legacy VGA text mode.
Change-Id: Ia9135d253083d363872c7cf0b3e2b5b69ba0831f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26664
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The primary pipe can drive DDI A (eDP) without the Power Down
Well (PDW). The scalers are inside the PDW, though. To enable
scaling for DDI A, ensure the PDW is active.
When switching between scaled / unscaled modes, we'll have to
reconfigure the whole pipe.
Change-Id: I46318bb74d00a584d268a9d76787f8b26249264d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26663
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The following ports are implemented: HDMI/DVI, VGA, LVDS and DP.
Tested with gfx_test and coreboot on a Thinkpad X200 (GM45).
Change-Id: Ifc05a1516329a61772af84558e5bfceb4d4ca277
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21295
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: Nico Huber <nico.h@gmx.de>
Since we do not know before hand the memory range initialized by FSP memory
init until it completes and as memory gets accessed from within FSP memory
init to migrate FSP from CAR to memory, we need to add this mapping in
coreboot.
Change-Id: I1ce2d489240e6e3686ceb7f6e824e5a94398d47e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/26745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Because of struct sci_source table of events that have to generate SCI or
SMI, <soc/smi.h> was included to kahlee/grunt gpio.c files. However, new
code transfered most of SCI/SMI/interrupt programming (with exception of
events not associated to a GPIO pin), and therefore smi.h is now included
by gpio.h. It was also added to some other files where they are not needed.
Only smihandler.c truly needs it. Remove the includes.
BUG=b:78139413
TEST=build and boot grunt.
Change-Id: I64cf0796103a5226ddace03d05d94160bf93aa69
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26721
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change may require board_mismatch=force if mainline firmware was
used. If vendor firmware was used this patch remove flashrom confusion
since system product name reported by SMBIOS tables will match mainline
firmware.
Change-Id: Ic6942bc36df1a02db61b035ddc892585688aa27b
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/26757
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently the throttle event handler method THRM is defined as an
extern on the intel bd82x6x and lynxpoint chipsets, then defined
again in the platform with thermal event handling. In newer versions
of IASL, this generates an error, as the method is defined in two
places. Simply removing the extern causes the call to it to fail on
platforms where it isn't actually defined, so add a preprocessor define
where it's implemented, and only call the method on those platforms.
This also requires moving the thermal handler, which now includes
the define to before the gnvs asl file.
TEST=Build before and after, make sure correct code is included.
Change-Id: I7af4a346496c1352ec20bda8acb338b5d277d99b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26123
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Along with other patches submitted for review to get the chipset
parts working, this allows Linux or other OS to use a TPM module
plugged into the 20-pin LPC header on the board, by exposing its
presence through the ACPI and PNP tables.
This patch adds to the Kconfig and devicetree.cb files.
Tested with the TPM/FW 3.19 and the trousers tools.
Change-Id: I8c1aea245f81fa44a6bdd5301bbee958cbcdfaaa
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The file cache_as_ram_ht.inc is used across a variety
of CPUs and northbridges. We need to split it anyway
for future C_ENVIRONMENT_BOOTBLOCK and verstage work.
Split and rename the files, remove code that is globally
implemented in POSTCAR_STAGE framework already.
Change-Id: I2ba67772328fce3d5d1ae34c36aea8dcdcc56b87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reducing two AGP aperture windows from default 256 MiB to
chipset minimum 4 MiB releases 504 MiB of unused MMIO space.
Thus we can decrease MMIO space reserve from 1024 MiB to 512 MiB.
Supported CPUs are 32-bit with PAE, so there is a little reason
to avoid overlarge MMIO region.
Change-Id: I34818e1ca36058309c7c5c295992ba6dda154acc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
With implementation of LATE_CBMEM_INIT, top-of-low-memory
TOLM was adjusted late in ramstage. We do not allow that with
EARLY_CBMEM_INIT so the previous maximum of 1024 MiB of MMIO
space is now used with statically set TOLM.
Also remove support code for the obsolete LATE_CBMEM_INIT
this northbridge used.
Change-Id: Ib3094903d7614d2212fbe1870248962fbc92e412
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
