The included .c file also pulled in ancient files
amdk8/pre_f.h and amdk8/raminit.h
Do a dirty copy-paste to work around that.
Change-Id: Ie89a5f91d5234f1ef334d30a43dd56e0b722b5ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch makes Sona follow the standard LED pattern for single LED
systems. Sona has two LEDs but both are connected to the same pin.
This increases userbility because LEDs are visible from each side
and users don't have to learn two different sets of patterns (i.e.
one for left LED and onother for right LED).
* Charging Amber on (S0/S3/S5)
* Charging (full) White on (S0/S3/S5)
* Discharge in S0 White on
* Discharge in S3/S0ix Alternate pulse (up-down-off-off)
* Discharge in S5 Off
* Battery Error Amber on 1sec off 1sec
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:80135370,b:74940319
BRANCH=none
TEST=Verified LED behaviors in S3, S0, charge, discharge on Sona
Change-Id: I1bd53c7c60529a8b813eabc338876af6d089ec82
Reviewed-on: https://chromium-review.googlesource.com/1074226
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Jack Huang <jachuang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Grunt and Careena hardware does not support sourcing 3A over USB-C
so reduce what we advertise to 1.5A.
BUG=b:78908554
BRANCH=none
TEST=Grunt advertises 1.5A Source Cap on both ports
Change-Id: Ifd3ddf45445ae69c5988dee4f66f21056b4b0f96
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1077096
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
We're doing a bit of refactoring to break out factory mode into its own
file. Now factory reset and rma reset will be two methods of entering
factory mode. Factory mode can be disabled with the disable_factory
vendor command.
Factory mode means all ccd capabilities are set to Always and WP is
permanently disabled. When factory mode is disabled, all capabilities
are reset to Default and WP is reset to follow battery presence.
This adds 56 bytes.
BUG=none
BRANCH=cr50
TEST=verify rma reset will enable factory mode.
Change-Id: I21c6f7b4341e3a18e213e438bbd17c67739b85fa
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1069789
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Using the p256 curve is beneficial, because RMA feature is currently
the only user of the x25519 curve in Cr50, whereas p256 support is
required by other subsystems and its implementation is based on
dcrypto.
The p256 public key is 65 bytes in size, appropriate adjustments are
being made for the structure storing the server public key and the key
ID.
The compact representation of the p256 public key requires 33 bytes,
including the X coordinate and one extra byte used to communicate if
the omitted Y coordinate is odd or even.
The challenge structure communicated to the RMA server allows exactly
32 bytes for the public key. To comply, the generated ephemeral public
key is used in compressed form (only the X coordinate is used).
For the server to properly uncompress the public key one extra bit is
required, to indicate if the original key's Y coordinate is odd or
even. Since there is no room for the extra bit in the challenge
structure, a convention is used where the generated ephemeral public
key is guaranteed to have an odd Y coordinate.
When generating the ephemeral key, the Y coordinate is checked, and if
it is even, generation attempt is repeated.
Some clean up is also included: even with debug enabled, generated
challenge is displayed only once as a long string, convenient for
copying and pasting.
The new feature is not yet enabled, p256 support on the RMA server
side is not yet available.
Enabling p256 curve for RMA authentication saves 5336 bytes of the
flash space.
BRANCH=cr50, cr50-mp
BUG=b:73296606
TEST=enabled CONFIG_RMA_AUTH_USE_P256 in board.h, generated challenge
and verified matching auth code generated by the rma_reset
utility.
Change-Id: I857543c89a7c33c6fc2dc00e142fe9fa6fc642cf
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1074743
Reviewed-by: Randall Spangler <rspangler@chromium.org>
ID pins are considered additional KSOs while keycode scanning works
for the existing KSI0 ~ KSI7. While diriving ID pins, the state of
interconnection between ID pins and KSI pins could be used for
identifiers to tell keyboard itself. (e.g. US, Japan,and UK keyboard)
BRANCH=master
BUG=b:80168723
TEST="make -j buildall"
TEST=Verified 5 distinct keyboard samples w/ different Language ID values
on the same reworked Coral, which VOL_UP and VOL_DOWN were reworked
for ID pins. crrev.com/c/1053617 is my experimental patch on top of
this for further verification
Change-Id: I1d6e647df74c50d60bc1264c045b2587d0bf23d8
Signed-off-by: paris_yeh <pyeh@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1068951
Commit-Ready: Paris Yeh <pyeh@chromium.org>
Tested-by: Paris Yeh <pyeh@chromium.org>
Reviewed-by: Paris Yeh <pyeh@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Instead of requiring the user to enter their root password to set the
created files to their user, create a new user inside the docker
container with the correct UID & GID and build with that.
Change-Id: Ibbeff00211e8cf653f48204d285e06bca39b5fd2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Users can have non-default configurations as to how git diff et al are
presenting file names in diffs (default: a/ and b/ prefixes). checkpatch
expects that and trims the first element, so enforce that configuration
for the diff that's sent into it.
Change-Id: I099795119456a73c900b31ce191c2d9e898a5c7e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
The SPD files will be common to many of the mainboards, so move them out
of grunt and into the variants/baseboard directory.
BUG=b:80106042
TEST=Build grunt, make sure spd.bin is the same.
Change-Id: I53975a46a8c7d7e519bb6f7ef6ccd0b817ac4c92
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Add more subdirectories and index.mds.
* Move "getting started" and "lessons" into sub-directories.
* Move "NativeRaminit" into northbridge/intel/sandybridge folder.
* Move "MultiProcessorInit" into soc/intel/icelake folder.
* Reference new files
Change-Id: I78c3ec0e8bcc342686277ae141a88d0486680978
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26262
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ec_boot_mode is used for flashing EC on STM32 and NPCX chips.
The ec_boot_mode pin is an open-drain GPIO. Doing save/restore is
destructive. For example, if DUT is unpowered (ec_boot_mode is "on"),
doing save/restore will force it outputting to "on". We should not
put it to the save/restore list. Instead, set it back to "off" on
exit.
BRANCH=none
BUG=b:80305869
TEST=Ran flash_ec when DUT is unpowered -> failed as expected.
Reran again when powered. Checked EC UART showed-up afterward.
Change-Id: Iecf4b663fe9ae75a673a29a66505a4121d29888c
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1073646
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We have determined the checks to run for board_is_first_factory_boot.
This change updates cr50 to check for those conditions and enable ccd
when the system determines that it is first boot in the factory. This
will check that the board id is erased and the inactive image is a GUC
image.
The factory updates Cr50 from the GUC image, because those GUC images
don't have support for everything they need to do in the factory. To
determine that cr50 just recovered from that factory update, it will
check that the GUC image is still in the inactive region and no board id
is set.
There are 2 images installed in GUC 0.0.13 and 0.0.22, so cr50 will
check these versions. Future GUC images will have a field in the header
declaring that they are a GUC image. I still need to create the GUC
field in the header and check that in inactive_image_is_guc_image.
Factory mode can't be enabled on deep sleep resume. It is only enabled
after power-on reset or hard reset.
This change also moves factory stuff into a factory_mode file instead of
keeping it in board.c
This adds 200 bytes.
BUG=b:77543904
BRANCH=cr50
TEST=Verify factory mode is only enabled when cr50 recovered from
reboot not deep sleep resume, 0.0.13 or 0.0.22 are in the inactive
region, and the board id is erased.
Change-Id: Ibece878049658493e8ad159121ada63d7a6f6b79
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1059864
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
There is a potential loop:
(1) We throttle AP when we see under-voltage.
(2) VBAT bumps because throttling starts. From our experiment,
AP throttling saves ~1A, and thus VBAT increases by ~80mV.
(3) VBAT hasn't hit BAT_LOW_VOLTAGE_THRESH for BAT_UVP_TIMEOUT_US,
so we stop throttling.
(4) VBAT again drops below BAT_LOW_VOLTAGE_THRESH.
(5) Go back to (1).
So let's introduce a hysteresis to under-voltage throttling.
We stop throttling only when we are confident that even if we stop
throttling, the battery voltage will stay above BAT_LOW_VOLTAGE_THRESH.
BUG=b:73050145, chromium:838754
BRANCH=scarlet
TEST=manually test on scarlet
Change-Id: Ic0c17a7d37d5d6ee38c7b19f9b65d17421e55cbc
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1070568
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
we normally try to find out a few things about a battery (like charge
level) before actaully applying charging power to it. when the
battery is completely discharged, the controller on the battery can't
respond as it is not self-powered. so, we have to avoid all
operations that depend on the battery responding in the battery
discovery/initialization path.
as long as we report that a battery is present and it is not
responsive, the charger task will enter ST_PRECHARGE which means it'll
provide a "precharge" current to the battery to try to talk to it.
this allows the battery's controller to report battery parameters
allowing our charger task can do the right thing.
BUG=b:79354967
BRANCH=none
TEST=atlas now discovers the discharged battery reliably
Change-Id: I5e5a3abda07508eb791b712fb2f9b9f5fe383e07
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1065492
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
Use a queue now for sync events, this will allow multiple interrupts to be
called before the motion sense task executes. The events (including
timestamps) get stored in a small queue. 8 events for the queue size should
be plenty, most applications will have latency concerns anyway once we
get a couple of queued up events.
Also changed the init function to be a little bit more robust to race
conditions. Added count argument to the "sync" simulation command to test
the queue behavior.
BRANCH=master
BUG=b:73551961, b:67743747
TEST="sync 4" yields 4 events on the AP, whereas before it would only
give the AP the last event.
Change-Id: I9fcb1fb8b35eb5f8ffcc21afbfcb0f0d9bc33804
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1065149
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Decreases verification time from 923ms to 785ms.
Optimized version do not really help in RW, as they just increase
the image size (which also increases verification time).
BRANCH=fizz
BUG=b:77608104
TEST=make BOARD=fizz -j, flash fizz, check timing.
Change-Id: Ia8c36c35c0321c1995dc1cede7b27f7636037795
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1075908
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
keyboard_disconnect was called without keyboard_init being called and in this
case keyboard_havechar returns true because i8042_data_ready_ps2 is
dereferencing uninitialized variable ps2_fifo from within fifo_is_empty causing
keyboard_disconnect to be stuck in this while loop.
while (keyboard_havechar())
keyboard_getchar();
BUG=b:80299098
TEST=Check if the normal mode path in depthcharge is not causing a hang
Change-Id: I944b4836005c887a2715717dff2df1b5a220818e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/26590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some devices have GPIO pins that control USB port power connected to
the EC, so they cannot be toggled by ACPI. This patch adds a memory
map between the EC and ACPI that can be used on such devices. It can
hold the power state of up to 8 USB ports. Currently, only dumb power
ports are supported.
BUG=chromium:833436
BRANCH=fizz
TEST=On a fizz that runs BIOS with EC_ACPI_MEM_USB_PORT_POWER mapped,
check that both reads and writes are propagated.
Change-Id: I413defcb9e4d234fea7f54d46b6b8a1a10efa31e
Signed-off-by: Emil Lundmark <lndmrk@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1069273
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This change adds and updates headers in all of the northbridge files
that had missing or unrecognized headers. After this goes in, we can
turn on lint checking for headers in all northbridge directories.
Change-Id: I8cd7c04ddb8e58946dcdf9c7c125e23698647a73
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This change adds and updates headers in all of the southbridge files
that had missing or unrecognized headers. After this goes in, we can
turn on lint checking for headers in all southbridge directories.
Change-Id: I09614730bfd4db923dda103bd07bab02836a4c92
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This change adds and updates headers in all of the soc files that
had missing or unrecognized headers. After this goes in, we can
turn on lint checking for headers in all soc directories.
Change-Id: I8b34dcd10c692f1048bd8d6c0fe3bfce13d54967
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Currently the throttle event handler method THRT is defined as an extern,
then defined again in the platform with thermal event handling. In newer
versions of IASL, this generates an error, as the method is defined in
two places. Simply removing the extern causes the call to it to fail on
platforms where it isn't actually defined, so add a preprocessor define
where it's implemented, and only call the method on those platforms.
Change-Id: I6337c52edaf9350843848b31c5d87bbfca403930
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Since the PS8751 is now driving the EN_SNK GPIO on the PPC, we cannot
reset without a battery otherwise we will brown out the board.
BRANCH=none
BUG=b:78896495,b:78021059
TEST=verified with reworked board.
Change-Id: Ibadf46de922c49f5fdd08c43991e71f852ff7600
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067711
Setting up the panel fitter for a second Pipe is omitted in order for
the configuration for the first pipe to remain valid. It is currently
unknown how the system would behave in such situation.
Change-Id: I4949fbb5356bd244d3d6f3eec71847b6e683079a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25409
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: Nico Huber <nico.h@gmx.de>
Hardware doesn't like minimal horizontal gaps. Scale to full width if
the difference is at most three pixels.
Also, don't scale to odd widths. At least Haswell doesn't like it.
Change-Id: Ic1484eda0f6022cd8a37611fdfb9d2c50b390b72
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26647
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
If we are supposed to show the test image longer than 8s, show a
different cutting of the image every 4s.
Change-Id: I8ce22c4f8dc2615ae1dbe8c39ad249aa959a3005
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23166
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
