Fixed resources have to be registered early during
read_resources() phase, such that device allocator
will avoid them.
Change-Id: I3c120cfb96c185f0052b9b3cdd93eeed0f712491
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
- Add some directories and files to the ignore list
- Add the LGPL as a recognized header. It's used in some files that
were pulled into coreboot from other sources.
Change-Id: I53423205f1cbf142a294ee5d24e885741a44dfcd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This change adds and updates headers in all of the mainboard files that
had missing or unrecognized headers. After this goes in, we can turn on
lint checking for headers in all mainboard directories.
Change-Id: Ibe038a8f7468253b21fd2ac90c045d0c9cc89dfc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
It matches the SS path, in which both port-0 and port-1 connect to the
hub.
BRANCH=none
BUG=b:74395451
TEST=Tried plugging USB 2.0 disk to port-0 and port-1, both bootable.
Change-Id: Ic0264657fbe126242a419ef33ce07bc2599375ee
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1082981
Reviewed-by: Douglas Anderson <dianders@chromium.org>
vbutil_kernel already supports 64bit arm architecture,
but it just allows "aarch64" option. However other script,
for example build_kernel_image uses ARCH environment variable,
which for arm64-generic overlay is defined as "arm64".
So vbutil_kernel will refuse the call.
BUG=None
TEST=run vbutil_kernel --arch=arm64
Check that the "Unknown architecture string: arm64" is gone
BRANCH=None
Change-Id: I94c547d6b6940ab8c622a6b8cff49b5f83c1fcad
Reviewed-on: https://chromium-review.googlesource.com/1080529
Commit-Ready: Adam Kallai <kadam@inf.u-szeged.hu>
Tested-by: Adam Kallai <kadam@inf.u-szeged.hu>
Reviewed-by: Mike Frysinger <vapier@chromium.org>
The EC needs to enable/disable the NVMe power rails on bootup and
shutdown. This commit just adds these controls in during chipset
startup and shutdown.
BUG=b:73258414
BRANCH=poppy
TEST=Flash nocturne, verify that rails come up on boot up and are turned
off on shutdown.
Change-Id: I3dc8c17255294c0bbf8638ea3ee3fcfaa321929b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1067947
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@google.com>
these changes reflect the hardware changes made between version 0 and
version 1 of the atlas board.
note: these changes are not backward compatible - version 0 of atlas
is no longer supported.
BUG=b:78309559
BRANCH=none
TEST=works fine on atlas version 1
Change-Id: Ia519f161c66066e02e9ddce7560a8fe2b7e74882
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1045730
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
There was a recent change to save the manual setting of charge current
and voltage, however it was done so assuming that the parameters were
set via the host command interface. (CL:922069) However, there are times
where the charge voltage/current would like to be manipulated without
booting the AP. This commit simply makes the EC console command work
again.
BUG=None
BRANCH=None
TEST=make -j buildall
TEST=Flash nocturne, `chgstate idle on; charger current 256; charger
voltage 7400`; verify that the charge voltage and current is actually
changed.
Change-Id: Id250d9704f8509162518495556603950248fb267
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1081120
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Currently, the power LED pulses in sleep state on Pantheon. This patch
makes it blink with 25% duty. That is, the LED turns on for 1 sec then
turns off for 3 sec.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:79733195
BRANCH=none
TEST=make BOARD=nami
Change-Id: I0ebd2778b9b6551f2313ea8f8648c69324e02368
Reviewed-on: https://chromium-review.googlesource.com/1069337
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Split battery info between baseboard and board, following the
Octopus example. This will allow Grunt and Careena to define their
own lists of supported battery types.
This also adds CONFIG_BATTERY_REVIVE_DISCONNECT support, and
checks the charge/discharge FET status.
BUG=b:79704826,b:74018100
BRANCH=none
TEST=Grunt still boots ok.
Change-Id: I6e82ac5e48f9aabf59b63add253108513f0a6b60
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1072039
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Fix regression after commit
6032018 console: only allow console messages after initialization
Fix it so that the two remaining platforms that are being
moved to EARLY_CBMEM_INIT have chance to send board-status
with non-dirty tags before and after the conversion is made.
This also leaves us with a record in the repository where
LATE_CBMEM_INIT was known to work on some platform.
Change-Id: Ie874f986a2c474bba117d7d6ae959decec8060a8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26743
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The driver only supports streaming images flipped horizontally
and vertically. In order to ensure that all current users will
be fine if or when support for upright streaming is added,
require the presence of the "rotation" control now.
BUG=None
BRANCH=None
TEST=Verified the MIPI and USB camera function on DUT board
Change-Id: I7e3abdea9071da1a089c7165f6bb609428090792
Signed-off-by: Lai, Jim <jim.lai@intel.com>
Reviewed-on: https://review.coreboot.org/26727
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It now looks like this:
Check that files have license headers (lint-stable-000-license-headers): success
Check for superfluous whitespace in the tree (lint-stable-003-whitespace): success
Check that C labels begin at start-of-line (lint-stable-004-style-labels): success
Change-Id: I9d1f6adebae5b68a51e89c2833f8713f0ffcb616
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Implement method to access the SuperIO's harware monitor (HWM) IO space.
Set the PSU fan using a new CMOS option psu_fan_lvl. Add the CMOS option
to all board that use NPCD378. In case no CMOS is set use the default
fan level 3.
The HWM space can be written to at any time, but the SuperIO has to be
notified that a write is ongoing. After clearing the write-lock bit all
changes are applied at once.
Tested on HP Compaq 8200 SFF.
Change-Id: I56ce7ad1df88638589a577b8a09d5d775557887b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26050
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds all USB ports to the device tree. Additionally, it adds _PS0
and _PS3 ACPI methods for the visible USB A ports, which makes it
possible to control the port power (VBUS) of each port individually.
Change-Id: I80ba090f323fbf9fc2b333b1c647b7dfb3393ff6
Signed-off-by: Emil Lundmark <lndmrk@chromium.org>
Reviewed-on: https://review.coreboot.org/26472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The default setting of the ROP PMIC's V085A output voltage is incorrect
for our application. This commit changes the output voltage to actually
be 0.85V.
BUG=b:80271678
BRANCH=poppy
TEST=Flash nocturne and verify that V085A is ~0.85V.
Change-Id: I3c6c7396bc8b896620aab7e4719f8a14b4a46e4a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1077085
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
An ADC conversion requires ~10 msec. However, if the bq25703 is in low
power mode, then this conversion time jumps to ~55 msec. This CL adds
a method to exit/enter low power mode and adds a call to exit low
power mode prior to starting the ADC conversion. Following the
conversion, low power mode is entered again.
BRANCH=none
BUG=b:79771760
TEST=Connected AC power and verified that EC console error message
'Could not read input current limit ADC' is no longer shown. In
addition, had instrumented this the ADC conversion with GPIO signals
and verified the conversion times before/after exiting low power mode.
Change-Id: I13f36e6261e219adbc8624f71bf7916bbc631b10
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1069768
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
We added a cr50 vendor command to control factory mode. This change adds
gsctool support for using the command.
gsctool -F [enable|disable] can be used to set factory mode. You can't
use it to get the factory mode setting, because factory mode is
indistinguishable from other forms of ccd. The regular ccd info can be
used instead gsctool -I.
BUG=b:77543904
BRANCH=cr50
TEST=none
Change-Id: I715e296c323be20bab0b54a2f94a380b61f74cd2
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1069370
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The factory reset command can be used to enable ccd factory mode. The
command can open ccd if write protect is removed and ccd hasn't been
restricted. Right now we check FWMP and the ccd password before allowing
factory reset. Factory reset cannot be used to get around anything that
disables ccd.
This adds 72 bytes.
BUG=b:77543904
BRANCH=cr50
TEST=Try enabling factory mode using factory reset. Verify setting write
protect, setting the FWMP disable ccd bit, or setting a ccd password
prevents factory reset from enabling factory mode.
Change-Id: I6e203bf6068250f009881aa95c13bc56cb2aa9e7
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1069369
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Now that initramfs, firmware updater, and auto-updater are all using
dynamically linked programs, there's no need to produce a static
build of crossystem anymore.
BUG=chromium:765499
TEST=precq passes (includes vmtests w/AU)
BRANCH=None
Change-Id: I5aa123e662040ff5d9f2328c0f036b648fc629fb
Reviewed-on: https://chromium-review.googlesource.com/667881
Commit-Ready: Mike Frysinger <vapier@chromium.org>
Tested-by: Mike Frysinger <vapier@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Don Garrett <dgarrett@chromium.org>
It's a white list (configured through $(top)/.clang-format-scope) with
the expectation that the list will grow over time.
Once everything is covered, we can turn off the white-listing and keep
everything enforced.
To not drive people crazy, only check the files their commit touched.
Change-Id: I52c7ea73fd36aaa46c0bfce928158e1cd6304540
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Recent changes to field lengths in include/memory_info.h resulted in
a mismatch between the memory_info struct the MRC blob writes to and
the struct used by coreboot to parse out data for the SMBIOS tables.
This mismatch caused type 17 SMBIOS tables to be filled incorrectly.
The solution used here is to define the memory_info struct as expected
by MRC in the pei_data header, and manually copy the data field by field
into the coreboot memory_info struct, observing the more restrictive
lengths for the two structs.
Test: build/boot google/lulu, verify SMBIOS type 17 tables correctly
populated.
Change-Id: I932b7b41ae1e3fd364d056a8c91f7ed5d25dbafc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/26598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
When the i210 MACPHY is operated in the SERDES Backplane mode (which
depends on the programmed firmware image), its PCI-ID will be 0x1537.
This does however not change the programming interface for the MAC
address.
Therefore add this new PCI-ID to the driver so that the MAC address can
be programmed in this operation mode as well.
Change-Id: I608535202c49e40690381c2b2ab26322d62cfb37
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/26683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The FPMCU is using the standard cros-ec-spi interface on GSPI1.
Configure the GPIOs controlling the MCU too.
We need to be able to wake from S3 on the MCU interrupt, re-configure
GPE0 DW0 to point to GPP_C bank.
BRANCH=poppy
BUG=b:79666174
TEST=exercise the cros_ec interface, e.g. 'ectool --name=cros_fp version',
verify the MKBP events by doing 'ectool --name=cros_fp fpmode fingerup'
then 'ectool --name=cros_fp waitevent 5 10000', toggle the other GPIOs
with the flash_fp_mcu script.
Change-Id: Ib417dcf84cda8e354060785cd16a7b6b812148d5
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/26684
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boards could choose a high ROM_SIZE that would result in an MTRR config
that conflicts with other resources. Thus, always use the filtered
CACHE_ROM_SIZE.
Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Most, if not all, chipsets have MMIO between 0xfe000000 and 0xff000000.
So don't try to cache more than 16MiB of the ROM. It's also common that
at most 16MiB are memory mapped.
Change-Id: I5dfa2744190a34c56c86e108a8c50dca9d428268
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26567
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As far as I can see this Kconfig option was used wrong ever since it
was added. According to the commit message of 107f72e (Re-declare
CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary
to prevent overlapping with CAR.
Let's handle the potential overlap in C macros instead and get rid
of that option. Currently, it was only used by most FSP1.0 boards,
and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?).
Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently, console_init calls cflush() twice, once before
"Console is enabled" string is printed, once afterwards.
The reason is that firmware_ECBootTime looks for that string,
and it may get corrupted/interleaved with others if the EC
is busy during initialization.
The problem here is that the CONSOLE task may have higher
priority than other tasks (for good reasons), but, on boot,
there are other more critical tasks that need to run (e.g.
RW image verification), rather than busy-looping waiting for
the console to be flushed.
By fixing firmware_ECBootTime to not look for the string anymore,
we do not need those 2 console flush.
BRANCH=poppy
BUG=b:35647963
BUG=chromium:687228
CQ-DEPEND=CL:1075832
TEST=Flash staff, see that RW verification starts at 0.001037
instead of 0.028087 (=> 27 ms faster).
TEST=test_that -b $BOARD $IP firmware_ECBootTime
Change-Id: I794e48eb69cc647c4595fd80265adee4a434d566
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1073180
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We need to control the console channels for cr50 testing, so we need
access to chan even if the console is restricted. Make chan a safe
command so it is always accessible.
BUG=b:80319784
BRANCH=cr50
TEST=on cr50 make sure the command is accessible no matter the console
state
Change-Id: Ia392f32c319c1acf9bb97b97d7f72c7e56427ce3
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1079452
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
