Beside updates to the framebuffer offset in memory, Setup_FB() allows
changes to size, position, tiling and rotation, too. Basically every-
thing but changes to BPC (which would need an update in the transcoder
configuration on pre-Broadwell hardware, too).
It is not clear if the updates work fully synchronous on all hardware
generations. Though, tests on APL have shown a glitch free transition
so far.
Change-Id: I3c8352315390d9c4d2fb2a7e09355b5fe4089421
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23165
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The surface register arms the other plane registers for a synchronous
update and should be written last.
Change-Id: I723cdf7e319c62004d3c4db80959d8b14f553ff6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23164
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Validate_Config() had the full `Port_Config` as parameter, though we
only accessed the modeline. Make that explicit so we can also call it
when we don't have the full config available.
Change-Id: Ia4620d1ffa1a3cd098d721d84f2453f2dc19da2a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23163
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
We assumed that the panel fitter (or pipe scaler) is already turned off
by default. But that won't be true if we only update the framebuffer
configuration without resetting the whole pipe.
Change-Id: I442d2a6a553d5d91187a4d09c8bc5fdd693eb4f4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23162
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
For tiled modes, the offsets add to the stride. To keep things simple,
we always assume that they are accounted for (even in linear mode).
To make the panning visible, the offsets are added in `gfx_test` and
the test image is drawn larger by two times the offsets. Also add the
new parameters to Dump_Configs() along with the forgotten tiling and
rotation parameters.
Change-Id: I5d1e1f2ed8b1872a2b82be23a6a622d948f7831f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22866
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
We used to add the second mapping for a 90 degree rotated frame-
buffer at `FB.Offset + GTT_Rotation_Offset` and patched the offset
when configuring the pipe. Instead, we expect the final offset in
`FB.Offset` (which should include `GTT_Rotation_Offset` when using
the default framebuffer setup.
Change-Id: I321a3db3af4b21eefbfc1bf0c2a7005feaf83c7a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22864
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
In RSA, we often need to actually compute (a*b)+c+d: provide some
assembly optimized functions for that.
With -O3, 3072-bit exponent, lower verification time from 104 ms to
88 ms on STM32F072 @48Mhz.
BRANCH=poppy
BUG=b:35647963
BUG=b:77608104
TEST=On staff, flash, verification successful
TEST=make test-rsa, make test-rsa3
TEST=make BOARD=hammer test-utils test-rsa3, test on board
Change-Id: I80e8a7258d091e4f6adea11797729ac657dfd85d
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1071411
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Dumb USB ports do not have the same notion of charge mode as smart
ports. However, the header common/usb_charge.h declares a function for
changing charge mode that the dumb USB port power implementation does
not define. Instead, it defines a similar function with a different
name, albeit with other allowed values for its second parameter.
This patch makes the names the same so the function can be used by
simply including the aforementioned header file.
BUG=none
BRANCH=fizz
TEST=emerge-fizz chromeos-ec
Change-Id: I87863f87f32f538cc1c723d9299afcc7353e1852
Signed-off-by: Emil Lundmark <lndmrk@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1069272
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This will be called after touchpad firmware is updated. "Full
initialization" will trigger auto tuning.
This function can also be called by console command `touchpad_st
calibrate`.
BRANCH=none
BUG=b:70482333
BUG=b:78483107
TEST=manual
Signed-off-by: Wei-Han Chen <stimim@chromium.org>
Change-Id: I336dfa79ae5133750dc90ba07cbe9fc81318e84e
Reviewed-on: https://chromium-review.googlesource.com/1049765
Commit-Ready: Wei-Han Chen <stimim@chromium.org>
Tested-by: Wei-Han Chen <stimim@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
On Ibex Peak (and maybe also on other platforms), when the AltMeDisable
bit is set (-S or -s option of me_cleaner), the ME PCI device disappears
from the bus and its configuration space is all ones.
This causes a freeze in intel_me_status(), as coreboot tries to access
an out of bounds array element.
Change-Id: I957abebe1db15ec2c9a2b439f0103106bfa56b33
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/26601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
tcpm_get_chip_info does not modify the parameter info if the
function is not implemented on the given chip.
This has a interesting side effect on Kevin, where, for whatever
reason, info's value ends up being 1, and causes unaligned access
exception:
[0.039 TCPC p0 init ready]
=== PROCESS EXCEPTION: 06 ====== xPSR: 61000000 ===
r0 :00000000 r1 :28000000 r2 :00000001 r3 :00000000
r4 :00000000 r5 :00000000 r6 :00000000 r7 :00000000
r8 :200c60f4 r9 :00000000 r10:100c0c3c r11:00000000
r12:200c52ed sp :200c5320 lr :100a9c71 pc :100abd5a
Unaligned
mmfs = 1000000, shcsr = 70008, hfsr = 0, dfsr = 0
BRANCH=none
BUG=none
TEST=On ToT make BOARD=kevin -j; flash, kevin boots
Change-Id: Ie7e758d5fb8c31180f36b073b635e54cc720a8a0
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1073179
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We multiply 2 32-bit numbers (and not 64-bit numbers), and then add
another 32-bit number, which makes it possible to optimize the
assembly and save a few instructions.
With -O3, 3072-bit exponent, lower verification time from 122 ms to
104 ms on STM32F072 @48Mhz.
Optimized mac function from Dmitry Grinberg <dmitrygr@google.com>.
BRANCH=poppy
BUG=b:35647963
BUG=b:77608104
TEST=On staff, flash, verification successful
TEST=make test-rsa, make test-rsa3
TEST=Flash test-utils and test-rsa to hammer => pass
Change-Id: I584c54c631a3f59f691849a279b308e8d4b4b22d
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/449024
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This patch adds RMA shared secret generation support using the p256
curve. It is not a simple shoe in replacement for the x25519 because
of a different key representations. This new code uses openssl library
for all calculations.
A new option is being added to indicate that p256 is supposed to be
used, the new server Key ID value is used for p256, which allows to
pick the correct curve when parsing the previously generated
challenge.
BRANCH=none
BUG=b:73296606
TEST=verified that the same secret value is generated on the client
and server side when using either x25519 or p256 curves.
./rma_reset -t
./rma_reset -c <challenge generated by the previous command>
./rma_reset -t -p
./rma_reset -c <challenge generated by the previous command>
Change-Id: I9b21b5ae389480d92f0f663fbb846b0f27b15de1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1073757
Reviewed-by: Randall Spangler <rspangler@chromium.org>
These pins should not have pull downs configured in standby state as that
can cause contention on the termination circuitry and lead to incorrect
behavior as per Doc# 572688 Gemini Lake Processor GPIOTermination
Configuration.
Furthermore, some of these pins were configured with normal termination
of None which would as per above mentioned document lead to a standby
termination of None anyways.
Instead of pull downs, use the IOSSTATE setting for driving low
via the Tx mode.
BUG=b:79874891, b:79494332, b:79982669
BRANCH=None
TEST=Flashed image and booted to OS on Yorp. Touchscreen does not
consume power in suspend state.
Change-Id: I7dcf3691b969d018b3cfb6af3f7467c9b523fee5
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/26491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Max98373's NHLT capture configuration is used for IV feedback for
DSM algorithm.
Feedback is 4-channel data. Without this configuration below error
is seen in dmesg:
[ 315.784250] snd_soc_skl 0000:00:1f.3: Blob NULL for id 0 type 3 dirn 1
[ 315.784263] snd_soc_skl 0000:00:1f.3: PCM: ch 4, freq 48000, fmt 32
So, update nhlt configuration accordingly.
BUG=b:79362472
TEST=Audio playback works with IV feedback enabled
Change-Id: I75434a63fe030ed9bb963c6d300d833a8e7d2d66
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26384
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of just checking the immediate parent for an device name,
walk up the tree to check if any parent can identify the device.
This allows devices to be nested more than one level deep and
still have them identified in one place by the SOC.
The recursive method calling this function has been changed to
handle a null return from acpi_device_name and abort instead of
continuing and perhaps forming an invalid ACPI path.
Change-Id: Ic17c5b6facdcb1a0ac696912867d62652b2bf18e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Saves another ~1300 bytes of flash size, as the touchpad
hashes can now be computed in blocks of 4K, instead of 1K.
This costs 3K of SRAM, which we would not otherwise need on
hammer.
wand can only fit 2k PDU, so let's stick to that.
Also, make sure that util/gen_touchpad_fw is regenerated when the
configuration option changes (touchpad FW size, PDU size). Sadly,
this will still break bisection from commit after this CL, to
before this CL.
BRANCH=poppy
BUG=b:80167548
TEST=make buildall -j
TEST=make BOARD=hammer/staff/wand/whiskers all tests -j
TEST=Copy new staff image with old touchpad FW to DUT, verify that
FW can be updated.
Change-Id: Ic1763684da730dc986bbbcb3312088c8208c84b5
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070953
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Some tests cannot be built on some boards (not enough SRAM,
unusual configuration, etc.). Instead of the long list of
exceptions in test/build.mk that we currently use, allow
each board (or chip) build.mk to set test-list-y, and
only use the default list if it is unset.
BRANCH=poppy
BUG=b:80167548
TEST=make buildalltests -j
Change-Id: I803c691f419451aad4396529302a4805cbe3f9b5
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1074572
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The default interrupt control for GPIO pins within stoneyridge is for
edge triggered, high. However, sometimes these need to change, or maybe
the interrupt needs to be reported or delivered. This was the case of
platform grunt, where the interrupt related bits were being changed
afterwards. Ideally all the bits should be programmed through the same
procedure. Create several PAD_INT definitions (for general configuration,
for trigger configuration and for interrupt type configuration) and change
function sb_program_gpios() to accept the output from PAD_INT_XX and
program all the necessary bits while keeping compatibility with other
PAD_XX definitions.
BUG=b:72875858
TEST=Add code to report GPIO and interrupt configuration, build grunt and
record a baseline. Add new code, rebuild grunt and record a test output.
Compare baseline against test, there should be no change in GPIO or
interrupt programming.
Remove code that reports GPIO/interrupt configuration.
Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This board was used a test target for the x4x DDR3 raminit patches and
has an easy to access DIP8 socket.
What is tested and works:
* S3 resume
* PEG, PCI, USB, SATA
* Sound
* Ethernet
* Native graphic init (textmode and linear fb) on the VGA output
* Passing memtest86+ with 2 2Rx8 4G dimms
* PS2 Keyboard
* Flashing coreboot internally from vendor BIOS.
What does not work:
* Running dram at 533 MHz (limited at 400MHz currently)
Tested with two 4G dual rank DDR3 dimm, booted SeaBIOS and Linux
4.10.
Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20003
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
memchr does not take into account end of string, so the test
`memchr("123", '4', 8)` actually does a buffer overflow. On some
boards, a '4' might be found in the 4 bytes that follow "123", and
the test might fail.
Fix another potential overflow as well.
BRANCH=none
BUG=none
TEST=Flash test-utils to hammer, test passes
Change-Id: I53755c0855bbd5b180801e4198341de1cec7b425
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1071409
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is mostly a clean up and refactoring change, which will make it
easier to extend rma_reset to supporting more EC curves.
BRANCH=none
BUG=b:73296606
TEST=verified that the same secret value is generated on the client
and server side by running
./rma_reset -t
./rma_reset -c <challenge generated by the previous command>
Change-Id: I15c010a4a62306bfaa56b97936318854b28a4945
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1073756
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When invoking make with DEBUG=1 add '-g -O0' to the compiler
invocation to facilitate debugging with gdb.
BRANCH=none
BUG=b:73296606
TEST=verified that building with DEBUG=1 adds '-g -O0' to the compiler
invocation.
Change-Id: Idd80bd481091b91683200c78fe49dc7e9783a730
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1073755
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There are still more ifdef than can be added: this just takes out
the low hanging fruits.
BRANCH=poppy
BUG=b:35647963
TEST=make buildall -j, see that we gain from 0 to 64 bytes on many
boards.
Change-Id: Ibe85b8bfa5d5c22c160e4a6656104256067beee9
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070948
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In rare cases, it is useful to be able to build tests for all boards:
buildall only builds the main image, but -paladin builders also builds
test cases for each board.
Also remove/fix tests for boards that currently fail.
BRANCH=none
BUG=b:35647963
TEST=make buildalltests -j, wait a long time, tests pass.
Change-Id: Id6d978705a40a2045731cb08ad2ca5d62cc12ebb
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1072218
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Allow setting password from the AP, but not from USB. Remove the old
password control logic, which is no longer needed.
Allow open if:
- Not explicitly blocked
- Not blocked via FWMP
- One of the following is true:
- A password is set
- Battery is removed (also doesn't require physical presence)
- Dev mode is on, and request came from the AP
Reduces cr50 binary by 152 bytes.
BUG=b:79983505
BRANCH=cr50
TEST=manual, with a CR50_DEV=1 build
ccd oops
ccd lock
ccd unlock -> fails
gsctool -U -> fails from host
gsctool -t -U -> fails from AP
ccd oops
ccd password foo -> fails from console
gsctool -P -> fails from host
gsctool -t -P -> works from AP
ccd get -> confirms password set
ccd lock
ccd unlock foo -> works
ccd lock
gsctool -U -> works from host, if correct password supplied
ccd lock
gsctool -t -U -> works from AP, if correct password supplied
ccd open foo -> works
ccd lock
gsctool -O -> works from host, if correct password supplied
ccd lock
gsctool -t -O -> works from AP, if correct password supplied
ccd oops
ccd lock
(remove battery)
ccd open -> works without physical presence
(reattach battery)
ccd lock
gsctool -O -> works from host
ccd lock
gsctool -t -O -> works from AP, if dev mode is enabled
Change-Id: I364b322d03db250e7dd140767d7a22dbb3ac1eef
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1072957
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This is needed so ccd_open() can see p->flags, for a subsequent
change. No change to existing command behavior or binary size.
BUG=b:79983505
BRANCH=cr50
TEST=gsctool -I still works
Change-Id: I614d8c410e8bc55a5045e253469b2ec222078684
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1072500
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
