Move code that will be common to Grunt and Careena to baseboard
to avoid duplication when creating the Careena board.
Add Careena board files. These are currently just a copy of Grunt
and will be modified for Careena next.
BUG=b:79704826
BRANCH=none
TEST=Grunt still boots ok.
Change-Id: I6dd0035bdd62e92a7f3664120fc6ac3f23a0af4d
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070988
This change moves PL2 override to variant_devtree_update for two reasons:
1. This function was added to basically override devtree settings in
variant specific code. So, it would be a good idea to perform all the
overrides in a single place.
2. Adding a device for performing nami_enable would require changes to
devicetree and special handling for calling this device enable. Thus,
nami_enable was never getting called.
BUG=b:80148703
Change-Id: Ifa24a7b6e99cad2368b3d656a757f26297373121
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This creates a pin-route matrix first and then generates the ACPI
entries based on that. This approach has the advantage of being
simpler (no need for checks on double entries) and requiring less
access to the pci config space.
A few thing that are also fixed:
* Don't declare DEFAULT_RCBA redundantly.
* Only loop over PCI devices on bus 0
* Add a license header to rcba_pirq.c
* Remove inappropriate use of typedefs
* Fix the pin field: needs to be a byte
* Fix the source field: it should either be a byte or a path
(according to Advanced Configuration and Power Interface Specification
rev 2.0c)
Change-Id: Ic68a91d0cb55942a4d928b30f73e1c779142420d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22979
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It doesn't make sense to log post codes from a previous (failed) boot
if we are resuming from S3, since the previous boot has to have been
successful in order to enter S3 in the first place.
While we are at it, use a helper function to combine conditionals and
improve readability.
BUG=none
TEST=boot, suspend & resume grunt
Change-Id: I4f3bb8526a0c8c0ea1efd924628b33c147543b88
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26528
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously, we were unconditionally adding a TYPE_BOOT message to the ELOG
on every boot (even S3 resume) if CONFIG_ELOG_BOOT_COUNT was disabled.
Now that boot_count_read() returns 0 for the !CONFIG_ELOG_BOOT_COUNT
case, the code becomes a bit simpler.
BUG=b:79865267
TEST=firmware_EventLog
Change-Id: I803fa4c3e03b6cc94751cf0ce34b78021ae2124e
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26527
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A pointer to rt_svc_desc_t was defined both in the
function and globally. The innermost definition
hid the global definition which is the one we want
to use so remove the innermost definition to prevent
this
Change-Id: Idabdbc0947178ae83224bd17a9b170df7c278d51
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
The weak pragma was assigned twice to the bl2_plat_handle_post_image_load
definition both in plat/common/ and in plat/arm/common/ this was an error as
it should have only have been defined in plat/common
Change-Id: Id85e14c699cb09ed998d1677f2a172e760911918
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
GPIO APU_BIOS_FLASH_WP_L is first read in ROM stage to determine the
state of the BIOS FLASH Write Protect signal at boot.
The result of this read accumulated in the vboot state that's passed on
to the upper layers of the stack.
Therefore this GPIO must be configured as a "reset stage" GPIO, not
a "RAM" stage GPIO.
BUG=b:79866233
TEST=firmware_WriteProtect
Change-Id: I1d96ab4bbfeaf9db9f74cf0c58cbab2104079bf7
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26498
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In early stages (pre ramstage), we have two notions of devices.
To access the hardware, "simple device" handles are used. These
are plain numbers. To access the static information of the device
tree, we use `struct device` pointers. This is referred to as
DEVTREE_EARLY in the code.
This file is about the latter and its name reflects that the
tree remains unmodified.
Change-Id: I31aeb118615e86026f7111f83a7866d4e7426170
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We need to disable under voltage protection because it prevents us from
enabling the sink path when there is not Vbus on the connector side. We
need to enable the sink path before we hibernate otherwise there is no
power power to get to the charger which will then assert ACOK. Without
this we won't wake up with the ACOK wake when USB power is inserted.
BRANCH=none
BUG=b:79948623
TEST=bip wakes with USB power insertion
Change-Id: Idf16a92dacde63cf943ef68b0258b320d11de44c
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070867
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
PS8751 supports the TCPCI spec for controlling the power source and sink
path, which is done through GPIO0 and GPIO1, respectively, by default.
BRANCH=none
BUG=b:78896495,b:78021059
TEST=verified TCPC drives PPC via reworked yorp board.
Change-Id: Ie1de67495947b787ad9cd5aee0db3ca21bec5a10
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1047796
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The BMI160 driver's init function generates a divide by 0 error
by calling config_interrupt before initializing the range defined
in struct accelgyro_saved_data_t. The explicit error is
generated by macro BMI160_TAP_TH that's called in config_interrupt.
BUG=b:80237518
BRANCH=None
TEST=`make -j buildall`
EVE boots from TOT
Signed-off-by: Sam Hurst <shurst@chromium.org>
Change-Id: I8b7a4a7c63c973bcc639779ee54958f3702f1b36
Reviewed-on: https://chromium-review.googlesource.com/1071847
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
When using larger block sizes (e.g. 4096 bytes), the write operations
take too long, which often causes a watchdog reset.
Fix this by reloading the watchdog after programming
every 64 bytes page.
BRANCH=poppy
BUG=b:80167548
TEST=Copy old touchpad FW to soraka, build staff, make sure FW
can be updated.
Change-Id: Ic6e7a3e3ef63877a4f2d5011e1fb0d49c04177a6
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070952
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
bip also need to enable the sink path when going into hibernate
BRANCH=none
BUG=b:79948623
TEST=on bip, verfied that AC_OK, LID_OPEN, and POWER_BTN all wake the EC
up.
Change-Id: I2c1168f856cc45635b5c76f7ca409007fcf141cc
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1065203
This CL retries reads and writes from/to TPM device if an error
is returned by read()/write(), up to 3 total attempts.
This is useful case of transient TPM communication errors that go
away after a single retry. Without this CL, after such errors the
encstateful key might be regenerated and encstateful data wiped.
BRANCH=none
BUG=chromium:702724
TEST=1) normal boot still works;
2) simulate a single error, verify that it retries.
Change-Id: I259882209df0aad66cd083729f746ea45909922b
Reviewed-on: https://chromium-review.googlesource.com/1067939
Commit-Ready: Andrey Pronin <apronin@chromium.org>
Tested-by: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
I noticed data was getting dropped from my console output on
bip. Adding the cflush fixes it.
BRANCH=none
BUG=none
TEST=ppc_dump 0 on bip works
Change-Id: Ib71cb37c4c8728a7ab958905d3b2627b8c163faa
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070626
Add new port based on autoport.
The board uses a NPCD378 SuperIO, that is full of custom hardware.
The 8MiB flash SOIC-8 can be accessed after cutting of a part of the
DIMM slot holder. The flash IC has no diode, powering a part of the
board while flashing externaly, including the Standby-LED.
The following have been tested and is working:
* Native raminit with up to four DIMMs
* Libgfxinit on DisplayPort
* USB
* EHCI debug
* Serial on RS232
* Ethernet
* PCIe on x4
* PCIe on x16
* SATA
* Booting GNU Linux 4.14 using SeaBIOS 1.11.1 as payload
* Flashing internaly
* PS/2 is working
Untested:
* PCI slot
* LPT port
* VBIOS
* S3 resume
Not working:
* PSU fan managment (runs at 100%)
* Half of SuperIO functionality is unknown
TODO:
* Reverse engineer remaining SuperIO registers
* Reverse engineer SMM
Fixes on follow-up commits:
* Added PSU fan control
* Reverse engineered some of Super IO's HWM registers
* Added SMBIOS tables for IPMI
Change-Id: I4ee8da6349222fda8b6c30a7210ffdd65c183439
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25385
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested with GRUB 2.02 as a payload, booting Arch Linux with
latest kernel. This code is based on the output of autoport
as well as existing ga-b75m-d3h and ga-b75m-d3v mainboards.
Working:
- Serial port I/O
- S3 suspend/resume (broken with SeaBIOS 1.11.1)
- USB ports and headers
- Gigabit Ethernet
- Integrated graphics (libgfxinit)
- PCIe x16 graphics
- PCIe x1
- SATA controller
- Hardware Monitor
- Fan Control (fancontrol on linux works well)
- Native raminit (4+4GB, 4+2GB, 2+2GB, DDR3-1333)
- Native graphics init with libgfxinit
- flashrom, using the internal programmer. Tested with coreboot,
as well as with the vendor firmware. Backup chip is untested.
- NVRAM settings. Only `gfx_uma_size` and `debug_level` have been
tested with values different from the default.
Untested:
- VGA BIOS for integrated graphics init
- DVI port. It can detect a "fake" display, that is, an
EEPROM connected to the DVI port.
- PS/2 ports
- Audio: Only rear output (green) has been tested.
- EHCI debug.
- Parallel port
- Non-Linux OSes
- ACPI thermal zone and fan control (probably not working)
Not working:
- SATA devices with Tianocore (payload issue)
- PCIe to PCI bridge. It seems to be poorly supported on Linux,
it lacks a public datasheet and vendor BIOS behaves in the
same way: The bridge and the devices behind it appear, but
drivers fail to find devices attached to the bridge.
Change-Id: I598a0b75093a0f1aef2ac615035d66786a8c22cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/25912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
