This allows one to compile intelmetool with support for older ME
versions by setting the OLDARC preprocessor definition.
For example, compiling with OLDARC enabled avoids the "ME: GET FW
VERSION message failed:" error on the Lenovo X201i (ME version 6.0).
Change-Id: I5eb0da7663e795f790e2723bb334447380724b56
Signed-off-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-on: https://review.coreboot.org/26450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
The BINF3 (VBT7) reflects the firmware type, and we need that to
describe which type of firmware was booted.
The 'legacy' did not have its own value definition, but without that we
can't make sure if the system is running a non-chrome firmware or simply
entered legacy boot path. CL:1054307 introduced a new value (0x4) for
legacy type and we should handle it in crossystem mainfw_type command.
BUG=b:79130310
TEST=emerge-eve coreboot depthcharge chromeos-bootimage;
Boot in legacy mode and see crossystem reporting 'legacy' for
mainfw_type.
Change-Id: I4a1165e547e70c634d45054f56d1357ae5af2a83
Reviewed-on: https://chromium-review.googlesource.com/1068556
Commit-Ready: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Drive SPKR_RST_L (GPP_A19) high at boot to take audio amps out of
reset.
BUG=b:78122599
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage", boot to kernel,
and verify sound works via "aplay /dev/random"
Change-Id: Ia49931f2dc7802edc8a46114b081e4a96eeee604
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/26317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Need to enable PPC interrupts, otherwise system doesn't work correctly
include USB 2.0 not working (since the BC1.2 chip won't be powered after
the Vbus change)
BRANCH=none
BUG=b:79886742
TEST=USB 2.0 works on insertion on C0 on bip
Change-Id: I227dcfac22128389c3d3ab3efdddd045141dff7e
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1066221
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Observed task stack sizes growing, especially PD related.
Adjust chip configuration for 64KB data.
Use RAM size config items in flash layout config items.
Update SPI image generator python script to not add
a Boot-ROM header to EC_RW and add a test mode for debugging
SPI read and hash calculations.
BRANCH=none
BUG=
TEST=Build boards based on chip mchp. Check RO and RW
EC binaries are correct size and located properly in
ec.bin
CQ-DEPEND=CL:1036258,CL:1053576
Change-Id: I12709a434d5aaa84fabe459176a3423365343308
Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1053948
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The values of CROS_EC_VERSION and VERSION variables generated by
getversion.sh are exactly the same. VERSION is used in more places
than CROS_EC_VERSION, let's keep VERSION and use it everywhere.
BRANCH=none
BUG=chromium:632937
TEST=make buildall
Change-Id: Ibec9ecdd4b67789a468dddfbc1c82565f90d48a8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1069330
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Added flags parameter to extension_route_command(). The caller now
specifies whether the command comes from the USB interface or the AP.
Moved USB-specific shuffling of response to embed result code into
usb_upgrade.c, so extension_route_command() can be more generic.
No change to permissions/behavior for existing commands.
ccd_command_wrapper() still sends vendor commands as if they come from
the AP. That's fixed in the next CL.
Reduces code size by 128 bytes
BUG=b:79983505
BRANCH=cr50
TEST=manual
Build with DEBUG_EXTENSION defined, to turn on printing each command
'ccd lock' comes from AP and works
From host, 'gscutil -I' comes from USB and fails
From AP, 'gscutil -t -I' comes from AP and works
Change-Id: I7136bb54073de9c5951a174c308151b1871c56f3
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1068101
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The new GCC build shows a warning/error in clock-f.c:
'alarm_us' may be used uninitialized in this function
[-Werror=maybe-uninitialized]
This is actually a fake warning. In the context of the logic,
there is no way 'alarm_us' would be used uninitialized.
But let's still initialize 'alarm_us' to clear the compiler warning.
BUG=none
BRANCH=scarlet
TEST='USE=coreboot-sdk emerge-scarlet chromeos-ec'
TEST=make buildall -j
Change-Id: I7a0642cbe03c5a0adb6997ddc80c9cb797715749
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1068256
Commit-Ready: Martin Roth <martinroth@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
We have converted all LPC-only configs to HOSTCMD_LPC so the remaining
CONFIG_LPC defines represent the common case.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: Iba9a48f2cab12fadd0d9ab8eab0d5d5476eab238
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067503
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Break the ec chip code up with the more granular
CONFIG_HOSTCMD_(X86|LPC|ESPI) options.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: Ie272787b2425175fe36b06fcdeeee90ec5ccbe95
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067502
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The ITE eval board relied on the chip's define for LPC. Since the ITE
chip supports both LPC and eSPI, we want to define LPC here to be
explicit.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: Ic477277543c1f24999070dc408052c7266df22e6
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067501
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Convert all boards that use both CONFIG_ESPI and CONFIG_LPC to only use
the CONFIG_HOSTCMD_ESPI option.
BRANCH=none
BUG=chromium:818804
TEST=entire stack works with lpc and espi
Change-Id: Idd1519494a4f880b7b2018d059579d50c5461fcf
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067499
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Introduce CONFIG_HOSTCMD_LPC and CONFIG_HOSTCMD_ESPI which will replace
CONFIG_LPC and CONFIG_ESPI. Today the CONFIG_LPC option guards both
common code to eSPI and LPC and LPC-only code. Going forward
CONFIG_HOSTCMD_LPC will guard only LPC code, and a new option
CONFIG_HOSTCMD_X86 will guard common code to both LPC and eSPI.
I am leaving the CONFIG_LPC and CONFIG_ESPI defines in this CL so each
CL in the stack compiles.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: I6ae3a805167a3404701d8a53c14dc83299afb376
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067498
Reviewed-by: Randall Spangler <rspangler@chromium.org>
To enable device mode, set the gpio USB2_OTG_ID
in the respective boards to high.
Pull the gpio low to disable device mode.
BUG=b:79343083
BRANCH=NONE
TEST=On Yorp board, for UFP mode gpio USB2_OTG_ID should be high,
for DFP mode gpio USB2_OTG_ID should be low.
In OS console, lspci should list xdci.
(with chromiumos/third_party/coreboot/+/1064592)
Change-Id: I70f13a9705626d9bcbe989239f6826d35d8fa536
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1058832
Reviewed-by: Jett Rink <jettrink@chromium.org>
AP and EC consoles may generate a lot of bursty traffic, and cr50 UART
console to USB processing is very slow: when characters become
available, a hooks task callback is invoked, which retrieves received
characters one at a time and queues them up to the appropriate USB
transmit queue.
This patch speeds up things as follows:
- increases the seize of USB transmit queues for AP and EC console
channels to 512 bytes. Experiments supported by code
instrumentation has shown that even this is not enough to avoid
underruns, but this is a good compromise between memory use and
performance, these sizes could be revisited later,
- raises UART RX interrupt priority from level 1 to 0
- moving bytes from UART TX FIFO to USB queue happens on the
interrupt context when UART TX interrupt is asserted
- as many characters as possible are read from the UART first,
before queuing function is called, and the entire received batch
is passed to the queuing function.
It has to be mentioned here that presently batch processing is not
necessarily much more efficient, because queuing function becomes
more complicated when multiple objects are passed to it, this will
have to be dealt with in a separate patch.
There is still a lot of room for improvement:
- functions used to queue up data are very generic, dedicated code
could help a lot.
- UART drivers should have methods for collecting all bytes
available in receive FIFO in one invocation,
- USB side of things (dequeuing data and passing it to the
controller.
BRANCH=cr50, cr50mp
BUG=b:38448364
TEST=ran 'chargen' application on both AP and EC to flood the console
channels and observed the flow of characters on the host site, it
is pretty smooth with occasional hiccups, especially when TPM is
active, before this patch it was impossible to have both stream
up, both were garbled.
- Verified that new account can be created and user logged in on
restarts while chargen is running, i.e. TPM task gets enough
processing bandwidth.
- When EC is reset, there seem to be no lost characters on the
console (it used to cause some garbled console output before this
patch). The below output was collected on Coral:
> reboot
Rebooting!
--- UART initialized after reboot ---
[Reset cause: soft]
[Image: RO, coral_v1.1.8363+2cc945d5a 2018-05-15 17:41:57 ...
[0.003605 init buttons]
[0.003826 Inits done]
[0.004094 tablet mode disabled
]
[0.008272 found batt:SMP]
[0.022278 SW 0x01]
[0.042247 hash start 0x00040000 0x00021994]
[0.045823 Battery FET: reg 0x0018 mask 0x0018 disc 0x0000]
[0.071136 kblight registered]
[0.071544 PB init-on]
[0.071818 USB charge p0 m0]
[0.073670 ID/SKU ADC 4 = 1309 mV]
[0.075630 ID/SKU ADC 3 = 852 mV]
[0.076077 SKU ID: 71]
[0.076335 Motion Sensor Count = 3]
[0.083594 PD comm enabled]
...
- did not test bitbang programming mode, it is in line for
reworking for speeding up as well.
Change-Id: Ic9f3972f585dd1976169965c2a2422253aeac87a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1016037
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The factory tests relies on being able to read CEC_IN through the
GPIO API. When it is configured as TA1, it can't be read as a
GPIO. With this change, the pin will be a reconfigured as a GPIO
at boot or when CEC is runtime disabled using "ectool cec set
enable 0"
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:79842676
BRANCH=none
TEST=Test that "ectool cec read" still works with CEC on, and
that "ectool gpioget CEC_IN" reflects the incoming voltage when
CEC is off.
Change-Id: I3b17d6551612a156897d95ea2473e4fbcbd70e39
Reviewed-on: https://chromium-review.googlesource.com/1064110
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
When pushing to the circular buffer, the read-offset mutex is no
longer taken, so don't unlock the mutex.
Don't allow writing to the last byte of the buffer. In that case,
the read and write pointers will become equal and the buffer will
be treated as empty.
Add handling for pushing messages of invalid size.
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:76467407
BRANCH=none
TEST=Turn on/off TV:
ectool cec write 0x40 0x36
ectool cec write 0x04 0x40
Verify that incoming messages still works when turning off TV:
ectool cec read -- -1
Change-Id: Id207c442fac573430aac0c744ec07fa203074228
Reviewed-on: https://chromium-review.googlesource.com/1068945
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
It is copied from the Lux board, as the rev-0 hardware uses the same
design as Lux. The LED doesn't work if AP is in G5, as the LED power
source PP5000 is disabled in G5. Will fix it later.
BRANCH=none
BUG=b:74395451
TEST=Tested several scenarios: charge, low-level battery, charge but
no battery.
Change-Id: I3803b917c6c4cba35176b75cb316b2c8ef9eb13a
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1060582
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Remove the previous hack of force increasing the adapter current.
The PP5000 rail is now turned on/off during power-on/off AP.
Add a check to ensure it has enough power to enable the 5V rail
and boot AP. If the battery is in low level or unplugged and the
charger adapter doesn't supply enough power, don't boot AP and
transition back to S5. The check may wait a while for PD
negoiation.
BRANCH=none
BUG=b:79353631
TEST=On battery plugged and unplugged cases, checked the device can
source VBUS to USB port-0 and port-1.
TEST=Unplug battery and use a low-power adapter, can't boot up AP.
See the "Not enough power to boot" message and transition to S5.
Change-Id: Ie9b8dff6e10d97dffd554b382595e5e7a70875e6
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1050607
This commit adds the appropriate hibernate flags to the hibernate wake
pins. It additionally, adds a board specific hibernate function which
sets up the PSL pins for wake as well as writing to the ROP PMIC to
disable all the power rails.
BUG=b:79713379
BRANCH=poppy
TEST=Enter `hibernate` on EC console, verify that system can wake from
AC insertion, power button press, and lid switch.
Change-Id: I5b197c3c4d54cfc9c0b00c19815faa019f8b8cae
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1067892
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Some boards (like nocturne) use PSL mode, but the deassertion of PSL_OUT
does not directly cut the EC's VCC1 rail. Therefore, the board needs to
implement a board specific implementation of hibernate while also being
able to configure PSL mode. This commit exports a function of entering
PSL mode which could be used in a board specific hibernate
implementation.
BUG=b:79713379
BRANCH=poppy
TEST=`make -j buildall`
Change-Id: I8debcae5e713b85c6d23ee3419416b6ae5d5dbf0
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1067891
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The original UUT mechanism has the limitation that the image size cannot
exceed the code RAM size. Hence, it only allows to flash the EC firmware
by programming RO and RW images seperately.
In this CL, we introduce the "--auto" flag in uartupdattool.
It will divide the firmware into segments (4K bytes) and program
the segments one by one.
It also simplifies the function flash_npcx_uut() in flash_ec because
some actions are moved into the uartupdatetool with auto flag enabled.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST=
------------------------------------------------------------------------
1. Connect the servo connector (J24) on npcx7 EVB to servo board v2 via
flex cable.
2. Manually turn the switch SW1.6 to "ON" on npcx7 EVB.
3. Reset ec by issuing Power-Up or VCC1_RST reset.
4. Manually turn the switch SW1.6 to "OFF" on npcx7 EVB.
5. Move npcx7_evb from array BOARDS_NPCX_7M7X_JTAG to BOARDS_NPCX_UUT in
flash_ec.
6. "./util/flash_ec --board=npcx7_evb" or
"./util/flash_ec --board=npcx7_evb --ro"
(Note: this line in flash_ec must be removed in step 6:
https://chromium.googlesource.com/chromiumos/platform/ec/+/master/util/flash_ec#961)
Change-Id: Ifdb6a40ef88c6a9fb435169e158fd615100237cf
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1043825
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. With
PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page table
entry for this range which caused a page fault. Since this test
is anyway not exhaustive, we will skip the memory test in FSP.
There is an option to do PCIe power sequence from within FSP if provided
with the GPIOs used for PERST to FSP. Since we do this from coreboot,
will skip the PCIe power sequence done by FSP.
FSP does not know what the clock requirements are for the device on
SPI bus, hence it should not modify what coreboot has set up. Hence
skipping SPI clock programming in FSP.
CQ-DEPEND=CL:*627827
BUG=b:78599939, b:78599576, b:76058338
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: I4fa7a73fbb4676bb7af2416c8a33bf10ef41dd53
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/26284
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Update the config files to 1.8.13
- Unify the coreboot and coreboot_simple configs. The only difference
now is that coreboot uses the graphviz library to generate call graphs
and other things, while coreboot_simple does not. This means that the
doxygen_simple target builds in just over a minute, while the doxygen
build target takes roughly an hour.
- Both targets now only document coreboot proper. While at times it
might be useful to see links to code from src/vendorcode, 3rdparty, or
util, these directories also really clutter up the doxygen output. To
make it easier to see the coreboot code, all of these directories are
excluded.
Change-Id: Iefc667ee2f65859f151f5a97b7b9d182e8ed31f7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Because the tegra124 & tegra201 lp0 builds weren't junit tests, the
builds weren't actually picked up by jenkins, so any failures were
not previously reported.
Change-Id: Ie443ca713912d01ccf6921ce49f846d7297163ef
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26422
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
The function prototype for "struct device *add_cpu_device"
is already correct and doesn't need to be fixed.
Change-Id: I7bd8b93922f113bdaf7ba460acf6a7d62c4df013
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26067
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
