Refactor board/chip-specific code into corresponding directories.
Add support of the four I2C temp sensor in Link.
Use table lookup to handle different types of temperature sensors.
BUG=chrome-os-partner:7527
TEST=Correctly read EC internal temperature on bds.
Compile for link succeeded.
Change-Id: I694cfa54e1545798d877fafdf18c5585ab5f03e2
The problem comes from the different assumption of interrupt mode in EC and
the PCH. The PCH assumes IRQ1 is edge-triggered and triggered at a rising edge.
However, the auto-IRQ functino of EC is level-triggered and uses low-active to
assert an IRQ. This makes the deadlock so that the kernel never gets an
interrupt until a byte is manually pulled from host.
So, the solution is manually firing an IRQ_1 to host after EC puts a byte to
port 0x60. Note that the auto IRQ needs to be disabled in order to avoid
the interference with manual IRQ generation.
This CL also moves chip specific code to lm4/lpc.c and handle some minor
keyboard commands.
BUG=none
TEST=on hacked baord.
Change-Id: Ib57f5a4d749cb019e4c3c00da110054c4f335c7b
The ADC input pin was always configured as BDS. Modified it to configure
the correct pin.
BUG=none
TEST=On Link, "rw 0x4002451C" show 0xff instead of 0xf7.
Change-Id: I1efd5cd59ad65f55cd673529afa6153add63ecac
Refactor ADC code and move board/chip-specific part to corresponding
directories.
Implement function and console command to read Link charger current.
BUG=chrome-os-partner:7527
TEST=Read EC temperature and POT input on BDS.
Change-Id: I7fafd310ea49d9b2781f10c3453f5488da29a08a
simple UART driver to get the serial console on the USART3.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run on Discovery board and check we get the first message on the
UART and the console is echoing the characters.
Change-Id: Id85999a5ddbd75804e9317a1b8c2fd4afb89eb38
Expand the macros before building the priority variable name in order to
ensure we have a valid name.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=check manually preprocessor expansion for several combinations.
Change-Id: I926821d42c966ac674e7d24254c9f22779f93ca2
I keep hitting the darn arrow keys. Until we can do something more
elegant like a real command history, this will at least keep me from
corrupting the display and input buffer.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=type 'help' and some arrow keys, then enter. Should print help, not an error.
Change-Id: Idb552e9c22876fc2dc1f349f0038e94048f00aa7
Preparatory work to introduce a second SoC : 3rd series 2/2
All the RO/A/B firmware copy code could be generic to all our platforms.
The console commands are a 'standard' API.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on BDS EC console, check the reset cause with the 'sysinfo' command.
Change-Id: Ieeb84571085d88b5747a09da4c33d3852bb0da96
Preparatory work to introduce a second SoC : 3rd series 1/2
Most of the code is handling the buffering and the printf, thus put it
in an hardware independant location and only implement the UART
dependant portions in the chip driver.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run on BDS and stress the console.
Change-Id: I9376f2fa1dad341eac808e1756dbeff32900bd51
Preparatory work to introduce a second SoC : 2nd series 1/4
The atomic operations are SoC independant since they are only using
LDREX/STREX instructions which are just core specific ARMv7-M).
The watchdog header defines the API which is common to all platforms.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC firmware on BDS and check a few console commands
Preparatory work to introduce a second SoC : 2/5
The hwtimer.* files implement the driver for the SoC timer block.
The timer.* files provides the OS level clock/timer functions.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on BDS, check 'waitms' and 'gettime' on the EC console.
Change-Id: Icbc58d9be59ee268e2d5a94f8b20de0cabcdc91d
Preparatory work to introduce a second SoC : 1/5
Instead of putting hardcoded IRQ SoC name in the vector table,
upgrade the DECLARE_IRQ macro to expand its argument.
Also add a parameter to set the size of the NVIC table to save flash
memory.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC on BDS and see timer IRQs firing.
Change-Id: I44fefdabdd37d756492a71f24554979c72c1b50f
They are designed to protect shared hardware resources (e.g. I2C
controller).
Please refrain using them as a general purpose synchronization primitive
for the tasks to avoid unintended slippery effects (e.g. priority inversion),
use the provided message-passing functions instead for that purpose.
The mutex variable (ie the "struct mutex") should be initially filled
with 0, but this is the default compiler behavior if you declare it as a
global variable.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make qemu-tests
Change-Id: I328f7eadf5257560944dbbbeda0b99d5b24520e8
Instead of using a runtime callback to register the console commands,
put them in a special linker section. So we can do a macro to "register"
them during the build.
It saves 684 bytes and a few microseconds at startup.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run a few commands from the BDS command line.
Change-Id: Id33ea210b9035bf76ed720373c74c5dd24ccd1b1
Implement TPS2543 USB charging control.
It contains routine for setting each USB port as dedicated charging port
or standard downstream port. To allow us controlling the current
distributed to each port, we can select whether to allow 500mA or 1500mA
for each port.
BUG=chrome-os-partner:7476
TEST=Added USB port definition for BDS and tested GPIO output voltage
level is correct for all modes.
Change-Id: I19bc4b30d333aa802f868ebfc3a398b30e99ba0f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7456
TEST=if it runs, it works
Change-Id: Ib82afab7d53203af31eefc9887feb98679266ac1
For bringup, this powers on the x86 unconditionally.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7528
TEST=none
Change-Id: Ib23e56d38ab42f8d8a4dbd1ba9dce12f0c3eeec9
Added gpio_enable_interrupt() to enable them. This ensures that a
module which handles GPIO interrupts doesn't get them until it's
ready.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7456
TEST=toggle power button while rebooting; without this fix it triggers a hard fault.
Change-Id: I35d926053963a70dd9246ce46a4913603b2b2489
This just ensures the JTAG pins are reset to JTAG function on warm reboot.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7448
TEST=none
Change-Id: I0cccdbe7a68c228db7f354898ed30598e9fabff0
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7528
TEST=from debug console,
gpioget --> prints current level. Run a few times to see DEBUG_LED
value toggle.
gpioset debug_led 1 --> turns debug LED on. Run repeatedly to
override the idle task toggling it off.
Change-Id: I7c64044228697e052a9c20eb052d37a1f640f6e7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7499
TEST=press and release power button; should see debug messages
Change-Id: I8909ae4643afc98753edb690771618ad43135e3e
Add LPC host command to get and set fan speed.
BUG=chrome-os-partner:7313
TEST=Connect a fan and manually test fan actual speed matches target
speed.
Change-Id: I4b6a711a1b8cca0dbd1c1936fe4f0f15240d3453
Add a LPC host command to read temperature sensor value with given
sensor id.
Add ectool command to read temperature sensor value through LPC.
BUG=chrome-os-partner:7329
TEST=Manual check the reading received is the same as value printed by
console command.
Change-Id: Id3386774435be6c3ae010a143f4fa894568efdb8
The constants don't work with the DECLARE_IRQ() macro yet, because it
relies on stringizing the IRQ number.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: Ie6ddecd79e28c319b095089131579ba994a17da3
(cherry picked from commit e24904644a977f2618f51629cc066b93a3d53595)
LPC module no longer directly talks to UART registers, and vice-versa.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST='ectool sertest' on target system
Change-Id: Id070c0d849bdfe91c752e0af651d357b695d2648
(cherry picked from commit ab8c3c2b8e3b08a4bf5573cda3a12dd3a384e67d)
The LPC is not stable enough to test. Kodus Rong. He creates this idea
to checksum the partial content of flash for read/write/erase. This can
improve the robustness of flashrom.
BUG=none
TEST=Tested with flashrom.
Change-Id: I2a2f7b698a94674c03cbd8e3f15caf34f8986399
This CL add host command to enable, get/set flash write protect range.
BUG=None
TEST=Use flashrom utility to set write protect range, enable write
protect and get status.
Change-Id: I345f1eb65944d8cf8028e6fdb7e43c40cc742a6d
Signed-off-by: Rong Chang <rongchang@chromium.org>
