with x86 power module enabled, it no longer fits in 32KB.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=make
Change-Id: I38c9054efd8a072cc5800cc87936e53e2df00e58
Preparatory work to introduce a second SoC : 2nd series 4/4
Add a build time assertion which checks whether the UART used in the C
uart code is the same one as the one defined for assembly panic code.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=build for BDS with both good and bad address in CONFIG_UART_ADDRESS
Change-Id: I28dd6089bc938f06be0654d7bed75d7d698fafe0
Preparatory work to introduce a second SoC : 2nd series 3/4
Some modules won't be used on other designs, make them optional.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run the EC firmware on BDS and check that the commands from the
optional features are still available and working.
Change-Id: I979864ed94dc4da90c1010bd2e4589d84bc2d046
Preparatory work to introduce a second SoC : 2nd series 1/4
The atomic operations are SoC independant since they are only using
LDREX/STREX instructions which are just core specific ARMv7-M).
The watchdog header defines the API which is common to all platforms.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC firmware on BDS and check a few console commands
Preparatory work to introduce a second SoC : 5/5
All Cortex-M3/4 have the same NVIC registers at the same address.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC firmware on BDS and check a few console commands
Change-Id: I6b03c4c1fb21850be8c8afb711ea44134c8cdea1
Preparatory work to introduce a second SoC : 4/5
Allow to use the common code for most SoC.
Also simplify the UART code, we don't need speed on the panic path.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=trigger a panic and check the UART output on BDS
Change-Id: I11f7bbc571ab9efbc21fb7b805bf4e271b192c3b
Preparatory work to introduce a second SoC : 3/5
We split the drivers files which contain SoC specific drivers from the
OS files which only depend the actual CPU core.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC firmware on BDS and test a few commands on the console.
Change-Id: I598f8b23e074da9bd6b0e2ce6689c1075fe854f0
Preparatory work to introduce a second SoC : 2/5
The hwtimer.* files implement the driver for the SoC timer block.
The timer.* files provides the OS level clock/timer functions.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on BDS, check 'waitms' and 'gettime' on the EC console.
Change-Id: Icbc58d9be59ee268e2d5a94f8b20de0cabcdc91d
Preparatory work to introduce a second SoC : 1/5
Instead of putting hardcoded IRQ SoC name in the vector table,
upgrade the DECLARE_IRQ macro to expand its argument.
Also add a parameter to set the size of the NVIC table to save flash
memory.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC on BDS and see timer IRQs firing.
Change-Id: I44fefdabdd37d756492a71f24554979c72c1b50f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=at EC console, gpioget twice, then toggle an output using gpioset, then gpioget again
May see *'s the first time. Second time, should see no *'s. Third
time, should see a * only the toggled output (and any input signals
which respond to it).
Change-Id: Ibc1870839201008592b7982049cc352c1779a0e3
They are designed to protect shared hardware resources (e.g. I2C
controller).
Please refrain using them as a general purpose synchronization primitive
for the tasks to avoid unintended slippery effects (e.g. priority inversion),
use the provided message-passing functions instead for that purpose.
The mutex variable (ie the "struct mutex") should be initially filled
with 0, but this is the default compiler behavior if you declare it as a
global variable.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make qemu-tests
Change-Id: I328f7eadf5257560944dbbbeda0b99d5b24520e8
This script is automatically loaded when launching 'openocd -f
openocd.cfg'.
It adds 'flash_bds', 'ramboot_bds' commands to the openOCD console. The
former is writing the current EC firmware inside the internal flash, the
latter is loading a RAM only firmware on the chip.
There are similar commands for the Link Proto-0 board :
'flash_link', 'ramboot_link'.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=none
TEST=type 'flash_bds' from openocd telnet console
Change-Id: Ic63281a99ee1d083986696675ed0a82da7c033ee
You can now enable/disable tasks more easily.
To conditionally compile a C file depending on the task FOO activation,
just write something like that in the build.mk file :
common-$(CONFIG_TASK_FOO)+=foo_source.o
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make all BOARD=link && make qemu-tests
Change-Id: I760fb248e1599d13190ccd937a68ef47da17b510
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7703
TEST=reboot; look for "Hello on UART1" message on UART1 (which is uart2 on servo)
Change-Id: Ie497af48e62c28174b69adca5bea52d2f68d494f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7527
TEST=run 'temps' from console. Should print info on 4 sensors.
Change-Id: I8e0165235f9a12233bc3ac1fbde55c8eb3cfbb00
Instead of using a runtime callback to register the console commands,
put them in a special linker section. So we can do a macro to "register"
them during the build.
It saves 684 bytes and a few microseconds at startup.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run a few commands from the BDS command line.
Change-Id: Id33ea210b9035bf76ed720373c74c5dd24ccd1b1
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7697
TEST=if it runs, it works
Change-Id: I36ab37a8cf1c3e4bf41bfb38e622e766cee8a4c4
This works around a chip errata where the internal oscillator on early
EC parts (as used on proto0) is untrimmed.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7693
TEST=if it runs, it works
Change-Id: Ie82a524543f4cf25efd0de7998dbdae103bd126b
When code is compiled for RAM (by re-enabling the flag in board.mk),
use the following openocd commands to load it:
reset halt
load_image ../../../build/link/ec.RO.flat 0x20000000 bin
reg 15 0x20000400
resume
Note that you'll also usually need to disable a bunch of modules to make
the code small enough to fit in RAM.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7681
TEST=if it runs, it works
Change-Id: I2b3cc69b361ad73706af3ff6de1ce952e8d5a0a9
Ensure that all the code ends up in the expected place.
This bug beat us for the RAM only version but it is present
even in the flash version (though probably harmless).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run the resulting image on BDS and inspect manually the .map file.
Change-Id: Iefe505bc507547b1043cb493ba7e8f210bb1ebc4
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7677
TEST=if it runs, it works
Change-Id: Ib4f28505f6b9a21375f9c3ba97c6e8d56722c051
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7456
TEST=if it runs, it works
Change-Id: Ib82afab7d53203af31eefc9887feb98679266ac1
For bringup, this powers on the x86 unconditionally.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7528
TEST=none
Change-Id: Ib23e56d38ab42f8d8a4dbd1ba9dce12f0c3eeec9
Added gpio_enable_interrupt() to enable them. This ensures that a
module which handles GPIO interrupts doesn't get them until it's
ready.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7456
TEST=toggle power button while rebooting; without this fix it triggers a hard fault.
Change-Id: I35d926053963a70dd9246ce46a4913603b2b2489
Also fixes a typo in power_button.c when compiled for link
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7528
TEST=none
Change-Id: Ib43ef9edefe0b0caba246faa4a0d12d66ff9e205
This just ensures the JTAG pins are reset to JTAG function on warm reboot.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7448
TEST=none
Change-Id: I0cccdbe7a68c228db7f354898ed30598e9fabff0
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7528
TEST=from debug console,
gpioget --> prints current level. Run a few times to see DEBUG_LED
value toggle.
gpioset debug_led 1 --> turns debug LED on. Run repeatedly to
override the idle task toggling it off.
Change-Id: I7c64044228697e052a9c20eb052d37a1f640f6e7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7499
TEST=press and release power button; should see debug messages
Change-Id: I8909ae4643afc98753edb690771618ad43135e3e
Implement the state machine for PWRBTN# input and output to PCH. The state
begins while power button is pressed and stops while it is released or 8 secs
pass. The state machine is maintained inside the infinite loop of gpio_task().
Remember to #define EVT after the board comes back.
Also, the power-up sequence is not completed yet. Remember to come back when
it is done. Search TODO in code.
BUG=none
TEST=Manual run on evaluation board (via console printf):
#---------------------------
# power button pressed and release after 8s
[3070341] New State: START next_ts:3070340
# wait for next pwrbtn_sm_handle() is run.
[3071428] set_pwrbtn_to_pch(LOW)
[3071482] New State: T0 next_ts:3103426
[3103963] set_pwrbtn_to_pch(HIGH)
[3104023] New State: T1 next_ts:7071961
[7072044] set_pwrbtn_to_pch(LOW)
[7072103] New State: T2 next_ts:11072042
[11072661] set_pwrbtn_to_pch(HIGH)
[11072723] New State: STOPPED next_ts:11072042
# power button released
[14336515] New State: STOPPING next_ts:14336514
[14337604] set_pwrbtn_to_pch(HIGH)
[14337662] New State: SOPPED next_ts:14336514
#---------------------------
# Power button released during T1
[378324436] New State: START next_ts:378324435
[378325530] set_pwrbtn_to_pch(LOW)
[378325589] New State: T0 next_ts:378357528
[378358080] set_pwrbtn_to_pch(HIGH)
[378358143] New State: T1 next_ts:382326078
[378889269] New State: STOPPING next_ts:378889268
[378890361] set_pwrbtn_to_pch(HIGH)
[378890420] New State: STOPPED next_ts:378889268
#---------------------------
# Power button released during T2
[448592391] New State: START next_ts:448592390
[448593483] set_pwrbtn_to_pch(LOW)
[448593542] New State: T0 next_ts:448625481
[448626041] set_pwrbtn_to_pch(HIGH)
[448626104] New State: T1 next_ts:452594039
[452594076] set_pwrbtn_to_pch(LOW)
[452594138] New State: T2 next_ts:456594074
[453199165] New State: STOPPING next_ts:453199164
[453200257] set_pwrbtn_to_pch(HIGH)
[453200316] New State: STOPPED next_ts:453199164
Change-Id: I5a12f3e46fa8086c530123a81ee743d3664b91f4
By default the scanning code would pull-low all column pins and listen to
any key press interrupt on input pins. This can save power compared to the
repeatly polling.
Once a key is pressed, the scanning code enters the busy loop and pull-low
column pins one by one. Then generate the scan code to host.
The code keeps polling after 1 second after no key is pressed. Then goes
back to interrupt mode.
BUG=none
TEST=Manual tested on S*y machine.
Change-Id: I0bf8877450dbd6ad1197a2fe1714ab755dc49a80
Implement EC lid switch interrupt handler and debouncing.
BUG=chrome-os-partner:7363
TEST=Manually test lid switch output signal is correct.
Use UART console to see debouncing is correct.
Change-Id: I74aad63330716da017fc4a57002349461c6a9b26
The constants don't work with the DECLARE_IRQ() macro yet, because it
relies on stringizing the IRQ number.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: Ie6ddecd79e28c319b095089131579ba994a17da3
(cherry picked from commit e24904644a977f2618f51629cc066b93a3d53595)
LPC module no longer directly talks to UART registers, and vice-versa.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST='ectool sertest' on target system
Change-Id: Id070c0d849bdfe91c752e0af651d357b695d2648
(cherry picked from commit ab8c3c2b8e3b08a4bf5573cda3a12dd3a384e67d)
This CL add host command to enable, get/set flash write protect range.
BUG=None
TEST=Use flashrom utility to set write protect range, enable write
protect and get status.
Change-Id: I345f1eb65944d8cf8028e6fdb7e43c40cc742a6d
Signed-off-by: Rong Chang <rongchang@chromium.org>
