there are no pullup resistors on the TCPC ALERT# pins and none on the
board, so we need to turn on internal pullups on the EC side.
BUG=b:75070158
BRANCH=none
TEST=board still boots
Change-Id: I15a7940d8b647b83c6ae304171c4a7c46b920529
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1059870
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Before:
*** 4560 bytes still available in flash ****
After:
*** 4696 bytes still available in flash ****
BRANCH=none
BUG=b:65253310
TEST=Update Cr50 with this image and verify the keys are the same.
Change-Id: I1c722ced185c41f732ce0ed5236db01401f21dfc
Signed-off-by: Allen Webb <allenwebb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1031058
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This patch makes led_get_brightness_range return amber=100, white=100
regardless of OEM ID or led_id. This function is for ectool led command,
which is used to test basic LED connectivity.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:78489297,b:77827579
BRANCH=none
TEST=Run
1. ectool led battery white=100
2. ectool led battery amber=100
3. ectool led power white=100
4. ectool led power amber=100
Change-Id: I6c6b3a5dd26aaba3a3ff7dccd6e116794c6594c9
Reviewed-on: https://chromium-review.googlesource.com/1062077
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Gemini Lake-based chipsets support a subset of virtual wires that other
Intel processors do. The current settings prevent the GLK APs from
bootign in some situations; PLTRST# doesn't get reasserted when there is
an error.
See "eSPI Compatibility Specification (562633)" for details.
BRANCH=None
BUG=b:79778835
TEST=Successfully booted bip after a cold reset from servo
Change-Id: I02b403ab6b06cbcae61ac46132018e95988a3d43
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1064704
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.corp-partner.google.com>
They're only used within the same file and should always be inlined.
It also helps gcc 8.1's lto linking which seems to not inline it (since
inline is just a hint) but then drops the function (presumably because
it's small, marked inline, and comes with no prototype).
BUG=b:65441143
BRANCH=none
TEST=builds with gcc 8.1
Change-Id: I881a5b9f13192dd11748d8a3060788f95a84dec0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1061075
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
This reverts commit cfcac78e62.
Reason for revert: Removing all s3 termination support. It's not
necessary and it causes scarlet to boot into recovery.
Original change's description:
> cr50: add support for enabling terminations on ap suspend
>
> rk3399 systems need terminations on the SPI signals in S3 and all other
> low power states. Add support for enabling the pulldowns and pullups on
> the correct pins.
>
> With this change, if BOARD_NEEDS_S3_TERM is set in the board properties,
> cr50 will enable a pulldown on the AP TX Cr50 RX signal and a pulldown
> on all of the SPS signals. To keep the pulldowns from interfering with
> the sps peripheral, s3_term will also disable the input for those
> signals.
>
> BUG=b:62200096
> BRANCH=cr50
> TEST=Flash onto bob. Make sure cr50 enables and disables terminations
> when the AP suspends/resumes. Flash onto reef. Make sure it doesn't do
> anything.
>
> Change-Id: I4adaf6d66160bab1eb3cf3d343d4a79524ccf883
> Signed-off-by: Mary Ruthven <mruthven@google.com>
> Reviewed-on: https://chromium-review.googlesource.com/991338
> Commit-Ready: Mary Ruthven <mruthven@chromium.org>
> Tested-by: Mary Ruthven <mruthven@chromium.org>
> Reviewed-by: Randall Spangler <rspangler@chromium.org>
Bug: b:62200096
Change-Id: I00c5051a48d4578badf9ce6622dea1af9903f4fd
Reviewed-on: https://chromium-review.googlesource.com/1062687
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This reverts commit c24d480d90.
Reason for revert: Removing all s3 termination support. It's not
necessary and it causes scarlet to boot into recovery.
Original change's description:
> cr50: disable s3_terms during init
>
> When cr50 resumes from deep sleep term_enabled is reset to 0, but not
> all of the s3 termination settings are reset. Some of them are, because
> some of the gpios are defined in gpio.inc and cr50 will handle setting
> those up during init, but others like the sps pulldowns aren't. At this
> point, the term_enabled setting does not actually match the state of
> enabled terminations.
>
> After deep sleep reset if the AP is on, ccd update state will try to
> disable the s3 terminations, but term_enabled is 0, so s3_term thinks
> they're already disabled and wont do anything even though some of the
> terminations are actually enabled.
>
> This change initializes all of the s3_term stuff to disable during hook
> init. This way things are reset so they won't interfere with sps_init.
> This will also make sure to align the system state with term_enabled,
> before the ccd hook starts getting called. It is safer to start with
> disabling the terminations, because it wont interfere with tpm
> communication if the AP is on. If the AP is off, ccd_update_state will
> re-enable the terminations around a second after init.
>
> BUG=b:62200096,b:79214702
> BRANCH=cr50
> TEST=firwmare_Cr50DeepSleepStress.reboot on bob
>
> Change-Id: I9a90c7f7703b1406b4c494db448a8ac84d040d1c
> Signed-off-by: Mary Ruthven <mruthven@google.com>
> Reviewed-on: https://chromium-review.googlesource.com/1043152
> Commit-Ready: Mary Ruthven <mruthven@chromium.org>
> Tested-by: Mary Ruthven <mruthven@chromium.org>
> Reviewed-by: Randall Spangler <rspangler@chromium.org>
> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Bug: b:62200096, b:79214702
Change-Id: If3467352030c65365c6851cd692aa5d0e9f47667
Reviewed-on: https://chromium-review.googlesource.com/1062686
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This commit fixes a bug where the base would not be powered after the
system was power cycled without disconnecting the base.
BUG=none
BRANCH=poppy
TEST=Flash nocturne; boot to S0, attach base, shutdown to S5. Boot to
S0, verify that base is powered.
Change-Id: Ia3de500afdc29cb601c1b5571cd3355711a3b368
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1062993
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Make Esc+Refresh+Power on Grunt enter Recovery Mode.
If Power is released fast:
[0.045303 KB init state: -- 02 08 -- -- -- -- -- -- -- -- -- --]
Add CONFIG_KEYBOARD_IGNORE_REFRESH_BOOT_KEY to handle this case.
If Power is held longer:
[0.045448 KB init state: 08 0a 08 08 08 -- 08 -- 08 08 -- 08 08]
Add CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3 to handle this case.
BUG=b:79758966
BRANCH=none
TEST=Esc+Refresh+Power gives recovery screen on Grunt
Change-Id: I43a7d485535ff7b0d9bfce59f28c0049ee989818
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1063032
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
CPRINTS() macro is already adding the newline character, no need to
include it explicitly.
BRANCH=none
BUG=none
TEST=vefied that Coral EC does not print this newline any more
Change-Id: I1f6b1fcb90818a8d4a2d18cf5060669fc46d38a7
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1062588
Reviewed-by: Jett Rink <jettrink@chromium.org>
When we exit DBGR mode on the ITE after flashing, it wedges the
SDA line, which prevents us from using dut-control cold_reset.
We do not need to exit DBGR mode since we will perform a cold reset
after we finish flashing.
BRANCH=none
BUG=b:79592483
TEST=flash bip multiple times and EC resets after flashing automatically
Change-Id: Iafbad7a88a528ec7385596fd7c674b151f276166
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1060588
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The decimal converted value for i2c read does not work.
It just happens to work every other time I have seen it.
BUG=none
BRANCH=none
TEST=bip i2cxfer r works
Change-Id: I7d868e3fc79eea081867634b679120f2da6f9363
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1060167
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Currently, field sizes are automatically set to the smallest size
which can fit a given value. This patch makes cbi-util allow field
sizes to be specified.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:79514391
BRANCH=none
TEST=Tested as follows:
1. Create CBI image:
$ cbi-util create --file cbi.bin --board_version 0x202 \
--oem_id 0xabcd:2 --sku_id 0xff:4 --size 256
2. Verify the image:
$ cbi-util show --file cbi.bin
CBI image: /home/dnojiri/tmp/nami/tmp/cbi.new.bin
TOTAL_SIZE: 22
Data Field: name: value (hex, tag, size)
BOARD_VERSION: 514 (0x202, 0, 2)
OEM_ID: 43981 (0xabcd, 1, 2)
SKU_ID: 255 (0xff, 2, 4)
3. Verify the output matches with the previous output if field sizes
are not specified.
Change-Id: Ic7149274d6e4a118ea12bbf03199b548b7089a3e
Reviewed-on: https://chromium-review.googlesource.com/1056201
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For Bip P0, we are using some of the Sanyo batteries. Need to add
support in battery.c/board.h so this battery is recognized and
battery disconnect and cutoff functions are supported.
BRANCH=none
BUG=b:79734977
TEST=Verfied Sanyo battery is found at EC init time and that 'cuttof'
EC console command works.
Change-Id: I4b69296869e1eed6248800eb4b7b3c35a79bae4c
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1059935
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Adding this config so that battery_get_disconnect_state() is called
directly as a condition in prevent_power_on instead of having this be
a condition battery_is_present. This change allows precharge current
to be sent to the battery when the battery is dead or recovering from
battery cutoff condition.
BRANCH=none
BUG=b:79133101
TEST=tested on Yorp and verfied that in both dead battery and battery
cutoff cases, the battery wakes up as expected.
Change-Id: Iefec578dd241ddb832630ffa2530ba7c631f9a96
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1053096
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
The ITE TCPC driver does not current support drp_toggle and so can't
have these config options defined. The driver method for drp_toggle is
set to NULL which causes the EC to reboot when power button is pressed
as that calls drp_toggle in the chipset hook.
BRANCH=none
BUG=b:79637786
TEST=Verfied that with these config options not defined the EC no
longer reboots when power button is pressed.
Change-Id: I08e27bb2541bac4fac52411d9c01a366b8874379
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1059580
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
This CL adds the port number to the error messages for the TI sn5330
PPC driver. It also adds 'ppc' so that its clear where the messages
are coming from.
BRANCH=none
BUG=b:79640678
TEST=Tested on Bip MLB and verfied that PPC EC console log errors
display the port number.
Change-Id: I7988e5e4008c005bb1ef9a78331d4a2597fdcb62
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1060105
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
When running signed with dev keys and the fallback certificate is not
available, proceed installing unverified root certificate. This at
least allows to keep basic TPM functions like storing objects in NVMEM
to keep going. Added a new return value to indicate this condition.
BRANCH=cr50, cr50-mp
BUG=none
TEST=verified that it is possible to switch chromebook between prod
and dev modes when running with a dev signed Cr50.
Change-Id: I5b16d0bcbcfb25368f65075e1d2d485a69cb729f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1054990
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
Add the FP_CAPTURE_RESET_TEST capture mode to be able to perform the
reset pixel values test.
Update ectool accordingly and also remove the deprecated 'fpcheckpixels'
command.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:78597564
TEST=run 'ectool --name=cros_fp fpmode capture test_reset',
then 'ectool --name=cros_fp fpframe > test.pnm'
CQ-DEPEND=CL:*626747
Change-Id: I183f33b1cb9ba4db67219b8f7740d29dc0551f2d
Reviewed-on: https://chromium-review.googlesource.com/1061074
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
charge_manager_fill_power_info can be called to fill the power info
of the dedicated port. This function might call
charge_manager_get_source_current with the dedicated port, we don't
want to use assert in that case, but just fail gracefully by returning
0.
BRANCH=None
BUG=chromium:841944
TEST=Check that the function returns 0 for dedicated and not 0 for USB.
Change-Id: I357c056647e01bdb0e77a08a6c6b492aa3dbb503
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-on: https://chromium-review.googlesource.com/1059248
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
The BMI160 driver requires that the macro I2C_PORT_ACCEL is defined.
This commit simply defines that macro and defines a matrix to rotate the
sensor data into the standard frame.
BUG=b:79715267
BRANCH=master
TEST=Flash nocturne, verify that the BMI160 initializes successfully.
Verify that when device is struck from the left edge, positive
acceleration is seen on the X axis. When device is struck from the
bottom edge, positive acceleration is seen on Y axis.
Change-Id: I6407b21fdfe311fa8ac7d83a8050ebfb27b4e0d8
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1059535
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Usually, we enable CONFIG_FPU on NPCX, which requires larger
stack size. Also, NPCX has very deep call patch in I2C transactions
(in particular, I2C recovery path), so it generally requires larger
stack.
To make the code fit, however, we need to reduce the accelerometer
fifo depth from 1024 to 512, on a few boards.
BRANCH=none
BUG=b:75234824
TEST=make buildall -j, stackanalyzer result on poppy looks a little
better.
Change-Id: I37b5a2a97a760dc4fd225253c23962d74e25605a
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/967963
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Processing of TCPC alerts takes place in the PDCMD task and the result
of processing alerts is to wake the PD task. When the PD task runs,
it's possible that it may attempt to put the TCPC into low power mode
prior to the remainder of the alert processing function completing. So
there may be pending TCPC accesses in the alert handler function which
called subsequent to the PD task putting the TCPC into low power
mode. The TCPC access in the PDCMD task will cause the TCPC to exit
low power mode. With the ANX7447 TCPC, this process will repeat
indefinitely.
This CL replaces the calls to task_set_event and task_wake with
indications stored in a local variable. Then at the end of the
function the task_set_event is made if necessary. This change in order
removes one guaranteed source of pending TCPC accesses from causing
the TCPC to exit low power mode.
BRANCH=none
BUG=b:77544959
TEST=Was using Salea logic analyzer and testing in conjunction with
low power mode. Verified that prior to this change I2C accesses were
attempted and NAKd after the command I2CIDLE was sent on the bus. Also
tested basic type C operation as both SNK/SRC.
Change-Id: I8879c655a48a2b16e0445522497002482dc9ca33
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1044868
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
After we set TE (CL:958295), rt946x terminates charging when
the charge current is below IEOC in constant-voltage mode.
When AC is plugged and rt946x terminates, we see cases that
battery SOC falls below BATTERY_LEVEL_NEAR_FULL but rt946x doesn't
re-enable charging yet, which leads to amber LED. The Chrome OS UI
might also show battery is not full in this case.
Let's clamp the reported battery SOC in this scenario to
avoid user confusion.
BUG=b:77870927
BRANCH=scarlet
TEST=When AC is on, charge terminates, and BATTERY_LEVEL_NEAR_FULL
is hit, confirm battery SOC is overwritten.
Change-Id: I4575e562873d149d6f349ddb578334d107e21776
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1055194
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
After we set TE (CL:958295), rt946x terminates charging when
the charge current is below IEOC in constant-voltage mode.
Let's add an interface to check charge termination status.
BUG=b:77870927
BRANCH=scarlet
TEST=charge scarlet, confirm rt946x_is_charge_done() returns 0 when
battery is charging and returns 1 when charge terminates (battery is
full). Then keep AC plugged and wait, confirm rt946x_is_charge_done()
returns 0 when rt946x restarts charging.
Change-Id: I559d328aa0d7c5c4cd5bf7178370ea039aa80204
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1044768
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
EC can't be waked up once it enters hibernate. Need to figure out the
cause. Disable it temporarily in order not to block others.
BRANCH=none
BUG=b:79348203
TEST=Ran "help" on console and not "hibernate" command.
Change-Id: Ifba2b95df26b03e4389616ebb3fc217bb5a24d54
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1050748
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The charge_prevent_power_on() function checks for battery presence and
its charge level as a condition to prevent AP power on. In order to
deal with the short (up to a few seconds) time window where the fuel
gauge can be read but the discharge FET is not yet enabled, the
status of battery_get_disconnect_state() has been added as a condition
to many board's battery_is_present() function.
The problem with this approach is that the return value of
battery_is_present() is also used by charge_state_v2 as a condition to
force the charge state to ST_IDLE. Then, if the config option
CONFIG_CHARGER_MAINTAIN_VBAT is not defined, the value of requested
current and voltage will be forced to 0 as long as the state remains
in ST_IDLE. When the battery is dead or has been cutoff its discharge
FET will be disabled. In order to for the discharge FET to be enabled
the charger must provide at least a precharge level of current to the
battery. But, if the FET status is used as a condition for
battery_is_present which in turn forces the charge state to ST_IDLE
which can lead to requested_current being forced to 0.
This CL enables a way to remove battery_get_disconnect_state() as a
condition from battery_is_present and instead call
battery_get_disconnect_state() directly in the function
charge_prevent_power_on. Therefore AP power can still be gated by the
battery FET status, but the charge state will not be stuck in ST_IDLE.
This new check is guarded by CONFIG_BATTERY_REVIVE_DISCONNECT. Boards
which currently condition battery_is_present on the value of
battery_get_disconnect_state() don't change at all, but a board which
needs to remove that condition on battery_is_present can still use the
FET check to prevent AP power on.
BUG=b:79133101
BRANCH=none
TEST=Tested on Yorp and verifed that when using either a dead battery
or a battery that had been cutoff, prevent_power_on was set to 1 until
the FET status was correct for the battery to provide power.
Change-Id: Ic27f42610a7b751394b29a013c4dd17030a3df31
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1053095
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When the EC sends an interrupt to the AP notifying it of new
accelerometer data we need to make sure the spot we record the timestamp
of the event is virtually identical to the spot the AP records the same
point in time.
Therefore a better spot for that is right next to the gpio toggling of
the interrupt line.
BUG=b:67743747
TEST=In the kernel, fifo_info->info.timestamp still has sane values.
TEST=CTS should still pass
BRANCH=master
Change-Id: Ic77101a045123e779f576c46b401c765304976fd
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/802976
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Sometimes common code needs __hw_clock_source_read, add it.
The implementation is similar of what common/timer.c does to create a ts
for get_time(), but in reverse.
TEST=Unit tests pass again for the next CL
BRANCH=master
BUG=None
Change-Id: I10564abedabe88e4789723bc97bac170ae020c69
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1055191
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
zoombini does not have MKBP enabled, it's nonsensical to have the sensor EC
side FIFO enabled. while it does compile (currently) it makes no sense to have
one without the other.
The next patch in this series will add more cross coupling between them (MKBP
set_gpio time will have to be communicated to the sensor fifo code). And
buildall is failing due to this half inclusion.
This patch disables FIFO stuff on zoombini as a fix. With that we also need
to disable the vsync sensor, since that depends on FIFO. #ifdefs everywhere!
TEST=FIFO stuff will not get compiled in when there's no MKBP
TEST=Next patch doesn't fail buildall anymore.
BRANCH=master
BUG=None
Change-Id: I6877fd131b84e9d42f32c5628c928a1355a5774c
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1055189
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Room remaining in flash is an ever important property of many EC
images. This patch adds a makefile rule with will calculate how much
free room is left in the RW partition with the current image.
The calculation uses two variables set by the linker: 'FLASH' which
shows how much room is allocated to the image and '__image_size' which
shows how much room is actually taken. The difference is how much room
is still available.
Wnen building with V=0, size is not reported.
BRANCH=cr50, cr50-mp
BUG=b:65253310
TEST=observed reported values:
$ make BOARD=cr50 -j
...
*** 7864 bytes still available in flash on cr50 ****
$ rm -rf build/cr50/
$ make BOARD=cr50 CR50_DEV=1 -j
*** 4488 bytes still available in flash on cr50 ****
Change-Id: I66e23dc72905988b21666c5dc9608d92e3fead50
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1030909
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
AES-CMAC implementation based on extant 128-bit AES, following closely
to the description in RFC 4493. Timing depends only on the length of the
message, not the content or the keys.
Signed-off-by: Jade Philipoom <jadep@google.com>
BRANCH=cr50
BUG=b:72788497
TEST=Passed the four test vectors provided in the RFC; these tests are defined as commands in aes_cmac.c and can be run with
"test_cmac 1 2 3 4" when CRYPTO_TEST_SETUP is defined.
Change-Id: I96fb4f29927c11970a6a17c0fd583694aa945c91
Reviewed-on: https://chromium-review.googlesource.com/975181
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Bip has an I2C mux that we need to set before we can program the ITE8320
chip. Set the dut's i2c mux to pass through to the EC.
BRANCH=none
BUG=b:79533605
TEST=flash bip and reef_it8320
CQ-DEPEND=CL:1054559
Change-Id: I690aa253c757c37dfb276d5be897b92a9aa1545e
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1054560
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Instead of fetching incoming CEC messages using a specific read
command, extend the standard mkbp event so the CEC message can
be delivered directly inside the event.
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:76467407
BRANCH=none
TEST="ectool cec read" still working with a kernel that has support
for the increased mkbp size.
CQ-DEPEND=CL:1046186,CL:1051085
Change-Id: Id9d944be86ba85084b979d1df9057f7f3e7a1fd0
Reviewed-on: https://chromium-review.googlesource.com/1051105
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add support for usb_updater2 in servo_updater.
This allows update back and forth between servo-9040.B
releases and builds from master, although they have
different updater enpoint interfaces.
Also add '-n' no force reboot to usb_updater2 as force reboot
is incompatible with servo_updater's flow.
BRANCH=None
BUG=b:69016431
TEST=update servo v4
Change-Id: I18809590c2e7e1cfcf60c4c97e956dfc22d85856
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1056157
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
