For oak, set a different list of task (no als, no accel) for compiling
revision 4 or less. Fix GPIO include issue.
BUG=chrome-os-partner:59423,chrome-os-partner:59084
TEST=compile for oak with board 4 and 5, tested on Reef.
BRANCH=kevin,reef
Change-Id: I09051a69cbad6d477a7b3bf9907f4c5c144b5136
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424220
Reviewed-by: Randall Spangler <rspangler@chromium.org>
sensor private structure for bmi160 and bmp280 were defined
in the drivers themselves. It worked because there was only one
instance of each sensors on a board. However, this is an error it
should be in board files, as it was done for other sensors like the kionix.
BUG=none
TEST=buildall.
BRANCH=kevin,reef
Change-Id: Ica3aba358d141a7df9a3e97251d4c1e520cbf2c8
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424218
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Perform PKCS1-padding-only signing for RSASSA if hashing algorithm is
TPM_ALG_NULL.
This feature is guarded by SUPPORT_PADDING_ONLY_RSASSA macro in
tpm2/Implementation.h.
BUG=chrome-os-partner:60967
BRANCH=none
TEST=On a unowned machine with TPM2: corp enroll, login, install
a network certificate (gECC or GMC), then:
a) retrieve the public key from the installed certificate
LIBCHAPS=`ls /usr/lib**/libchaps.so`
CERTID=`pkcs11-tool --module=$LIBCHAPS --slot=1 --type=cert \
-O | grep "ID:" | awk '{print $2}'`
pkcs11-tool --module=$LIBCHAPS --slot=1 --id=$CERTID \
--type=cert -r > /tmp/cert
openssl x509 -inform der -pubkey -noout -in /tmp/cert > /tmp/pub.key
b) sign a sample text using the private key for the certificate and
MD5-RSA-PKCS mechanism, not supported by TPM2_Sign command:
echo "ABCDEF" > /tmp/1.txt
pkcs11-tool --module=$LIBCHAPS --slot=1 --id=$CERTID --sign \
-i /tmp/1.txt -o /tmp/1.sig -m MD5-RSA-PKCS
c) verify signature:
openssl dgst -md5 -verify /tmp/pub.key \
-signature /tmp/1.sig /tmp/1.txt
Step (b) should succeed and step (c) should return "Verified OK".
Change-Id: I0d7a11c48cdb04e37748f7255b98e9e023481a96
Signed-off-by: Andrey Pronin <apronin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/420854
Reviewed-by: Darren Krahn <dkrahn@chromium.org>
This change takes away control of trackpad from EC entirely. This will
prevent EC from interfering with the OS's interaction with the trackpad
for firmware update, device detection at boot, or entering S3.
Disadvantages are the trackpad will stay on (thus can wake up the system
unintentionally) when the system enters S3 in laptop mode then
transitions to tablet mode, or vice versa: the trackpad will stay off
(thus cannot wake up the system) when the system enters S3 in tablet mode
then transitions to laptop mode.
However, these corner cases can be handled by waking up the system upon
mode transition. The OS can then disable or enable the trackpad depending
on the transition direction (laptop <-> tablet) and re-enters S3. Or the
OS can leave the system running because mode transition implies a user's
intention to start interacting with the device.
The keyboard will continue to be managed by EC and disabled or enabled
upon mode transition.
BUG=chrome-os-partner:61058
BRANCH=reef
TEST=Put device into S3 in tablet mode. Wake it up.
Change-Id: I2f4aa72d704c6562dd861b105225b1995226a09a
Reviewed-on: https://chromium-review.googlesource.com/421275
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch enables accels in S3. Accels are required to calculate a
lid angle. EC enables/disables keyboard based on lid angles. EC
needs to be able to control it because the kernel is in sleep state
in S3.
BUG=chrome-os-partner:58792
BRANCH=reef
TEST=lid angles are calculated correctly in S0 and S3.
Change-Id: I13c69a47da2c6521cd0c03c66cf061deb3f4fabd
Reviewed-on: https://chromium-review.googlesource.com/421276
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Provide the calling stubs for p256 sign, verify, point mul, etc.
This also drops third_party/cryptoc/p256_ec and p256_ecdsa from the
image. And fewer routines from cryptoc/p256.c remain as well.
BRANCH=none
BUG=none
TEST=tcg_tests pass, test/tpm_test/tpmtest.py pass
Change-Id: Ib6c35f5d34a2c8434e78b44cbef8b69802734c50
Signed-off-by: Marius Schilder <mschilder@google.com>
Reviewed-on: https://chromium-review.googlesource.com/422942
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Trybot-Ready: Marius Schilder <mschilder@chromium.org>
After every reboot, we were resetting the write protect and console
lock states back to default. With this change the wp and lock states
will be preserved through deep sleep. They will still be reset on any
other type of reboot (like Power On reset or panic).
The states are also cleared if the system detects a rollback even when
booting from the deep sleep.
With this patch it is going to be impossible to remove hardware write
protection guarding writes into AP and EC firmware flash, unless the
cr50 console is unlocked.
Locking the console would reinstate hardware write protection
automatically even if it was disabled when the console was unlocked.
Two long life scratch register 1 bits are used to keep the console and
write protect states over resets. To make code cleaner bitmap
assignments of the long life scratch register is put in its own
include file.
BUG=chrome-os-partner:58961
BRANCH=none
TEST=manual
On prod/dev images verify that the default wp and console lock
states are still correct.
change the lock and write protect states from the default and
verify they are preserved through deep sleep.
reboot cr50 and make sure that they are reset.
unlock the console and enable flash writes, then set fallback
counter on cr50 to the value of 6 (rw 0x40000128 1; rw
0x4000012c 6) and put the AP into deep sleep by hitting
Alt-H-VolUp.
In five minutes press the power button on the device to bring
it back from s5. Observe cr50 fall back to an older image and
console lock and wp disabled.
Change-Id: Ie7e62cb0b2eda49b04a592ee1d0903e83246b045
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/420812
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- CHG port can connect as SNK at different voltage levels
- DUT port presents as SNK only
- DUT port uses fixed polarity since it has a fixed cable
- Not supporting ALT or ALT_DP modes in terms of svdm messages at
this point.
- No support yet for USB mux.
BUG=chromium:571476
BRANCH=None
TEST=Manual
CHG port: Tested with Zinger and Plankton and 5/12/20V VBUS levels.
DUT port: Tested against Reef and verified that port reached SNK_READY.
Change-Id: Idbdc963ba077a14efad9eea3b047f35a5a605bd6
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/419117
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When including USB PD support, the image won't fit in the default RO
size of 0xf000, but does fit in the 0x10000 RW. This change removes
PSTATE and increases the RO to 0x10000.
BRANCH=none
BUG=chrome-os-partner:61170
TEST=manual
Verfied the image still builds and can run after updating via
util/flash_ec and via /usb_updater/fw_update.py -b servo_v4.json
Change-Id: I8f60bb1f107060e26390e6c8292a3add58703c0d
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/422450
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
There are plans to extend use of the LONG_LIFE_SCRATCH1 register for
other purposes than keeping board properties. Just as the board
properties, the new use is also very board specific. This patch moves
the board properties code from chip/g to board/cr50, where it belongs.
Instead of reading board properties bitmap and checking if various
bits are set, api functions are now provided to allow determining
various properties settings without actually looking at the properties
bitmap.
CQ-DEPEND=CL:*313057
BRANCH=none
BUG=chrome-os-partner:58961
TEST=verified that both Gru and Reef boot with the new image,
additionally, on Reef confirmed that it is possible to
communicate with the H1 over USB, and that plt_reset signal is
handled properly.
Change-Id: Id0dd2dc16389f773a149fb01eee1ce7bb99c4547
Reviewed-on: https://chromium-review.googlesource.com/422081
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Battery need some time to provide power when releases
shipping mode or plug in battery at first time.
BUG=chrome-os-partner:60921, 59904
BRANCH=master
TEST=remove battery & AC, then insert battery & AC,
system can boot up.
Change-Id: I33ca4df54e0b02e68ade9426864561dae8c57851
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/419881
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds a vendor command to invalidate the old rw. It should be used
when the tpm has been validated.
BUG=chrome-os-partner:55667
BRANCH=none
TEST=manual
run the vendor command
run 'ver' on the cr50 console and verify the inactive RW version
is Error
reboot cr50 10 times and make sure there is no rollback.
Change-Id: Ibec3dde77d6b1ab921e43613d54638b7318f3f57
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/420407
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The previous code split the initialization of digest_len
out into a separate area than were it was used. This confused gcc
into thinking that the variable might be uninitialized when it was
used later. By putting it all in one area, we save a couple of bytes
and make things more plain for the compiler.
This does not change the size of any ec.*.flat file.
BRANCH=none
BUG=none
TEST=build succeeds under GCC 4.9.2, 5.3 and 6.2
Change-Id: I1e21a13e3d7f9dc296296db6465ec975187a1cc0
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/411407
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Reef discharges on AC till the charger is detected and settled but
when booting from the cut-off mode this will kill the power hence
do not discharge on AC when battery is still waking up and settled.
BUG=chrome-os-partner:60974
BRANCH=none
TEST=Reef can boot from cut-off mode to S0.
Change-Id: I34c5fd8df03a1e60736541c85627fbb18a6d56f7
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/420467
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
To avoid inrush current from the external charger, enable discharge
on AC till the new charger is detected and charge detect delay has
passed.
BUG=chrome-os-partner:60547
BRANCH=none
TEST=Multiple Ramp Resets and inrush current is not observed.
Change-Id: Ie3317fa6e6c2e8f00d4ce7cb9c6bee81c50d7bb2
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/417168
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
(from CL:415672)
Slow the keyboard scan rate from 50 us to 80 us. This compensates the
additional delay added to the KBO line by Silego / H1.
BUG=chrome-os-partner:60335,chrome-os-partner:60615
BRANCH=reef
TEST=check press key "f3" then system only output "f3" scan code.
Change-Id: Icaa8f040c20f72b1fa1c9260f86b29da8c69ec2b
Reviewed-on: https://chromium-review.googlesource.com/419577
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Eve board version will use Hi-Z to get 3 values out of
each bit in the version. In order to support this read each
strap and determine the ternary encoding.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=ensure P0 reports 0 and P1 reports 1, test with an unused
GPIO to ensure that a tristate pin will also be read properly.
Change-Id: Ib1f569e2b06bed0995eb70f24c90533cbccb0fb8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/418978
Reviewed-by: Scott Collyer <scollyer@chromium.org>
cr50 has an internal pull-down on this pin so the EC should match it
to prevent leakage.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=build and boot on eve and verify hibernate enter/exit
Change-Id: I3eba0661211d356783c0c710f0d7d5fe11fd6c26
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/415225
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Turn off the charger BGATE when the system is hibernated to
save maximum power.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=build and boot on eve P0 and enter hibernate
Change-Id: I8c694789276cf4e50e32e6fe0956a3743380ca3a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/414542
Reviewed-by: Scott Collyer <scollyer@chromium.org>
If keeping HDMI/DP Type-C cable connected doing sysjump sets
HPD signal to high while it is already high from previous state,
so the SOC does not see a pulse. Manually set it low so it will
be asserted high again to send a pulse to the SOC.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=connect HDMI dongle, boot with EC SW sync enabled and see
that the display is still working in the OS.
Change-Id: I7b6ea24880bf4a0c44f7c92d9173372404d3fc4b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/414541
Reviewed-by: Scott Collyer <scollyer@chromium.org>
This change adds the plumbing for SHA-384 & 512.
The actual hash implementation is software only,
and a part of the third_party/cryptoc library.
BRANCH=none
BUG=none
CQ-DEPEND=CL:418263
TEST=TCG tests pass
Change-Id: Iba7e6d420fd7fa0bce4ad9061e00f9275ecf4d72
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/417888
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
As we are getting short on SRAM and do not need that extensive UART
debugging support, let's reduce the UART TX buffer size to a standard
value of 512 bytes.
BRANCH=none
BUG=chrome-os-partner:58961
TEST=built and booted a new image. Verified that the cr50 console
connection is still operational.
Change-Id: Ieb77671cb144b9ea5073f5d3242c9e41e5d78883
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/418948
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Deep sleep needs to be considered a normal behavior and should not add
to the rollback count. This change subtracts one from the reset count
when the system sees that it just resumed from deep sleep.
Ideally the rollback counter would be able to verify the TPM
functionality and detect rolling reboots. With this change the rollback
counter will only be able to detect rolling reboots, but it fixes the
false positives for rolling reboots we were seeing before.
BUG=chrome-os-partner:60449
BRANCH=none
TEST=manual
check the reset counter
turn off the AP
wait for cr50 to enter deep sleep
plug in suzyq
check it resumes from deep sleep and that the reset counter
still has the same value
Change-Id: Ie8490c29636403b409b2a3f0912a5b312d23bc24
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/418321
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Having cr50 resume on the falling edge of its uart rx signal is causing
some issues, and wake on low is good enough and works fine. This change
switches uart rx from DIO_WAKE_FALLING to DIO_WAKE_LOW
BUG=chrome-os-partner:60449
BRANCH=none
TEST=cr50 can still resume on uart activity and plugging in the charger
has no impact on cr50 remaining in deep sleep.
Change-Id: If77126cb64cf2fa949a75d53bb40098f037a2aa4
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/418335
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(Original CL: https://chromium-review.googlesource.com/#/c/411395/)
Enabling/Dislabling keyboard and touchpad is required to prevent EC
from waking up the system from S3 in tablet mode.
This change disables the keyboard and the trackpad when the lid goes
beyond 180 degree.
Keyboard and touchpad are also enabled/disabled by the tablet switch.
When the lid reaches 360 position, keyboard and touchpad are disabled.
And they stay disabled as long as the lid stays at 360 position.
This prevents keyboard and touchpad from turning on by the (faulty) lid
angle calculation.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I919f44bae4a13aa4d9e6072e96e46bb90c08ec22
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/417643
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When the battery is fully charged or not charging, upon removal of
the AC, discharge takes long time. To overcome this issue suspend
the DC-DC converter when discharging on AC.
(Refers Reef CL:413153)
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: Iebfcb95d0469be552283d17eb1aea0310eccbcb9
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/417428
Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com>
Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Apparently, one does not simply remove power from the trackpad and
restore it at will; the kernel needs to be involved and decide if the
device needs to be fully reinitialized, or if it was supposed to keep
some state. Therefore, let's not touch it except from startup and
shutdown and let the higher parts of the stack make the necessary
decisions.
BUG=chrome-os-partner:60478
BRANCH=gru
TEST=Boot in tablet mode and verify trackpad still works.
TEST=Go from clamshell to tablet mode and verify trackpad still works in
both modes.
Change-Id: I7674c5516ce4d237b0d2a15fb94b47e6fbe3ba39
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/417110
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The new reef form-factor, Electro, has the lid accelerometer on the
reversed side. Undo the matrix setting.
BUG=chrome-os-partner:60477
BRANCH=reef
TEST=compile, check on reef the value are incorrect.
This reverts commit 430dd5e644.
Change-Id: I0a0efc89f0fad6cce3720836caf2c52bdb7e2b8d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/416390
Tested-by: Ryan Zhang <ryan.zhang.quanta@gmail.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
gru has circuitrythat selects the charge LED color based on the
frequency of the PWM.
By adjusting the PWM frequency instead of just the duty, we gain more
control over the brightness of the charge LED.
BUG=chrome-os-partner:54155
BRANCH=gru
TEST=activate each LED in turn and confirm color and brightness
Change-Id: Ie653125a528595c1ec68aea4d02cb70595a1b151
Signed-off-by: David Schneider <dnschneid@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/415517
Reviewed-by: Shawn N <shawnn@chromium.org>
If battery is not present, input current is set to PD_MAX_CURRENT_MA.
If the input power set is greater than the maximum allowed system power,
system might get damaged. Hence, limit the input current to meet maximum
allowed input system power.
BUG=chrome-os-partner:58498
BRANCH=none
TEST=Manually tested on Reef. Removed the battery & using 'charger'
console command observed the following.
With Zinger charger at 20V - Input current is set to 2.25A
With Type-C & other chargers - Input current is set to 3A
Change-Id: Ife8686f322e095aa74b740a7c469bfe87107fb9a
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/397865
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The tablet mode value is set to 1 on each program start (RO power on
reset or any sysjump) in common tablet mode infrastructure. This
results in the tablet mode not ever reflecting current reality at the
beginning of each program. In addition to not being able to order
hook callbacks within a single hook it's the luck of the draw if
the tablet mode is set correctly if it was is being set within a
hook callback. With a lid accelerometer that doesn't work it
results in the input peripherals never being enabled.
To fix all this ensure the tablet mode state reflects the current
hardware input such that there's no ordering issues in addition to
making it reflect reality.
BUG=chrome-os-partner:60481
BRANCH=reef
TEST=With a machine whose accelerometer is unattached. Keyboard
and trackpad continue to work through suspend-resume, EC reboot,
etc.
Change-Id: I3456a7b578c9752344424721858756a33992a37d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/416348
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
When a WAIT is received in response to a request, wait SinkRequestTime
before resending the request.
BUG=chrome-os-partner:34984
TEST=make -j buildall
BRANCH=none
Change-Id: I5c8429c4a7b9cf06609996f924b8d9d535ab6b5f
Reviewed-on: https://chromium-review.googlesource.com/414533
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Common code is more flexible and supports more parts, so delete the
npcx-only register translation code.
BUG=chrome-os-partner:60029
BRANCH=gru
TEST=Manual on gru, run 'flashrom -p ec --wp-enable' and check that 0x28
gets written to SR1, which matches our desired 'protect botton 128KB',
according to the datasheet. Also run 'flashrom -p ec --erase' then read
back EC SPI contents, verify ROM is erased except for first 128KB
region.
Change-Id: I526401997ff7ec77f2a6047a4a9af74a671ed69a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/413228
Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 43634d36d273887b1f2349c333a7b4b229a83365)
Reviewed-on: https://chromium-review.googlesource.com/415498
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
- Stop charging when thermal limits are violated.
- Don't start charging if battery percent is above 95% (but continue to
charge if we're already charging).
- Don't allow battery voltage to get too close (10mA) to BD9995X VBAT
setting. If battery voltage exceeds VBAT then back boosting may occur.
BUG=chrome-os-partner:56255
BRANCH=gru
TEST=Manual on kevin, insert charger with battery at 97%, verify battery
doesn't charge and reported current is 0. Discharge down to 95% and
insert charger, verify battery charges. Charge to 100%, verify battery
stops requesting current.
Change-Id: Icc5641e88bfad7d9d8ad4b6840338541fe7ba9a8
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/403483
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/415494
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
