Change effects:
1. samus_pd: Acts as initiator of SVDM discovery once its reaches source
ready and upon identifying UFP with display port
alternate mode enters that mode.
2. hoho: Acts as responder for SVDM discovery providing its identity,
svids and svid capabilities which are display port only. If
asked to enter display port alternate mode it does.
3. fruitpie: Acts a initiator with mock display port mode.
BRANCH=none
BUG=chrome-os-partner:30645
TEST=manual,
Plug hoho into samus_pd
- see dpout
- from console
> typec 0
Port C0: CC1 451 mV CC2 111 mV (polarity:CC1)
Superspeed DP1
Change-Id: I1a76767353a69baeceffa3e79c37dcea77b8337d
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221354
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Some platforms may need to take different actions depending on which
port is requesting a limit. Add a new port parameter to the
pd_set_input_current_limit API to accomodate this.
BUG=chrome-os-partner:32003
TEST=Manual on samus_pd. Verify zinger charges battery.
BRANCH=samus
Change-Id: I1578252c751b3a80b4da6ca68e2a958934283cbf
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222621
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add support for enabling USB type-C Vconn by defining CONFIG_USBC_VCONN.
Enable Vconn support for samus, ryu, and fruitpie.
BUG=chrome-os-partner:30445
BRANCH=samus
TEST=make buildall
Change-Id: Ibe247286c96fd5a8fa12c88a4e3a5fea02997134
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222284
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The PD protocol no longer uses a SHA1 RW hash. Instead, it uses the
first 20 bytes of the SHA-256 hash. Update constants and comments
accordingly.
BUG=chrome-os-partner:31361
TEST='make buildall -j'
BRANCH=samus
Change-Id: Ice74b841dbd1d81205c1ef0079a5e18fca2153b6
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222446
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This lowers the CPU temp at which the fans start up, from 55C to
43C. It also increases the slope a bit, so that they run a little
faster as well.
BUG=chrome-os-partner:32260
BRANCH=ToT,samus
TEST=manual
Visit www.fishgl.com/?full both before and after this CL.
Before, the keyboard got a little too warm. After, the fans come
on sooner and the keyboard is cooler.
Change-Id: I5c4947c5d2bb4a28c0ac449e109e2bd1af84068c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222171
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Allows dingdong to receive initial USB PD communication (source
capabilities payload) and with some manual manipulation (see 'TEST=')
drive DPout.
CL is based heavily off hoho dongle where all files were copied from
board/hoho:
7b1e58c ectool: Add host command support to set fan RPM for each
fan separately
Files gpio.inc, board.h & board.c were modified but others should
be identical.
BRANCH=none
BUG=chrome-os-partner:31193
TEST=manual,
When attaching dingdong to samus_pd and configured via
'pd dualrole source'
I see following on samus_pd console:
C1 st9
Switch to 5000 V 900 mA (for 900/900 mA)
C1 st10
C1 st11
C1 st12
showing power constract and transition to SRC_RDY:
> pd 1 state
Port C1, Enabled - Role: SRC Polarity: CC1 State: SRC_READY
> typec 1 dp
Also if I connect in CC1 configuration and get access to dingdong
console I can
> gpioset PD_SBU_ENABLE 1
And see dingdong drive external monitor
Change-Id: I30ef6f8503a3fb015cfb8806bc36fb98f5150e40
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221913
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Fix bug that can cause ADC initialization to hang and eventually
watchdog. Problem was that you need at least 4 ADC clock cycles
between end of ADC calibration and enabling ADC (setting ADEN).
Fix is to (1) move some ADC configuration to between end of cal
and setting ADEN, and then just to be safe, (2) continually set
ADEN until we see ADRDY (ADC ready).
See bug report for more information.
BUG=chrome-os-partner:32561
BRANCH=samus
TEST=load onto a samus that regularly has ADC problems on boot.
Using power+refresh verify that without this change PD hangs
some of the time, and with this change it never hangs.
Change-Id: Ifa4c3240ad7e1612647cc74e2105e6545ed19db4
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221984
Reviewed-by: Vic Yang <victoryang@chromium.org>
Design Goals:
1. Every time the AP boots, the same default sensor settings are configured.
2. If the AP goes to suspend (S3) and wakes back up (S0),
then the AP sensor settings will be restored.
3. In S3 and in S5, only sample specific sensors that are needed.
BUG=chrome-os-partner:32368
BRANCH=ToT
TEST=Verified on Samus.
Verified suspend and resume logic with EC console messages.
- Test Case0: close lid & open lid
- Test Case1: powerd_dbus_suspend
Change-Id: I553c53e63ecfcb39d5e649a7189aa6ea02589471
Signed-off-by: Sheng-Liang Song <ssl@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220371
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Seems that all previous boards used the subvariant specific name, and had an
alias from emerge-variant_subvariant to the ec subvariant folder.
BUG=chrome-os-partner:32331
BRANCH=None
TEST=cd board/pinky; make clean && make -j && ../../util/flash_ec --board=pinky
Change-Id: Ie6e0c977b6659687357a1b5aa2915cf0e40a5da7
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221904
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Add a minor revision to the PD device hardware ID field in the info
custom VDM and set increment this minor ID from 0 to 1 for zinger.
This differentiates zingers for the auto-update payload, so we can
update only those with a specific major and minor ID version.
BUG=none
BRANCH=samus
TEST=load onto samus and zinger. when connect zinger, see on PD
console: Dev:0x0401 SW:2289 RW:0, which shows the appropriate
device ID.
Change-Id: I482ee2d850332b608cdd81537f68d4dc509bfc1a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221320
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Send host event to AP when we receive info VDM from a PD device.
This allows the AP to potentially send an update to the device.
BUG=none
BRANCH=samus
TEST=load onto samus. when zinger is attached, verify that
EC sends host event to AP.
Change-Id: I10961ab60fb752e2e40a21d9351bd1ba98cc11da
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221162
Reviewed-by: Todd Broch <tbroch@chromium.org>
Changed sending of info VDM from the UFP side in SNK_DISCONNECTED
to the DFP side in SRC_READY to match the PD spec. Only the DFP
is supposed to send VDMs, and by default the power source is the
DFP. This affects simple DFPs such as power adapters, they must
initiate the info VDM once a power contract has been negotiated.
BUG=none
BRANCH=samus
TEST=load onto samus_pd and zinger and make sure that when you
attached zinger to samus, samus receives info VDM and prints out
something like:
VDM/7 [11] 18d1000b
Dev:1 SW:2280 RW:0
Change-Id: I16ceac31939fdc1c74be7323e628dd8706e1283b
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221174
Reviewed-by: Todd Broch <tbroch@chromium.org>
Disable hibernate by default on zinger because some EVT zingers
do not wake up on connect due to hardware problem.
BUG=chrome-os-partner:28335
BRANCH=samus
TEST=load onto zinger, leave disconnected for 60s, make sure it
doesn't go into hibernate
Change-Id: I9f5f9fb1ce349ea862652cd38aa5d1e521234b30
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221478
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is mostly the same as previous commits, but with increased delay.
Previously, we have short delays (e.g. 3ms) which is too short and may
cause instability.
Now that we have slowed down the time when running unit tests and
increased the delay, this shouldn't cause problems anymore.
BUG=chrome-os-partner:31200
TEST=Repeatedly run multiple unit tests in parallel.
BRANCH=Samus
Change-Id: Ib55e3adc5fd27a8e233996b4799dab3cefd62318
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220734
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Automatically go into hibernate (standby mode) if not powering
anything for 60 seconds. Will wake up when it is plugged into
something (senses pull-down on CC line).
BUG=chrome-os-partner:28335
BRANCH=samus
TEST=load onto zinger. if disconnected for 60s, see hibernate
print on zinger console. when connected to a device, verified
it boots again.
Change-Id: I2564c6192395bb5e4f6d7586c2725f13a4581049
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220837
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The Zinger RW is now signed with 2048-bit RSA key (using SHA-256 as
digest).
This CL implements the verification mechanism.
note: the RSA key used for signing must be provided as a .pem file.
The path to .pem file must be provided in the PEM environment variable.
By default, it's using the dev key stored in zinger_dev_key.pem.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:28336
TEST=on Zinger, run with properly signed RW firmware and corrupted
firmware and check the serial traces.
Change-Id: Ia58482458904a3ed72d6b0e95996cae86a0ead83
Reviewed-on: https://chromium-review.googlesource.com/220178
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Minimuffin is identical to zinger, same MCU, same gpio, same
circuitry aroundt the MCU with two differences:
- Rated current is 2.25A instead of 3A
- USB PD hardware device ID needs to be different so that host
can differentiate between the two.
Due to the similarity between the two, minimuffin is defined
as a symlink to the zinger board.
BUG=none
BRANCH=samus
TEST=make BOARD=minimuffin
load onto a zinger and verify that samus reads device ID correctly
and limits input current limit to 2.25mA.
Change-Id: Ie39ec43262c7d14663eb68abff073bfeec451a24
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220689
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Silego variant in pinky rev2 require the signal to be inverted.
BUG=None
TEST=on pinky-rev2: all keys from col2 work correctly
BRANCH=None
Change-Id: I83a029b4e9c6b4770e83f30b170595d45ea40cca
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220314
Enabled deep sleeping during S0. This was previously inhibited by
SLEEP_MASK_AP_RUN but the new config option (CONFIG_LOW_POWER_S0) will ignore it.
SPI needed a sleep mask, it essentially gets enabled and disabled whenever the
CS changes. Warning: waking up when the CS falls takes a little time, if the AP
sends fast data before the 48MHz clock is enabled characters will get corrupted;
leave about 30uS time for the clock to start.
CQ-DEPEND=CL:219997
CQ-DEPEND=CL:220243
CQ-DEPEND=CL:220461
BUG=chrome-os-partner:32223
BRANCH=none
TEST=load onto pinky, boot the AP(S0), use idlestats command to verify
that we are going into deep sleep (STOP mode). Verify that everything works
normally during S0(SPI, keyboard, anything that requires the EC to wakeup).
Change-Id: I81c4fa472332f1ad8ad93301089a99dcdb108948
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219555
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Currently, when an assertion fails, the error message is like:
ASSERTION FAILURE '1 + 1 == 3' in command_apreset() at common/chipset.c:24
To save flash space, let's add an option to remove the failed
expression and function name. The error message becomes:
ASSERTION FAILURE at common/chipset.c:24
BUG=chrome-os-partner:32203
TEST=make buildall
TEST=Add an assertion and triggers it. Check error message.
BRANCH=None
Change-Id: Ie323d5b43cbff2cd8f6cd5bb46c1f34ecd16bd5e
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219670
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Sometimes I2C1 is wedging and this can cause the ALS task to
overflow its stack.
As a temporary measure to stop the random reboots increase the
ALS task size.
BUG=chrome-os-partner:32471
BRANCH=samus
TEST=build and boot on samus with stuck I2C1
taskinfo before (after fresh reboot):
2 ALS 00000000 0.001012 364/384
taskinfo after (notice it is >384 after some time):
2 ALS 00000000 0.031586 400/512
Change-Id: I04e9b93d3cc60afd3303eb4610c81952f365b992
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220442
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This pin is already set to out+low so it should be fine to rename
it on EVT1 boards.
BUG=chrome-os-partner:32031,chrome-os-partner:32359
BRANCH=samus
TEST=make buildall
Change-Id: I0d904b0301b793bbfa1d829b4fce60e0b1154b00
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220259
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add low power mode for zinger. This uses stop mode in task_wait_event(),
the non-runtime equivalent of the idle task.
BUG=chrome-os-partner:28335
BRANCH=samus
TEST=load onto zinger and plug and unplug into samus a bunch of times
to make sure it negotiates to 20V every time. also send custom vdm's
from samus_pd and make sure those always succeed.
Change-Id: I626365e7d22e030792d28dbf7eafaeb8f54f8a74
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219933
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Enable flash prefetch buffer for stm32f0 chips to make for
faster CPU execution.
BUG=none
BRANCH=none
TEST=load onto samus_pd and zinger. let run for a while.
connect/disconnect AC a few times. boot samus.
Change-Id: I88c0ae67a3205987344552f5b44952f9890c8177
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219921
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Enable low power idle for veyron (with uart wakeup as well).
Low power idle is only active in S5/S3.
Also sorted options from board.h
BUG=chrome-os-partner:31226
BRANCH=none
TEST=load onto pinky-proto1, use idlestats command to verify that we are going
into deep sleep (STOP mode). Run 30 min. and verify no watchdog reboots or
anything out of ordinary.
Change-Id: Id14b04f33ea46b1e6cca1c8e812b5875e9ee0446
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219044
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Fix potential bug in ADC initialization. After setting ADEN bit to
enable ADC module, we must wait for ADRDY (ADC ready) bit before
continuing. This bug only affects a few chips, and only some of
the time.
BUG=chrome-os-partner:31978
BRANCH=none
TEST=Used a samus board where the PD MCU fails ADC initialization
quite often. Without this fix, if you reboot the PD MCU, it will
sometimes come up with all ADC's reading 0 and ADEN reading 0.
With this fix, it always boots with the ADC's working
Change-Id: Iba1d0e56006ba1ad6d9f0eee964a70ef2d0f8dcf
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219522
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
This code is used to find the orientation of the sensor.
Given sensor are aligned with the edges of the device,
it is not too dificult to find manually.
BRANCH=ToT
BUG=None
TEST=Check ACCEL_CALIBRATE is not used anymore.
Check 'make buildall -j' works.
Change-Id: I81ffcb4f6b01c530ef16baf13113a5942f615092
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219527
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This task echo's all bytes from any console stream back to all
other console streams. It is a test case for the new
multi-USART and USB stream drivers.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Manual testing of cutting and pasting large blocks of text
into the echo'ed usarts, and verifying no dropped characters.
Change-Id: I408c77e40931d3a473657326f9772e71a7ae8a60
Reviewed-on: https://chromium-review.googlesource.com/213178
Reviewed-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
'powerindebug' is only used when there is a problem with power
sequencing. 'taskready' is rarely used and the same info can be
retrieved by 'taskinfo'.
Put both behind config flags and disable 'taskready' by default. Also
disable 'powerindebug' for Ryu.
BUG=chrome-os-partner:32203
TEST=Build Ryu and check flash space used.
BRANCH=None
Change-Id: I753a1f5411d6e840a80aba03afc94f9640d381a8
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219490
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When a cable is connected, set USBC_POLARITY to the right polarity. This
is done in a different way than how we do this on other boards because
we only want to control polarity automatically on cable connection.
BUG=chrome-os-partner:32163
TEST=Flip the cable, check USBC_POLARITY changes.
BRANCH=None
Change-Id: I903123b8fd729e8c913014b83812d20328600f8e
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219291
Reviewed-by: Alec Berg <alecaberg@chromium.org>
When 5v/12v/20v buttons are pressed, plankton first switchs to source
role, set the requested source cap, and then perform a soft reset.
However, if plankton was sink and just switched to source, the port
partner might not have switched to sink and this leaves the CC line in a
state where communication is not possible. The subsequent soft reset
then fails. If we are not already sourcing power, we actually don't need
a soft reset after changing source cap.
BUG=chrome-os-partner:32163
TEST=Switch from sink to source. Doesn't see "soft reset" in console.
TEST=Switch from 5V to 12V. See "soft reset".
BRANCH=None
Change-Id: Ia4b834c2e7dc1324b9143c46a72938845499e2fb
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219004
Reviewed-by: Alec Berg <alecaberg@chromium.org>
On power-on reset, the USB hub might get stuck in a locked state due to
a race condition in hardware. Let's reset the hub after 0.5 seconds to
make sure this doesn't happen.
BUG=chrome-os-partner:32163
TEST=Power on the board. Measure the reset signal.
BRANCH=None
Change-Id: I0f89883c5db7c5376f3612da1615ba4f86b5efa6
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219199
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Enable low power idle for samus_pd. Low power idle is only
entered when no USB PD device is connected.
BUG=chrome-os-partner:31226
BRANCH=none
TEST=load onto samus_pd, use idlestats command to verify
that we are going into deep sleep (STOP mode). Run 30 min.
and verify no watchdog reboots or anything out of ordinary.
Also, verify that host commands from EC work when going into
deep sleep by sending host commands on the EC console with
pdcmd 0 0.
Change-Id: I3e2e04e6c4c0a84e291286dbed90945847e0dfdd
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218957
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
OSPEEDR cfg for PB15 was inadvertently set to '01' for PB15 (should be
'00'). Not sure it causes any harm but shouldn't be set according to
comment which is speeding up output pins on SPI interface PB12-14
only.
BRANCH=none
BUG=none
TEST=manual, compiles, boots, talks PD w/ samus_pd.
Change-Id: Ibc2ec1c427a2c3c92ffdf424b668752b1c0b0032
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217963
Reviewed-by: Vic Yang <victoryang@chromium.org>
