The WebUSB specification defines a specific Platform Descriptor in the
Binary Object Store:
https://wicg.github.io/webusb/#webusb-platform-capability-descriptor
This descriptor provides a special 'Landing page' URL to the host
browser and associated privileges for it.
Bump the USB version for BOS descriptors to 2.1 to be compatible with
Chrome implementation.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=none
BRANCH=twinkie
TEST=manual: on Twinkie (chip/stm32) and HG proto2 (chip/g), enumerate
WebUSB descriptors with lsusb and connect to a WebUSB page in Chrome
R61+.
Change-Id: I7211ab554f4a6c156c1e8e79a3d9f0d6644217c6
Reviewed-on: https://chromium-review.googlesource.com/664813
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In the USB 2.0 specification, the "8.5.3 Control Transfers"
chapter says that "When all of the data structure is returned to the host,
the function should indicate that the Data stage is ended by returning a
packet that is shorter than the MaxPacketSize for the pipe. If the data
structure is an exact multiple of wMaxPacketSize for the pipe, the function
will return a zero-length packet to indicate the end of the Data stage."
When doing a 'Control Read' transfer and the returned data (in IN
packets) was a multiple of MaxPacketSize, we were omitting the
zero-length packet and so the host was blocked waiting for a successful
IN transaction.
This corner-case was a regression introduced by the re-writing of the
control transfer handling done by CL 318864. So the STM32 USB code which
is similar to the former code is dealing properly with this case.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=cr50
BUG=none
TEST=manual, extend the configuration descriptor to be exactly 64 bytes,
and see the enumeration is no longer failing.
Change-Id: I108e8c6bb9eb727c41f3e1c607f0919fa1192d5a
Reviewed-on: https://chromium-review.googlesource.com/664814
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
lsusb scans for USB_DT_DEBUG, which produces logspam
on the cr50 console. This isn't an error, just unimplemented.
Remove the printout.
BRANCH=cr50
BUG=b:65407184
TEST=no logspam on lsusb
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: Ib4fc7105015506927f45ee02f587f97e46e1ad9b
Reviewed-on: https://chromium-review.googlesource.com/663786
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In USB FS on a bulk/interrupt endpoint, the transactions normally toggles
between DATA0 and DATA1 PIDs.
After a USB suspend/resume cycle, we need to restart from the PID we
were at before suspend.
In our current code, when going to deep-sleep during USB suspend, we are
re-initializing everything when the MCU restarts at each resume. So we set
implicitly the PID to DATA0. The USB Hardware IP just silently discards the
packet when the PID of an incoming OUT packet is not matching the
expectation in the endpoint register.
In order to preserve DATA PIDS, record the state of the PID toggling on
each endpoint when going to deep-sleep and restore it during the USB
initialization.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:38160821
TEST=manual, plug a HG proto2 on a Linux host machine and enable
'auto-suspend' for this USB device. Let it go to sleep and wake-it up by
sending a U2FHID request. Repeat the process several times and see that
the key answers every time (while it was failing after the second cycle
before).
Change-Id: I75e2cfc39f22483d9e9b32c5f8b887dbafc37108
Reviewed-on: https://chromium-review.googlesource.com/655238
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Currently, only usb_pd_protocol.c cares about the actual ccd mode
(disabled/partial/enabled). Everything else just cares whether it's
enabled or not. So promote the boolean ccd_is_connected() from
board/cr50 up to chip/g, and rename it to ccd_ext_is_enabled() to
match the new nomenclature (since 'CCD' itself is now too overloaded).
This will make it easier to handle CCD state directly in board/cr50
after we split it from common/case_closed_debug.c
BUG=none
BRANCH=cr50
TEST=make buildall; boot cr50; make sure USB endpoints still work
Change-Id: Ic3df7467bfe29f1c5d7060cac1309a1f0e090d9e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/648212
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
CCD_CHANGE_HOOK should use CONFIG_CASE_CLOSED_DEBUG_V1.
All boards which use chip/g either use both CONFIG_USB_SERIALNO and
CONFIG_CASE_CLOSED_DEBUG or neither of them, so just depend on
CONFIG_USB_SERIALNO.
This is in preparation for making common/case_closed_debug refer only
to the usb_pd_protocol version (with mode=disabled/partial/enabled),
and cr50 will have its own version (with only enabled/disabled, and
tied more closely to CCD config).
No functionality changes.
BUG=none
BRANCH=cr50
TEST=make buildall -j; boot cr50 and see change hook called
Change-Id: I1985c8c48c1a85fed4549402a7b47b8a9cf135d7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/648067
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Add a delay to allow the clocks and usb signals to settle.
BUG=b:63767046,b:63867566
BRANCH=cr50
TEST=put the eve ec into hibernate, wait until cr50 enters deep sleep,
use the uart to wake it up, and verify that it eventually reenters deep
sleep
Change-Id: I26463ce3e00996368a791a245b0f9de01737478c
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/598448
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Save a small amount of time when the USB resume is making the chip boot
from deep-sleep by removing the verbose serial traces in main and
increasing the usb initialization priority.
This brings us from borderline timings wrt the USB specification to a
reasonable margin.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:38160821
TEST=run on hotelgolf, go to deep-sleep on USB-suspend.
On USB resume, measure the time from CPU boot to the end of usb_init
using the CPU cycle count. We are shaving 1.3ms.
Change-Id: Ia5bf69c0ca26748dec59a87f3908a5fe68296b36
Reviewed-on: https://chromium-review.googlesource.com/563206
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Remove the code switching between PHY0 and PHY1. We now only use the CCD
PHY on all boards.
BUG=b:36488273
BRANCH=cr50
TEST=ccd works fine. cr50 usb doesn't show up on the AP. You cannot
switch the PHY on cr50.
Change-Id: I6ff641af9d7129daa8592f952f9df97c3862395b
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/595201
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
One Time Programmable memory can be used to store permanent data like
serial numbers.
Reorganize the code to support writing serial number to OTP, in
addition to pstate (if using its own memory bank) or autogenerate from
unique id (hammer).
+ Add CONFIG_OTP to enable OTP code
+ Add CONFIG_SERIALNO_LEN to indicate the size of the serial number
string. Currently set to 28, when USB serial number is needed.
+ Expose flash_read|write_pstate_serial and add otp_read|write_serail,
remove more generic flash_read|write_serial.
+ Make board_read|write_serial generic, declared outside of USB subsystem.
Priority order to read|write serial string:
- board definition (like hammer)
- pstate location, if stored in its private memory bank
- otp area
If none of these methods are available, a compilation error is raised.
BUG=chromium:746471
BRANCH=none
TEST=compile
Change-Id: I3d16125a6c0f424fb30e38123e63cf074b3cb2d3
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/580289
Reviewed-by: Nick Sanders <nsanders@chromium.org>
When (USB-)resuming from deep-sleep, ensure that we avoid switching back
and forth the selected USB PHY at boot, in order to avoid having a
short disconnection at resume.
To achieve this, allow the board configuration to select the PHY it is
really using with the CONFIG_USB_SELECT_PHY_DEFAULT configuration
variable, still keep the default USB_SEL_PHY1 as before.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:38160821
TEST=manual: build 'proto2' firmware with CONFIG_LOW_POWER_IDLE defined,
with the chip connected to the host on PHY A, make the host issue a USB
Suspend then resume and see no disconnection.
Change-Id: I7abd5e338e5c688c2dd486293f520049cdfd273b
Reviewed-on: https://chromium-review.googlesource.com/501947
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Let's split the usb headers in 3 different parts, instead of having
usb_descriptor.h pull in usb_hw.h and usb_api.h.
- usb_api.h: EC functions related to usb (e.g. connect/disconnect)
- usb_descriptor.h: common USB names and structures
- usb_hw.h: Functions required for interactive with EC's USB HW
BRANCH=none
BUG=b:35587171
TEST=make buildall -j
Change-Id: I37ead61e3be5e7ae464f1c9137cf02eaab0ff92e
Reviewed-on: https://chromium-review.googlesource.com/454861
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
To make sure cr50 usb works, we need to disable sleep immediately
after the usb controller detects that usb has resumed. The usb WKUPINT
is asserted on usb resume, but cr50 doesn't currently respond to that.
This change umasks the usb wakeup interrupt, so that USB ISR will
disable sleep on resume.
BUG=b:35774906
BRANCH=none
TEST=Run 100 'usb_updater -f' 100 times sleeping 20 seconds in between
each run. Verify there are no failures and cr50 still goes to sleep
between each run.
Change-Id: I1819deaa3988bcf2a85686d1b9d57092ba264c4d
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450900
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
We had disabled wakeups on the AP phy when we were running on gru,
because the AP phy was not in use. We never changed that for reef, so
UTMI wakeups were disabled even when the AP USB was supposed to be
enabled. After Cr50 went to sleep any usb transactions would drop bits,
because Cr50 wouldn't notice anything was happening until it woke up on
one of the HOOK_TICK events.
This change reenables UTMI wakeups on boards with AP usb. It writes 1 to
USB_PCGCCTL_STOPCLK. This makes the controller disable the PHY clock
whenever it detects a usb suspend. When it resumes out of suspend, this
bit has no effect.
BUG=b:35774906
BRANCH=cr50
TEST=Boot up reef. Wait until cr50 goes to sleep run 'usb_updater -f'
and verify that it runs successfully. Make sure deep sleep still works
Change-Id: I54bd866111b5c9b5738575f23757e0cbe4907ec4
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/448988
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
USB uses a special mode the trigger remote wake-up during host
suspend, by setting the K-state on the data differential pair,
and setting a bit in the USB config descriptor attributes field.
Let's enable that so that hammer can wake up host from S3.
BRANCH=none
BUG=chrome-os-partner:62325
TEST=Connect hammer to chell, put chell in S3. Press a key (or use
("kb 3 3 1; kb 3 3 0" in console), or touch trackpad =>
host wakes.
Change-Id: Ib7b1e9047e01869f07ddd771c9c9bc640eef10d6
Reviewed-on: https://chromium-review.googlesource.com/446240
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The RESETDET and USBRST USB interrupt status bits are often set
together. There is no point in resetting USB twice.
BRANCH=none
BUG=none
TEST=verified that cr50 still operates fine of Reef and ec and ap
consoles are available (still intermittently).
Change-Id: I467d975a3a5955b6072a2a3376de7a1501e7c6c5
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/404910
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
To be able to identify different cr50 devices connected to the same
machine we need a serial number. This change uses dev id 0 and 1 to come
up with one.
BUG=chrome-os-partner:56641
BUG=chrome-os-partner:58342
BRANCH=none
TEST=lsusb -vd 18d1:5014 | grep iSerial shows different numbers for
different devices. Verify when ccd is disabled the serial number is 0.
Change-Id: I85c54af4a21bdfd0542019c02aa8420d9a879fae
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/395633
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
- changed the pad assignment for plt_rst_l from DIOA13 to DIOM3;
- removed the board property used to keep uart rx disabled, Uart0 is
now enabled by default on Cr50.
- removed resetting fallback counter on USB updates for reef boards,
they are going to use the same mechanism as kevin and gru.
BRANCH=none
BUG=chrome-os-partner:56540
TEST=Tested on Reef Board ID 1 and Gru Board ID 1. Verfied that
plt_rst_l signal is being detected and that there are no
interrupt storms related to not having a pullup resistor on the
uart rx line. Verified that both platforms successfully boot into
chrome OS using cr50 TPM.
Change-Id: I300a0c75e60acbecf93500b46aced303955a192a
Signed-off-by: Scott <scollyer@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/391140
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
There is now a call to reset the retry counter before the hard reset
after an update. Cr50 will use the updated image for the next 5 boots,
but on the 6th it sees the retry counter is greater than 5 and then
jumps back to the old image. Cr50 needs to call
system_process_retry_counter to reset the counter and corrupt the old
image header to prevent falling back to the old image.
Normally the reset counter would be processed after it receives a TPM
command. Reef does not have Cr50 TPM support. Until Cr50 has TPM
support for Reef, Cr50 should have a different point to know when the
update is good. This change adds a board property to mark the process
the reset counter once the Cr50 USB controller receives a set address
request from the host. On Reef the controller defaults to the AP PHY
when suzyq is not connected, so it should have a connection to the AP
or through suzyq after boot.
The board property is only added to Reef. Behavior on Kevin and Gru is
unchanged.
BUG=chrome-os-partner:56864
BRANCH=none
TEST=update reef. Wait until Cr50 prints 'SETAD' then run 'rw
0x4000012c' and verify it is reset to 0.
Change-Id: If517202f25a694cd70550e3be047ea502e7c5383
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380354
Since pretty much always, we've declared console commands to take
a "longhelp" argument with detailed explanations of what the
command does. But since almost as long, we've never actually used
that argument for anything - we just silently throw it away in
the macro. There's only one command (usbchargemode) that even
thinks it defines that argument.
We're never going to use this, let's just get rid of it.
BUG=none
BRANCH=none
CQ-DEPEND=CL:*279060
CQ-DEPEND=CL:*279158
CQ-DEPEND=CL:*279037
TEST=make buildall; tested on Cr50 hardware
Everything builds. Since we never used this arg anyway, there had
better not be any difference in the result.
Change-Id: Id3f71a53d02e3dc625cfcc12aa71ecb50e35eb9f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/374163
Reviewed-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The parse_bool() function exists so we don't have to litter our
console commands with stuff like this:
if (!strncasecmp(argv[1], "on") ||
!strncasecmp(argv[1], "enable" ||
!strncasecmp(argv[1], "true" ||
[...]
This CL uses parse_bool instead of that kind of thing so I don't
have to remember which commands use "enable" and which use "on"
and so forth.
I only changed the commands that Cr50 uses.
BUG=none
BRANCH=none
TEST=make buildall; test on Cr50 hardware
I tested all the affected commands to ensure that they still work
correctly: usb, ccd, flashwp (which doesn't do anything anyway).
Change-Id: I7d875ab22934fb4b500e3d0f62ebe3e04101272d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/373658
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Servo_micro sets usb config maxpower to 100mA.
Servo_v4 is set to self powered as it's powered by a
shared vbus and not be the bub it's connected to.
cr50 is self powered as no power is transmitted as part of CCD.
* Add CONFIG_USB_MAXPOWER_MA to define USB maximum power draw requested
per board.
* Add CONFIG_USB_SELF_POWERED to indicate that a device is not
powered by allocated USB power.
BUG=chromium:631302
TEST=lsusb reports 100mA bMaxPower (micro), Self powered (v4)
BRANCH=None
Change-Id: I79b8ce46f32d94f16104a4a8080104e30dce7f2c
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363153
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The USB controller should disable the PHY itself when usb is released,
but from the power tests I ran it does not. This change adds a call in
usb_release to deactivate the PHY.
It looks like having the AP on vs off also makes a difference in power
consumption. I am looking into that now, but until that is resolved turn
of the AP off while testing this USB change to see the effects on power.
BUG=chrome-os-partner:54331
BRANCH=none
TEST=manual
Without deactivating the PHY put cr50 into deep sleep on gru.
run 'reboot ap-off'
measure pp3300_haven_mw and it is around 4.5mW
Add deactivating the PHY during usb_release.
Put cr50 into deep sleep
run 'reboot ap-off'
measure the power and the average should be around 2mW
Change-Id: I16e6885a4e40c78e81d9bbc42c9af79e5f55047e
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362159
Commit-Ready: Dan Shi <dshi@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Instead of enabling the SOF calibration at usb_init(), enable it
only when the first SOF packet is seen following the usb_init(),
as suggested in the recommendations document linked from the bug
report.
Also fix the code to do the right thing. The original reference
code had errors.
BUG=chrome-os-partner:50800
BRANCH=none
TEST=make buildall; test on Cr50
After adding some instrumentation code, I see the SOF being
detected and the calibration started. It only happens once after
each usb_init() and only when the USB traffic begins.
Change-Id: Id2b9a41d90ce9cc9e467fb759463d69a57bb5540
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/350371
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The timer clock nominally requires no firmware settings. It is
tuned in manufacturing to be centered around 24MHz. However, it
will potentially migrate away from 24MHz based upon variations in
temperature and voltage. The variation is approximately
0.1-0.5MHz, based upon functional simulations, and backed up with
observations in the lab. This CL enables a hardware feature to
dynamically tune the timer clock if the device has an active USB
port, by monitoring the SOF (start of frame) USB packets that are
sent by the USB host every milllsecond with 500ppm accuracy.
BUG=chrome-os-partner:50800
BRANCH=none
TEST=make buildall; run on Cr50 hardware
Verified that deep sleep, USB suspend/resume, etc continue to
work with this enabled. Not too surprising, since I've never
encountered a problem without it.
In addition, I monitored XO_CLK_TIMER_CURRENT to see that the
timer adjustments are being made while connecting and
disconnecting from USB, entering andleaving sleep and deep sleep,
etc. They are.
Change-Id: I328b6416bc40ef8718815c5e09cf91ec1c6646f0
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342145
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This adds support for RD Detection on cr50. It can be used to detect a
debug device and signal the controller to switch from the AP PHY to the
to CCD PHY. When RDCC1 and 2 no longer detect the debug device, then
the controller switches back to using the USB to AP PHY.
BUG=chrome-os-partner:50700
BRANCH=none
TEST=change the value on RDCC1 and RDCC1 and check that the usb
controller connects to the right PHY.
Change-Id: Ice01a45a31fe1932945f89df2e3b851f4d287a17
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338454
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
While kevin is still in development default to connecting to the CCD PHY
instead of the AP PHY. This will automatically enable CCD instead of
having to rely on things working to detect the debug accessory and
switch to the proper PHY.
We also disable the TX lines to the AP and EC, in case servo is
connected. To turn them on manually, use these console commands:
rw 0x40060040 74
rw 0x400600c8 78
pinmux
gpiocfg
BUG=chrome-os-partner:50700,chrome-os-partner:52281,http://crosbug.com/p/52322
BRANCH=none
TEST=hook up suzy q to kevin. Run 'lsusb -vd 18d1:5014' and check that a
device appears.
Change-Id: Ic2802430680adc6186982022c995ee6f452b45fd
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338680
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Trybot-Ready: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
This adds a command to connect or disconnect, and to switch the
PHY between A or B.
BUG=chrome-os-partner:52055
BRANCH=none
TEST=make buildall; test on Cr50
Using a test board with both PHYs plugged in, try the various
commands:
usb off
usb on
usb a
usb b
The on/off option connects and disconnects, the a/b option
switches between PHYs. You can see the state change on the
console, or by running dmesg on the host.
Change-Id: I4c77e9c586ce197dc99b0b50af7396c253a1a377
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/337706
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This is still in testing mode, so you have to take special steps
to enable it (keep reading). But if you do the right dance, it
does go into deep sleep for USB suspend, and resumes correctly.
However, it doesn't yet wake for any other reason. That's coming next.
Normal sleep is not yet supported, either.
BUG=chrome-os-partner:49955, chrome-os-partner:50721
BRANCH=none
TEST=make buildall; extensive tests on Cr50
Testing is a pain.
First, you can't print anything in the idle task, because that
just makes it stop being idle, so the only way to detect when
it's triggered is by wiring up a GPIO and instrumenting things.
Second, you have to manually reenable USB suspend on the host
every time the Cr50 boots with
echo auto > /sys/bus/usb/devices/<BLEH>/power/control
where <BLEH> is the correct device.
Third, for reasons probably related to the mysteries of HID
devices combined with crbug.com/431886, you have to build the
firmware without CONFIG_USB_HID (and the related items in
board.h)
Finally, because it's still a work in progress, you have to type
idle d
at the serial console after every boot (or resume) to reenable
deep sleep in the idle task.
If you do all that, then you'll see that it does go into deep
sleep. Ping it again with "lsusb -v -d 18d1:5014" or
./test/usb_test/device_configuration, and it wakes up and
responds!
If you disconnect the USB while it's in deep sleep, it stays
asleep. When you plug it in again, it wakes up, but it correctly
recognizes that it shouldn't resume and does a normal reset
instead.
Change-Id: I3cc66e48ce671142a4d12edbe0eb9fdacecea0d9
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/336279
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
This adds USB support to Set and Get the Device Configuration.
These control transfers are standard device requests that need to
be added in order to behave properly for USB suspend/resume (and
in general). Before this CL, the Get command always failed and
the Set command had no effect internally. With this CL it works.
Note that this particular change only supports ONE configuration
for the Cr50. If/when we add additional configuration
descriptors, we'll need to update it again.
BUG=chrome-os-partner:50721
BRANCH=none
TEST=make buildall; manual tests on Cr50
This CL includes a test program. Connect the Cr50 to the build
host, and use that program to read and change the configuration.
cd test/usb_test
make
./device_configuration
./device_configuration 0
./device_configuration 1
./device_configuration 2
You may need to use sudo if your device permissions aren't sufficient.
Change-Id: Id65e70265f0760b1b374005dfcddc88e66a933f6
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/335878
Reviewed-by: Scott Collyer <scollyer@chromium.org>
We clear global NAKs by writing bits in the USB_DCTL register.
However, prior to this CL we were overwriting the entire
register, not just touching individual bits.
Since we've never actually set any global NAKs, this mistake
didn't have any noticeable effects. But we should still do the
right thing in case we need it later.
BUG=chrome-os-partner:50721
BRANCH=none
TEST=make buildall; test on Cr50
No visible change; everything continues to work.
Change-Id: Ia25d95dc6211e5460132622ac005723f43b00e24
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/335190
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We were referring to unhandled USB control messages as errors,
but they aren't necessarily. Sometimes they're optional things
that aren't fatal. We should still address them, but we don't
have to freak out.
BUG=none
BRANCH=none
TEST=make buildall; test on Cr50
Change-Id: I892acec2d89b8ec95353cdc09f3e49aa78b1704d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/335200
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This cleans up a great deal of flakiness that we've seen on the
USB for a long time. I was misinterpreting and/or misimplementing
some of the documentation. This seems to make all the difference.
BUG=chrome-os-partner:50370
BRANCH=none
CQ-DEPEND=CL:328979,CL:*249229
TEST=make buildall, and test on Cr50
Before this CL, the USB connection would only work on USB2.0
buses, connected directly to my workstation. With this CL, it
works on USB2.0, USB3.0, through hubs, etc. Yay!
Change-Id: Icfa1910bf34f73332e2f8fc4f0d6789541549493
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/329262
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Change the report_error() macro that we use to indicate unhandled
conditions so that it can take an integer argument. Sometimes
that's useful.
BUG=none
BRANCH=none
TEST=make buildall, try some USB stuff, everything still works
No functional difference, console error output only.
Change-Id: Icdfd1f9162bb5e557c711b6363b73ef55fbc272d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/328490
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
With transitioning to silicon there is no need to check if the
hardware includes USB subsystem or not.
BRANCH=none
BUG=chrome-os-partner:50141
TEST=the cr50 image successfully boots to the ec prompt
Change-Id: I593205cf307e0fce5e74ea695ed1cf5bfea8fde4
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/326482
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This is a rewrite of the Cr50 USB Device Control Endpoint
implementation, using the instructions in the DWC USB 2.0 OTG
Programmer's Guide (such as they are). Some of the major
differences:
* Not every USB interrupt indicates the receipt of an incoming
packet. Many merely provide updates on packet transfer status,
transaction stages, or other activity. We handle those
cases correctly.
* We may need to start a new Control transaction at any point,
even in the middle of an existing transaction.
* Large IN data transfers can be handled with one interrupt by
chaining multiple together.
* Logical separation of the phases of each transaction (Setup,
Data, Status).
That said, while this CL matches the Programmer's Guide fairly
closely, that Guide is pretty crappy and this is just the first
commit. There is still a fair amount to do (marked with comments
and bug reports). However, it works at least as well as the
previous version and is much closer to what the supplier claims
is the correct implementation.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
We also connected this device to Windows, and Mac laptops (and a
Chromebook) and used a USB bus analyzer to monitor the behavior.
It works on machines those, too.
Change-Id: Ic515ea83e217a8d0552d61ac5eb19693661fcd15
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/318864
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
This allocates more space for FIFO buffers, according to the
instructions in the Programmer's Guide. Many more comments and
some slight refactoring was added to explain the configuration
more clearly.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: I1a870a4b1dc628729f7cd1b80bab7ec6dfd11f37
Reviewed-on: https://chromium-review.googlesource.com/318262
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
No new functionality, just a little refactoring and general
cleanup of the USB initialization steps.
BUG=chrome-os-partner:34893
BRANCH=none
CQ-DEPEND=CL:317376
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
Change-Id: Ia6922acf82a793759870a61217562f4e63608a80
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317319
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
No new functionality, just adding stub handlers for some
additional USB interupts that we'll eventually need to deal with.
BUG=chrome-os-partner:34893
BRANCH=none
CQ-DEPEND=CL:317354
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
Change-Id: I805ac00432c31735d2904227c5d19ad53cfa7ccb
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317376
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
The control endpoint (EP0) can receive some Setup packets that
are specific to individual Interfaces. The USB_DECLARE_IFACE
macro is used to register the callbacks that an interface
implementation provides to handle those Setup packets.
This change cleans up the callback API a bit, so that we don't
have to export the internal workings of the Cr50's EP0 interrupt
handler.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
Change-Id: I9ac22f6a74f360f201c58e9ef39e3576834578a8
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317269
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
No functional changes, just some additional debug stuff that's
not normally compiled.
BUG=none
BRANCH=none
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
Change-Id: I32b4944c01006f2e9c8cdb2e732a4b1710a60e19
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317560
This just replaces a few manually created macros in
chip/g/registers.h with a more programmatic version based on
names in chip/g/hw_regdefs.h.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall; run it
No new functionality, just refactoring.
Change-Id: I73ee2ee1ee3f53a0939000822c552deace46f154
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314937
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
Use some meaningful macro names instead of just raw numbers when
selecting the correct USB phy port. Also we only need to do this
once, since it should be sticky through anything short of a
complete power down.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall; run it
No new functionality, just refactoring.
Change-Id: If6ea2b9d9a62bf6ce4adaed1c5aac1f66013ebeb
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314938
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
In fact this provides support for three FPGA images:
20151104_011218 - full crypto, no USB
20151104_041733 - tiny crypto, full USB
20151104_065845 - full crypto, full USB (only for hard-to-get boards)
We can tell these FPGA images apart at run-time by looking at
some SWDP registers:
register crypto usb full
GREG32(SWDP, BUILD_TIME) 0x2bd2 0xa305 0x10135
GREG32(SWDP, FPGA_CONFIG) 0x1 0x2 0x3
This CL includes a run-time check for the USB features so that
it's safe to build the firmware with CONFIG_USB and run it on a
non-USB FPGA image.
Here are the differences I could find in the top-level image
header files:
All three FPGA images define different (apparently arbitrary)
default values for the PMU_PWRDN_SCRATCHn registers, but other
than that, the usb and full images differ only in the BUILD_TIME
and FPGA_CONFIG register values.
I'm not sure why, but function uart_init() in file
chip/g/polling_uart.c writes to one of the PMU_PWRDN_SCRATCHn
registers, but nothing seems to read it again.
The crypto image defines these values which don't appear in the
other images:
#define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL 0x4f
#define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL 0x50
#define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL 0x51
#define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL 0x52
#define PINMUX_USB0_EXT_RX_DMI_SEL 0x53
#define PINMUX_USB0_EXT_RX_DPI_SEL 0x54
#define PINMUX_USB0_EXT_RX_RCV_SEL 0x55
#define PINMUX_USB0_EXT_SUSPENDB_SEL 0x56
#define PINMUX_USB0_EXT_TX_DMO_SEL 0x57
#define PINMUX_USB0_EXT_TX_DPO_SEL 0x58
#define PINMUX_USB0_EXT_TX_OEB_SEL 0x59
#define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_OFFSET 0x230
#define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_OFFSET 0x234
#define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_OFFSET 0x238
#define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_OFFSET 0x23c
#define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_RX_DMI_SEL_OFFSET 0x240
#define PINMUX_USB0_EXT_RX_DMI_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_RX_DPI_SEL_OFFSET 0x244
#define PINMUX_USB0_EXT_RX_DPI_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_RX_RCV_SEL_OFFSET 0x248
#define PINMUX_USB0_EXT_RX_RCV_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_SUSPENDB_SEL_OFFSET 0x24c
#define PINMUX_USB0_EXT_SUSPENDB_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_TX_DMO_SEL_OFFSET 0x250
#define PINMUX_USB0_EXT_TX_DMO_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_TX_DPO_SEL_OFFSET 0x254
#define PINMUX_USB0_EXT_TX_DPO_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_TX_OEB_SEL_OFFSET 0x258
#define PINMUX_USB0_EXT_TX_OEB_SEL_DEFAULT 0x0
The crypto image also differs in this:
#define PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x25c
instead of this:
#define PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x230
The rest of the differences between the crypto and usb versions
are in these values, which I don't think we care about. At least,
I can't find any place where they're used.
PINMUX_EXITEDGE0_DIOAn_OFFSET
PINMUX_EXITEDGE0_DIOBn_OFFSET
PINMUX_EXITEDGE0_DIOMn_OFFSET
PINMUX_EXITEDGE0_VIOn_OFFSET
PINMUX_EXITEDGE0_OFFSET
PINMUX_EXITEN0_DIOAn_OFFSET
PINMUX_EXITEN0_DIOBn_OFFSET
PINMUX_EXITEN0_DIOMn_OFFSET
PINMUX_EXITEN0_VIOn_OFFSET
PINMUX_EXITEN0_OFFSET
PINMUX_EXITINV0_DIOAn_OFFSET
PINMUX_EXITINV0_DIOBn_OFFSET
PINMUX_EXITINV0_DIOMn_OFFSET
PINMUX_EXITINV0_VIOn_OFFSET
PINMUX_EXITINV0_OFFSET
PINMUX_HOLD_OFFSET
PINMUX_SEL_COUNT
PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL
PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL
PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL_OFFSET
PINMUX_XO0_TESTBUSn_SEL
PINMUX_XO0_TESTBUSn_SEL_OFFSET
I used the header from the usb image to update chip/g/cr50_fpga_regdefs.h
BRANCH=none
BUG=chrome-os-partner:43791
CQ-DEPEND=CL:310978
TEST=make buildall
I also built a single Cr50 firmware and tried it on both the
crypto and usb FPGA images. Both worked as expected.
Change-Id: Ia8a064758f71f86771729437ae3e81226fd55789
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311211
Oops. I was losing one of the args when the USB debugging output
was enabled. And with a lot of messages I was also losing some
of the output.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall, manual test of Cr50 USB:
1. Plug into a USB jack on a Linux host.
2. In src/platform/ec/extra/usb_console, run
make
./usb_console -p 5014 -e 1
3. Type something, hit return
4. See whatever you typed come back with swapped case
5. ^D to quit
Change-Id: I284606aa91a76262644cfce60913a91ccc36ae60
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/310846
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The latest Cr50 FPGA release runs at 15MHz, but supports USB
operations. This CL includes changes to make that work.
Specifically:
* Enable the security features and select the correct PHY
* Adjust the turnaround time for the slower clock speed
* Handle the SET ADDRESS command specially for this SoC
* Remove all printfs from interrupt handlers (but add #ifdef code
to print debug messages later if desired).
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall, manual test of Cr50 USB:
1. Plug into a USB jack on a Linux host.
2. In src/platform/ec/extra/usb_console, run
make
./usb_console -p 5014 -e 1
3. Type something, hit return
4. See whatever you typed come back with swapped case
5. ^D to quit
Change-Id: I848e96d19df056a453d30d4b5537481046fe852d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308062
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Add a description for the USB HID interface, neaten a bit of
console output. No new functionality.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: Ie85a0192bc4ab9fa87afb4be41d496545a3b548a
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/283051
Reviewed-by: Randall Spangler <rspangler@chromium.org>
