Commit Graph

5 Commits

Author SHA1 Message Date
Anton Staaf
fba4f335a9 cortex-m0: Constrain target register in atomic read
One more register constaint needed to be added to the cortex-m0 atomic
inline assembly.  Vincent fixed all the others.  The requirement for
ARMv6-m includes that the target load register be one of the low
registers as well.

Signed-off-by: Anton Staaf <robotboy@chromium.org>

BRANCH=None
BUG=None
TEST=make buildall -j

Change-Id: Ie44e824cafcc9b862ade664e3016cc34886cdf6e
Reviewed-on: https://chromium-review.googlesource.com/292435
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
2015-08-11 19:52:40 +00:00
Anton Staaf
4626177c3b Atomic: Mark the modified uint32_t volatile
The atomic_* functions are often used in contexts where the data they
will operate on are volatile (due to being shared between tasks or a
task and an interrupt handler).  Adding volatile here makes using the
atomic_* functions a little easier in those cases and removes a cast
from the call sites (which could be obscuring a bug, if for instance
the variable was modified to be a uint16_t).

Signed-off-by: Anton Staaf <robotboy@chromium.org>

BRANCH=None
BUG=None
TEST=make buildall -j

Change-Id: I71356eb3cf2c0506df38532eee767c7d78f9240e
Reviewed-on: https://chromium-review.googlesource.com/287516
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
2015-07-27 19:30:44 +00:00
Vincent Palatin
2650ff3d70 Add option to enable GCC LTO
Add CONFIG_LTO to use GCC Link-Time Optimizations to try to reduce the
flash footprint of the firmware.

Add additional protection to some functions/data to avoid removal by the
linker when their usage is not obvious.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=make buildall (with and without LTO enable on all boards)

Change-Id: I586b8c1eda4592b416c85383b65153c1d5ab0059
Reviewed-on: https://chromium-review.googlesource.com/271291
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
2015-05-19 02:46:27 +00:00
Vincent Palatin
ba98b92bbb cortex-m0: add more constraints on atomic implementation
In ARMv6-m instruction set, the load/store address register can only be
a "low" register : r0..r7.
Update the inline assembly constraints to match the hardware.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=make buildall

Change-Id: I9872aeb437b2bb6401bed8076348e26d434320dd
Reviewed-on: https://chromium-review.googlesource.com/224582
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
2014-10-21 22:44:53 +00:00
Vincent Palatin
0f73a129b4 Add Cortex-M0 core support
The Cortex-M0 core is based on ARMv6-M instruction set rather than
ARMv7-M as Cortex-M3 and M4.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=run console on STM32F072,
and pass all available unit-tests on target.

Change-Id: I9bdf6637132ba4a3e739d388580a72b4c84e930e
Reviewed-on: https://chromium-review.googlesource.com/188982
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
2014-03-11 05:52:41 +00:00