Implement TMP006 object temperature calculation. Also add a console
command to calculate temperature with manually entered data.
BUG=chrome-os-partner:7801
TEST=In console, "tempremote 29715 -105000 6390" gives 285.00K.
Change-Id: I0f9193fb970fdc36566399e7083e73ab58965a85
- Add #ifdef CONFIG_TEMP_SENSOR before #include'ing temp_sensor.h
which actually requires temp_sensor_id to be defined.
Revert the forward declare used earlier since it is not the
correct solution in this case.
- Add #ifdef CONFIG_CHARGER before calling charger_init()
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=None
TEST=compiled on both BDS and Discovery
Change-Id: I60b7e4ba91eb958b3ad724cc9ffa9a12fe9c3a71
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7906
TEST=from ec console, 'x86power s0' should power the system on reliably.
Change-Id: Idebfc8b4e86587b540934d245649f912ccb4aa95
F1-F7: swap scancode of set 1 and set 2
F8-F10: change from (F9, F10, F11)
arrow keys: swap scancode of set 1 and set 2
Search key: change from CapsLock key
BUG=none
TEST=tested on bds.
Change-Id: Ifb8e715a2cd5f8ea174f7c38647c5ce550382615
Refactor board/chip-specific code into corresponding directories.
Add support of the four I2C temp sensor in Link.
Use table lookup to handle different types of temperature sensors.
BUG=chrome-os-partner:7527
TEST=Correctly read EC internal temperature on bds.
Compile for link succeeded.
Change-Id: I694cfa54e1545798d877fafdf18c5585ab5f03e2
The GPIO console commands are common to all platform, let's push them in
the common code.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=link && make BOARD=bds && make BOARD=discovery
on BDS console, try gpioget command.
Change-Id: I26e6d26b8d661e78b80d5d5f665e81f4daef0c11
When the flash base address is not zero (e.g. STM32L chip), the current
image index is wrongly computed.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=check it compiles for all boards, run on Discovery board and see
proper value.
Change-Id: I06f5508cdffce6d754bd93e870d64087d299c9c7
The problem comes from the different assumption of interrupt mode in EC and
the PCH. The PCH assumes IRQ1 is edge-triggered and triggered at a rising edge.
However, the auto-IRQ functino of EC is level-triggered and uses low-active to
assert an IRQ. This makes the deadlock so that the kernel never gets an
interrupt until a byte is manually pulled from host.
So, the solution is manually firing an IRQ_1 to host after EC puts a byte to
port 0x60. Note that the auto IRQ needs to be disabled in order to avoid
the interference with manual IRQ generation.
This CL also moves chip specific code to lm4/lpc.c and handle some minor
keyboard commands.
BUG=none
TEST=on hacked baord.
Change-Id: Ib57f5a4d749cb019e4c3c00da110054c4f335c7b
Handle left and right arrow key to move cursor around.
Other escape sequences are still ignored.
BUG=chrome-os-partner:7865
TEST=type some text and use left and right arrow key. Cursor should
move.
type 'hellp', left key, and backspace. Should show 'help' and hitting
enter prints help.
type 'hexp', left key, backspace, 'l'. Should show 'help and hitting
enter prints help.
Change-Id: If9ac4504c56f023f824175de2daf565ce72d4560
I keep hitting the darn arrow keys. Until we can do something more
elegant like a real command history, this will at least keep me from
corrupting the display and input buffer.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=type 'help' and some arrow keys, then enter. Should print help, not an error.
Change-Id: Idb552e9c22876fc2dc1f349f0038e94048f00aa7
To assist in x86 chipset bringup, there are 4 GPIOs we weren't
printing state transitions for.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=reboot; should see state transitions in the high nibble (mask 0xF000), for example:
[x86 power state 1 = S5, in 0x2001]
[x86 power state 1 = S5, in 0x3001]
[x86 power state 1 = S5, in 0x7001]
Change-Id: I0527e4698425d845e8b08589e89592f95d8bee41
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7528
TEST=x86power s0; should turn on all power rails (check via gpioget)
Change-Id: I284ac2104e02748ed69408873fbcebb9d54cdcff
Preparatory work to introduce a second SoC : 3rd series 2/2
All the RO/A/B firmware copy code could be generic to all our platforms.
The console commands are a 'standard' API.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on BDS EC console, check the reset cause with the 'sysinfo' command.
Change-Id: Ieeb84571085d88b5747a09da4c33d3852bb0da96
Preparatory work to introduce a second SoC : 3rd series 1/2
Most of the code is handling the buffering and the printf, thus put it
in an hardware independant location and only implement the UART
dependant portions in the chip driver.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run on BDS and stress the console.
Change-Id: I9376f2fa1dad341eac808e1756dbeff32900bd51
Preparatory work to introduce a second SoC : 2nd series 3/4
Some modules won't be used on other designs, make them optional.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run the EC firmware on BDS and check that the commands from the
optional features are still available and working.
Change-Id: I979864ed94dc4da90c1010bd2e4589d84bc2d046
Preparatory work to introduce a second SoC : 2nd series 2/4
Avoid introducing platform specific dependencies in common files where
they are not necessary.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=build for BDS and Link
Change-Id: If2ccd022e4956425222b55a5a48ca7522857e7f0
You can now enable/disable tasks more easily.
To conditionally compile a C file depending on the task FOO activation,
just write something like that in the build.mk file :
common-$(CONFIG_TASK_FOO)+=foo_source.o
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make all BOARD=link && make qemu-tests
Change-Id: I760fb248e1599d13190ccd937a68ef47da17b510
Instead of using a runtime callback to register the console commands,
put them in a special linker section. So we can do a macro to "register"
them during the build.
It saves 684 bytes and a few microseconds at startup.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run a few commands from the BDS command line.
Change-Id: Id33ea210b9035bf76ed720373c74c5dd24ccd1b1
This works around a chip errata where the internal oscillator on early
EC parts (as used on proto0) is untrimmed.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7693
TEST=if it runs, it works
Change-Id: Ie82a524543f4cf25efd0de7998dbdae103bd126b
Implement TPS2543 USB charging control.
It contains routine for setting each USB port as dedicated charging port
or standard downstream port. To allow us controlling the current
distributed to each port, we can select whether to allow 500mA or 1500mA
for each port.
BUG=chrome-os-partner:7476
TEST=Added USB port definition for BDS and tested GPIO output voltage
level is correct for all modes.
Change-Id: I19bc4b30d333aa802f868ebfc3a398b30e99ba0f
For bringup, this powers on the x86 unconditionally.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7528
TEST=none
Change-Id: Ib23e56d38ab42f8d8a4dbd1ba9dce12f0c3eeec9
This just ensures the JTAG pins are reset to JTAG function on warm reboot.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7448
TEST=none
Change-Id: I0cccdbe7a68c228db7f354898ed30598e9fabff0
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7499
TEST=press and release power button; should see debug messages
Change-Id: I8909ae4643afc98753edb690771618ad43135e3e
Removed a duplicated line in common/build.mk which causes compilation
fail.
BUG=chrome-os-partner:7313
TEST=Compilation passed
Change-Id: Ia7bb73b96e4feae27e5b6e519feb3ea1a672913a
Add LPC host command to get and set fan speed.
BUG=chrome-os-partner:7313
TEST=Connect a fan and manually test fan actual speed matches target
speed.
Change-Id: I4b6a711a1b8cca0dbd1c1936fe4f0f15240d3453
Add a LPC host command to read temperature sensor value with given
sensor id.
Add ectool command to read temperature sensor value through LPC.
BUG=chrome-os-partner:7329
TEST=Manual check the reading received is the same as value printed by
console command.
Change-Id: Id3386774435be6c3ae010a143f4fa894568efdb8
The LPC is not stable enough to test. Kodus Rong. He creates this idea
to checksum the partial content of flash for read/write/erase. This can
improve the robustness of flashrom.
BUG=none
TEST=Tested with flashrom.
Change-Id: I2a2f7b698a94674c03cbd8e3f15caf34f8986399
This CL add host command to enable, get/set flash write protect range.
BUG=None
TEST=Use flashrom utility to set write protect range, enable write
protect and get status.
Change-Id: I345f1eb65944d8cf8028e6fdb7e43c40cc742a6d
Signed-off-by: Rong Chang <rongchang@chromium.org>
