Added code to get the VBUS level by reading the charger registers.
BUG=chrome-os-partner:55117
BRANCH=none
TEST=Manually tested on Amenia, VBUS_VAL (5Ch) & VCC_VAL (5Eh)
registers are updated with the correct VBUS value on the
respective ports.
Change-Id: I3b019b2d87e4c347f12596df387a2a659092ae25
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/359416
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
When cr50 is not trying to do ccd, we dont need to monitor the devices.
Disable device state detection interrupts and the AP and EC UARTs.
BUG=none
BRANCH=none
TEST=gru and kevin monitor devices correctly when ccd is enabled, and
dont monitor anything when it is disabled.
Change-Id: Ic3f5974320486ff6dd0147c490a1c294cc2f6a76
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356770
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The code reporting the RW version is in fact using a fixed location in
flash memory. This is fine for a single RW image (i.e. the vast
majority of the EC boards), but is wrong for CR50 which can run one of
two RW images.
The fix is to account for this by providing the currently running
image type to the function retrieving the image version.
Note that RW and RW_B versions end up at different offsets into the
image, it is impossible to retrieve the version of the not currently
running RW by just changing the offset into the flash memory.
BRANCH=none
BUG=chrome-os-partner:55145
TEST=as follows:
- build, update and start a cr50
- check the vers. command output, observe that it is running from
RW and reports the correct RW version string:
> vers
Chip: g cr50 B1 0_0
Board: 0
RO:
RW: cr50_v1.1.4856-df14f6a
Build: cr50_v1.1.4856-df14f6a 2016-07-11 11:52:44 vbendeb@eskimo.mtv.corp.google.com
>
- build the image again, update and restart the cr50
- check the vers. command output, observe that it is running from
RW_B and reports the correct RW version string:
> vers
Chip: g cr50 B1 0_0
Board: 0
RO:
RW_B: cr50_v1.1.4856-df14f6a
Build: cr50_v1.1.4856-df14f6a 2016-07-11 11:52:44 vbendeb@eskimo.mtv.corp.google.com
>
- erase the RW space base
flasherase 0x4000 0x20000
- run the vers command again. It was failing before this fix, now
it still shows the proper RW_B version.
Change-Id: Iab8bc0e61b50dd65a9e18a0369b18bdd9cc05421
Reviewed-on: https://chromium-review.googlesource.com/359580
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The AP no longer uses PHY0 to to interact with Cr50. Cr50 only uses PHY1
so dont switch the PHY when disabling CCD just release the usb.
BUG=none
BRANCH=none
TEST=After running 'ccd disable' the command 'usb' still returns PHY B,
but 'lsusb | grep 5014' on the host doesn't show any devices. When CCD
is enabled 'lsusb | grep 5014' shows a device on the host.
Change-Id: Icec0acc7a0d00f7eb56c6feef3ff4cf5a3f99735
Reviewed-on: https://chromium-review.googlesource.com/359931
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
cts.tasklist contains tasks run only for CTS. These tasks are added to the
tasks registered in ec.tasklist with higher priority. This design allows
board directories to be free from CTS stuff.
cts.tasklist can be placed in each suite directory (cts/suite/cts.tasklist).
If a suite does not define its own cts.tasklist, the common list is used
(i.e. cts/cts.tasklist).
BUG=chromium:624520
BRANCH=none
TEST=Ran the followings:
make buildall
make CTS_MODULE=gpio BOARD=nucleo-f072rb
make CTS_MODULE=gpio BOARD=stm32l476g-eval
Change-Id: Ibb242297ee10a397a8fcb6ff73d8cbc560daa885
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359445
Reviewed-by: Chris Chen <twothreecc@google.com>
If wait_us < 0, comparison against motion_min_interval actually fails,
and this negative wait_us causes task_wait_event() never returns if we
are not using any motion task event except the timer. The motion task
will then stop running and sensor data stay unchanged.
BRANCH=none
BUG=chrome-os-partner:54092
TEST=hardcode wait_us to a negative value before motion_min_interval check,
and see motion task is still running by EC console cmd timerinfo
Change-Id: Ic1e7ffeeb9d2ec1f5c5beb4387294014298123af
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/358332
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
If the EC has CONFIG_HOSTCMD_RTC set to 'y', then export this via the
features host command. The kernel can then use this feature to expose
an RTC device under /dev/rtc*.
Signed-off-by: Stephen Barber <smbarber@chromium.org>
BRANCH=none
BUG=chrome-os-partner:54639
TEST=`ectool inventory` shows RTC on kevin
Change-Id: I644c8e61c4d9f691cc6ca94ef60bee4384c21660
Reviewed-on: https://chromium-review.googlesource.com/359414
Commit-Ready: Stephen Barber <smbarber@chromium.org>
Tested-by: Stephen Barber <smbarber@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
elm EC console output is very spammy, as EC_CMD_MOTION_SENSE_CMD
is called every 100ms, so we want to set "hcdebug" to "off" as
the default (which still includes errors, but no "normal"
commands).
BRANCH=none
BUG=chrome-os-partner:55001
TEST=make buildall -j
TEST=Flash elm EC, see that output is fairly quiet.
Change-Id: I70d91c291d934b4f032e5c57f3c333e2c10b93bc
Reviewed-on: https://chromium-review.googlesource.com/359112
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
While the proper manufacturing initialization is in the works, we need
to be able to initialized the device, but do not want to run
manufacturing process on every reboot.
Let's store the state in the lowest location of the NVRAM, this patch
will be reverted when the proper initialization procedure is in place.
BRANCH=none
BUG=chrome-os-partner:50115
TEST=used the device in Kevin. Observed that factory initialization
sequence was invoked only on the first boot, the following boots
had no problems reading rollback counters.
Change-Id: I812cbad4d91db47de76ecfa5a14c56ae9c0efdab
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358680
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Currently, it is assumed the host will sooner or later retrieve the
events from the sensor ring: It is only used by Android and the sensor
HAL is enabling the ring buffer at boot.
But if nobody processes the ring, and the ring is almost full, the EC will
generate interrupt for every new events.
This can happen with ARC, where events generated for ChromeOS
will be in the ring but nobody will process them until Android is
started.
Add a command to allow sending ring MKBP events. It will be used when
the IIO ring buffer is enabled / disabled.
It also can be used for preventing raising interrupt when the device is
about to go to sleep.
BRANCH=ryu,cyan
BUG=b:25425420,b:27849483
TEST=Check with fiforead that no events are queued when IIO ring
buffer is disabled.
Check with ectool and androsensor that interrupt generation stops.
Change-Id: Ibc85eed2e0eae3a9ec07d191e692118bc2fd0dab
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356689
For certain board configurations, KSI2 will be stuck asserted for all
scan columns if the power button is held. We must be aware of this case
in order to correctly handle recovery mode key combinations.
BUG=chrome-os-partner:54602
BRANCH=None
TEST=Manual on gru. Do three-key salute, verify EC detects recovery mode.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I03d76e1121107484f79520745858388f6cae096c
Reviewed-on: https://chromium-review.googlesource.com/357590
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When verifying RW using rwsig, we need to be able to erase the RW
signature to remain in RO. This change excludes the RW signature from
the area protected by system_unsafe_to_overwrite, so flash write can be
used to overwrite the RW signature while still in the RW system image.
BUG=none
BRANCH=lucid
TEST="ectool flashwrite 0x1ff00 corrupt_sig" runs successfully, and on
reboot the EC firmware verification fails.
Change-Id: I7e234664ae564eef30a8b021ea0539b6c0ae898e
Reviewed-on: https://chromium-review.googlesource.com/356810
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The CR50 RO version is identified not just by the git hash, but also
by the fuse settings and keys used for signing. The first four bytes
of the entire RO image's hash are saved in the image header. Adding
these four bytes to the version string reported to the host allows to
uniquely identify both RO and RW firmware versions.
BRANCH=none
BUG=none
TEST=verified that the appropriate string is showing up:
localhost ~ # grep cr50 /sys/firmware/log
Firmware version: RO: 97594095 RW: cr50_v1.1.4803-dcac93a-dirty
localhost ~ #
Change-Id: I30a21fad15d99523b1edfa1baa32d80b44e7d0df
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356735
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Not everything with a temperature sensor uses thermal throttling. This
change modifies the conditional build to enable building temp sensor
source without thermal throttling.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I8c0753f12899e9f203c04477ae520bcda40d5fd8
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356484
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
For designs where the host SOC is responsible for setting the USB-C SS
mux, the EC must track the desired mux state and inform the host when
the desired state changes. Then, the host must ask the EC for the new
desired state and set the mux accordingly.
BUG=chrome-os-partner:52639
BRANCH=None
TEST=Manual on gru with subsequent commit.
Attach USB dongle in port 1 and DP dongle in port 0, then verify `ectool
usbpdmuxinfo` output:
Port 0: DP
Port 1: USB
Flip DP dongle and verify output changes:
Port 0: DP INV
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6a99ce93a76c3197f9195cfaa25c5217d09aeb75
Reviewed-on: https://chromium-review.googlesource.com/355281
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Created a new TPM register define at the beginning of the
vendor defined configuration register space 0xF90 - 0xFFF.
Note that this same space is defined for each locality.
In order to retrieve the FW version string, the TPM register
at offset 0xF90 needs to be written. This will initialize
a the pointer index to 0. The same register is then
read by the AP and each read will return up to 4 bytes of the
FW version string. Once Cr50 detects the string termination
character, it stops incrementing the index so that 0s continue
to be returned for each subsequent read.
In addition there is a max value of reads for the case when the
version string is corrupt and doesn't have a '\0' character.
BRANCH=none
BUG=chrome-os-partner:54723
TEST=Manual
Added a routine in /coreboot/src/drivers/spi/tpm.c tpm_init()
that does the write/read sequence described above. This test
routine produced the folloiwng AP console output:
Reading TPM EC Version!!
scollyer@ code goes here
Read 1: cr50 0x30
Read 2: _v1. 0x2e
Read 3: 1.47 0x37
Read 4: 81-1 0x31
Read 5: 3619 0x39
Read 6: 95-d 0x64
Read 7: irty 0x79
Read 7: 0x0
Cr50 FW Version: cr50_v1.1.4781-1361995-dirty
Read Count = 29
Initialized TPM device CR50 revision 0
Change-Id: I5d68a037f7a508e3109c35e841dbcb3a893ce22f
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355701
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The "PC Client Protection Profile for TPM 2.0" document defines SPI
bus addresses for different localities. That definition is not honored
in the cr50 implementation, this patch fixes it: locality zero
register file is based off 0xd40000.
BRANCH=none
BUG=chrome-os-partner:54720
TEST=verified that upstream Linux driver is happy now
Change-Id: Ibc01035a5dcc823a0ec82374d758de08a70083b6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355610
Tested-by: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Added mutex lock for nvmem write/move operations. In the
current implementation, there is no single entry point
for the platform specific NvMem calls. The mutex lock is
coupled with a task number so that the same task can attempt
to grab the lock without stalling itself.
In addition to the mutex lock, changed where the cache.base_ptr
variable is updated. Previously, this was done prior to the
partition being copied from flash to the shared memory area.
Now, the variable is only updated after the copy so that read
operations will always read from the correctly from either
flash or from cache memory if a write operation has been
started.
BRANCH=none
BUG=chrome-os-partner:52520
TEST=Manual
make runtests TEST_LIST_HOST=nvmem and verify that all tests pass.
Tested with tcg_test utility to test reads/writes using the
command "build/test-tpm2/install/bin/compliance --ntpm
localhost:9883 --select CPCTPM_TC2_3_33_07_01".
Change-Id: Ib6f278ad889424f4df85e4a328da1f45c8d00730
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353026
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Add a host event to support MKPB:
When sent, the ACPI code will send a notification to the kernel
cros-ec-lpcs driver that will issue EC_CMD_GET_NEXT_EVENT.
We can allow code (sensor stack for instance) that uses MKBP to work
on ACPI based architecture.
Obviously, host event over MKPB is not supported.
BRANCH=none
BUG=b:27849483
TEST=Check we get sensor events on Cyan through the sensor ring.
(cyan branch)
Change-Id: Iadc9c852b410cf69ef15bcbbb1b086c36687c687
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353634
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When we jump from RO to RW, tcpc_vbus declared in tcpci.c
is initialized to 0. So even if we had VBUS present before,
PD_FLAGS_VBUS_NEVER_LOW is not set and soft reset cannot be used
later when source cap is timeout. This causes power loss and reboot
when we boot up system without battery.
Set PD_FLAGS_VBUS_NEVER_LOW after tcpm_init() so we can refresh
tcpc_vbus from TCPC first.
BUG=chrome-os-partner:53496
BRANCH=none
TEST=test on elm.
Remove battery and boot up successfully only with AC.
Use "sysjump rw" command and ec won't reboot by pd hard reset.
Change-Id: Id4737f076a9572cb540310f9fdce062198257967
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/352833
Reviewed-by: Rong Chang <rongchang@chromium.org>
Previously our charger ISR called a deferred task which woke our charger
task. We can skip the deferred task and just wake our charger task
directly.
The other meaningful change here is to assume that we're using the
charger for VBUS detection / BC1.2 if we have a usb_chg task, which
holds true for all of our current boards with this charger.
BUG=None
TEST=Manual on kevin with subsequent commit. Verify charger connect /
disconnect detection works properly on both ports, with zinger, donette
and generic DCP charger.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iad4f3ea90947b50859c549b591675e325717209f
Reviewed-on: https://chromium-review.googlesource.com/352822
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If i2c communication with the TCPC is failing after 300ms+ then it's
likely going to fail forever, so return an error to allow the PD task to
continue initialization.
BUG=chrome-os-partner:53815
BRANCH=None
TEST=Manual on reef. Disconnect TCPC, attach charger to other port, and
verify charge manager correctly sets current limit based on detection.
Change-Id: I2c12320971a77504292f75393791e609e34897b4
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/352501
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
There is only one charger IC and one interrupt PIN for both the ports
and also from the ISR it's not possible to decode from which port the
interrupt is triggered hence a deferred function is used to trigger
the wake event for the ports. As there is no additional benefit of
having an extra task, added code to use only one USB charger task for
both the ports.
BUG=chrome-os-partner:54272
BRANCH=none
TEST=Manually tested on Amenia. BC1.2 detection is success
and the battery can charge on both the ports (VBUS/VCC).
Change-Id: I2745a5a179662aaeef8d48c8c1763919e8853fd0
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/351752
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
If the lid is initially closed, keyboard scan should be disabled.
BUG=chrome-os-partner:53566
BRANCH=none
TEST=Check ESC+Refresh+PwrBtn is detected.
Check keyscan is enabled if lid is open.
Check keyscan is disabled if lid is closed.
Check power button is functional if lid is opened.
Check power button is masked if lid is closed.
Change-Id: I2354a657d8bf0c13207517cc789547a68befd240
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/351534
Reviewed-by: Shawn N <shawnn@chromium.org>
In TCPCI specifiction R1.0 4.7.2, the last step of transmitting
hard reset message is enable PD message passing by writing to
RECEIVE_MESSAGE register.
BRANCH=none
BUG=chrome-os-partner:52815
TEST=manual
build and load on reference board with anx7688 port controller.
connect zinger to port 0, and use ec uart console to send hard
reset message:
pd 0 hard
check PD communication
Signed-off-by: Rong Chang <rongchang@chromium.org>
Change-Id: I52968b603f0227d7d9a112b0216cd5fd6362a0b2
Reviewed-on: https://chromium-review.googlesource.com/348142
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Section 5.3.1 TPM Register Space Decode of TCG PC Client
Platform TPM Profile (PTP) Specification Rev 00.43 allows
partial access to registers: "Software may access only part
of a register, e.g. read or write one byte of a 4 byte register."
BUG=chrome-os-partner:54286
BRANCH=none
TEST=tpm driver successfully sets TPM_STS_COMMAND_READY
(see more details in BUG)
Change-Id: I92995f04c6f6221ab7e00d086c4067e447557476
Signed-off-by: Andrey Pronin <apronin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351701
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
If our battery isn't able to provide enough power to the EC on boot, we
should not cut off our input power, regardless of dual role
determination or other charging policy.
BUG=chrome-os-partner:54058
BRANCH=None
TEST=Manual on gru. Drain battery completely, attach USB-C charger,
verify that "Battery critical, don't disable charging" is seen on the
console and the EC doesn't brown out.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I981f9dbf3d84390550bb696e561f5fa51ffc573a
Reviewed-on: https://chromium-review.googlesource.com/351224
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Added support to enable the BD99955 charger interrupt to detect
the VBUS activity. With this approach GPIO USB_Cx_VBUS_DET_N pin
can be removed.
BUG=chrome-os-partner:53688
BRANCH=none
TEST=Manually tested on Amenia. Type-C, DCP & SDP chargers can
negotiate to desired current & voltage. Battery can charge.
USB3.0 & USB2.0 sync devices are detected by the Kernel.
Change-Id: I5470092c5cd43026aafc1a638ba446d0037c71e7
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/343650
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commands makes it possible to control the PD chip (or
the interaction between EC and PD), from the AP.
- PD_SUSPEND: Suspends the PD chip: EC needs to stop talking
to PD chip. Useful at beginning of PD FW update.
- PD_RESUME: Resumes the PD chip: EC can start talking to PD
chip again. Useful at end of PD FW update.
- PD_RESET: Resets the PD chip (called at the end of the update).
- PD_CONTROL_DISABLE: Prevents further calls to this command
(for security reason, we do not want the AP to be able to
call the other subcommands after the update has been performed).
BRANCH=none
BUG=chrome-os-partner:52433
TEST=ectool pdcontrol {suspend,resume,reset,disable}
Change-Id: I7a955dd27b65086c21d195a6504aa7392eb0406d
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342584
Reviewed-by: Randall Spangler <rspangler@google.com>
Also, make sure that pd_set_suspend can work asynchronously,
but looping until the status is read back as SUSPENDED.
BRANCH=none
BUG=chrome-os-partner:52433
TEST=On elm:
ectool pdcontrol reset
sleep 0.1
ectool pdcontrol suspend
i2cset -f -y 2 0x28 0x05 0x10
=> No I2C communication with ANX7688
Change-Id: Iad7b500f1af554e2bc4f64f90ee0a492f903749a
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347730
This change adds a ccd console command to control the usb endpoints.
The uart console command is moved into this command so 'ccd uart
[enable|disable]' controls the AP and EC TX signals instead of the
'uart' console command. CCD can be enabled using 'ccd enable'. This
switches the PHY used by the USB controller to be the external PHY.
Changing the PHY exposes the cr50, AP, and EC consoles as well as the
upgrading mechanisms for the AP, EC and cr50. The AP and EC consoles
will be read only until 'ccd uart enable' is called. Cr50 can be updated
using the usb upgrade endpoint. The EC and AP can be updated using the
USB SPI endpoint.
When CCD is disabled the usb controller will switch to using the AP PHY.
None of the endpoints will be visible to the host.
The USB SPI endpoint can be used to flash the EC or AP using
'flashrom -p raiden_debug_spi:target=[AP|EC]'. If CCD is not enabled
running flashrom using the raiden_debug_spi programmer will fail. Cr50
will not forward the commands to the external AP or EC ROM, so flashrom
will not be able to find the chip.
The UART TX signals are now controlled by the 'ccd uart' console
command instead of the 'uart' console command. The UART TX is enabled
separately from CCD, because we want to be able to enable CCD while
servo is connected, and having the cr50 UART TX pins wired directly to
the Servo TX lines could damage both devices. The AP and EC consoles
are be read only until 'ccd uart enable' is called. 'ccd uart disable'
disconnects the AP and EC TX pins from the UART peripheral.
When RDD becomes reliable on cr50, ccd_set_mode will select the PHY
being used by the g chip USB controller.
BUG=chrome-os-partner:49960,chrome-os-partner:52281
BRANCH=none
TEST=manual
TEST SERVO
power cycle the DUT
connect servo and check that the AP and EC consoles still work
check that both the AP and EC can be flashed using servo.
TEST SUZY Q
Attach Suzy Q
Connect to the all three consoles. Check that the cr50 console
is in read-write mode and the EC and AP consoles are read only.
Attach Servo.
Verify all of the servo functionality described above still
works with suzy q attached and ccd enabled.
Disconnect Servo.
run 'ccd uart enable' on the cr50 console and check both the AP
and EC consoles can be written to.
Check that the AP and EC can be programmed using the
raiden_debug_spi programmer.
Change-Id: I96db2a72fc95086871c9e4c778c19ebd01efb851
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342563
add a new config flag to support active low power control signal
BUG=chrome-os-partner:53665
BRANCH=none
TEST=Use multimeter to check for voltage present on the WiFi slot.
Use gpioget to check GPIO state in S0 (on) and S5 (off).
Change-Id: Ibeca88d16f39eadd7f29589cd3cd15aeef0dd524
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/347085
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Kevin uses inverted polarity (low = enable 5V output), so add a new CONFIG
to support this.
BUG=chrome-os-partner:53777
BRANCH=None
TEST=Manual on Kevin. Enable USB charger tasks, verify that VBUS is
properly detected on no-battery case.
Change-Id: Ifb3e5fa9db1973d9826435712711f0cb0fd1d3a5
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349260
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Previously CONFIG_USB_PD_TCPM_VBUS had two uses which were independent:
- When operating as a TCPC, it indicated that the VBUS level should be
tracked (through GPIO inputs) and sent to the external TCPM when
appropriate.
- When operating as a TCPM, it indicated that the VBUS level should be
obtained by querying the TCPC.
These two independent uses have been split into
CONFIG_USB_PD_TCPC_TRACK_VBUS and CONFIG_USB_PD_VBUS_DETECT_TCPC, which
sould be more clear.
In addition, CONFIG_USB_PD_VBUS_DETECT_* CONFIGs have been added for
other means of VBUS detection.
BUG=chromium:616580
BRANCH=None
TEST=Verify kevin continues to boot + charge.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I936821481d6577e17e3e9c61ff97c037574d6923
Reviewed-on: https://chromium-review.googlesource.com/348950
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
It is important to be able to wipe out the non-volatile memory for
various reasons. This patch adds this ability for both when NV memory
is kept in SRAM and in flash.
Also a minor clean up to eliminate some code duplication and to have
normal flow messages printed out with time stamps.
BRANCH=none
BUG=chrome-os-partner:44745
TEST=just makeall at this time.
Change-Id: I59c1909669aeaa9e8ffb3d8ef81b02fa0facb6ab
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348291
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Initialize the charge suppliers after change manager is initialized,
otherwise charge supplier current & voltage values will be overwritten
to -1 by the charge manager ini function.
BUG=chrome-os-partner:53788
BRANCH=None
TEST=Observed there are no "CL: p(port) s(supplier) i-1 v-1" prints
on the EC console.
Change-Id: Id0212c502d5833c016ac79ee15d21304d6d7ceb2
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/347896
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
There are a couple of issues that cr50 has when it cannot know the state
of servo, the EC, and the AP. This change adds support so we can detect
when the AP or EC has been powered on and when servo has been connected.
It uses the UART RX signals to monitor the power state of the AP and EC.
The TX signals are used to monitor the state of servo.
BUG=chrome-os-partner:52056,chrome-os-partner:52322
BRANCH=none
TEST=verify device states are correct when the AP and EC are powered on
or off and when Servo is attached or detached
Change-Id: Id0a2281b65cb367ecc8d0ca2f9a576672318a5fb
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344019
Used #define CONFIG_FLASH_NVMEM to have functions in
/board/tpm2/NVMem.c utlitize on chip Nvmem functions.
On chip NV Memory availability is tied to an internal nvmem
error state which itself only depends on finding at least one
valid partition.
Added nvmem_is_different and nvmem_move functions which were
needed to complete the tpm2 platform interface. In addition,
added unit tests to support these two new functions.
BUG=chrome-os-partner:44745
BRANCH=none
TEST=manual
make runtests TEST_LIST_HOST=nvmem and verify that all tests pass.
Tested with tcg_test utility to test reads/writes using the
command "build/test-tpm2/install/bin/compliance --ntpm
localhost:9883 --select CPCTPM_TC2_3_33_07_01".
Change-Id: I475fdd1331e28ede00f9b674c7bee1536fa9ea48
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346236
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Full implementation of NvMem read, write, and commit functions.
Includes partition definitions, shared memory allocation, and
initialization function.
Includes a set of unit tests located in ec/test/nvmem.c which
verify functionality.
This module is required by Cr50, however this CL does not
include any Cr50 specific code.
BUG=chrome-os-partner:44745
BRANCH=none
TEST=manual
make runtests TEST_LIST_HOST=nvmem and verify that all tests pass
Change-Id: I515b094f2179dbcb75dd11ab5b14434caad37edd
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/345632
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This change provides a console command for setting,
and loading a usb serial number from flash. This
feature adds CONFIG_USB_SERIALNO, and currently only
has a useful implementation when PSTATE is present.
BUG=chromium:571477
TEST=serialno set abcdef; serialno load; reboot
BRANCH=none
Change-Id: I3b24cfa2d52d54118bc3fd54b276e3d95412d245
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/337359
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The console adc command prints adc values in the
order they appear in hardware, however they are lableled
in the order they are enumerated in board.h, which is not
necessarily the same.
This prints the correct name and value pairs, and removes
the adc_read_all_channels function which is not otherwise
used.
BUG=chromium:571476
BRANCH=None
TEST="adc" command associates correct values with names now.
Change-Id: I688641953d20082224b4120eaefe0d634ad4c74c
Signed-off-by: Nick Sanders <nsanders@google.com>
Reviewed-on: https://chromium-review.googlesource.com/340892
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This allows the AP to protect a I2C passthru bus. A board-specific
function then defines what I2C commands are allowed, so that we
can white/black list some addresses (e.g. I2C address allowing
PD chip FW updating).
BRANCH=none
BUG=chrome-os-partner:52431
TEST=Book elm-rev1
Change-Id: Ib106924418b16388ea8ea53c7b6bda6ef92e1d09
Signed-off-by: Nicolas Boichat <drinkcat@google.com>
Reviewed-on: https://chromium-review.googlesource.com/345761
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@google.com>
The host command(ectool) to set led colors will read the brightness
range and then set as requested. If brightness range is 0, then it will just
return INVALID_PARAM.
BUG=chrome-os-partner:35416
TEST=build and run on veyron
ectool led battery green
ectool led battery red
ectool led battery red=1 green=1 #this gives amber
ectool led battery off
ectool led power white
ectool led power off
ectool led battery auto
ectool led power auto
BRANCH=veyron
Change-Id: I65a73275741ada5c01e041ae2c11efe3aa2d8c38
(cherry picked from commit ba88b6d6b35959d7ff33cdf075e494406a2f4b5f)
Reviewed-on: https://chromium-review.googlesource.com/345693
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
