This uses the last bank of flash to hold persistent settings, and
looks at the write protect GPIO to decide whether to protect the chip
at boot (chrome-os-partner:7453).
For ease of debugging, I've temporarily hacked this so flash uses the
RECOVERYn signal (dut-control goog_rec_mode:on) to enable WP instead
of the write protect signal; this works around chrome-os-partner:8580.
Also note that if you write protect any blocks even temporarily,
you'll need to do a power-on reset to clear them before you can
reprogram the flash. See chrome-os-partner:8632. At the EC console,
"hibernate 1" will do that, or you can just yank the power.
This also fixes a bug in the flash write and erase commands, where
they weren't properly detecting failure if you attempted to modify a
protected block (missed an interrupt reason...)
New "flashwp" console commands work. LPC commands need reworking.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8448
TEST=manual
Change-Id: I49c38cc25c793094ae3331a4586fda0761b4bac6
Comapre the range to be write (erase) with the range of active image.
If overlap, return error to indicate the access denied.
Note that we actually protect only runtime code and ro data.
FMAP is intentional unprotected so that flashrom can update to new map
before jumping. Since the vector table and init code are in the same
erase page, they are unprotected as well.
BUG=chrome-os-partner:7478
TEST=
Change-Id: Icb5cc89836432a11cef80e18eb66bb39a6c9b1d9
This is necessary at init-time for verified boot to jump from RO to
one of the RW images.
It's also used by factory EC update to update one image and then jump
to the updated image to finish the update. In this case, the x86 does
NOT reboot.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8449
TEST=manual
1) power on x86 and log in
2) sysjump a --> system is in a; x86 has not rebooted
3) sysjump ro --> system is back in RO; x86 has not rebooted
4) reboot -> system is in RO; x86 HAS rebooted
Change-Id: I9dbadcf9775e146a0718abfd4ee0758b65350a87
More modules can be disabled individually through CONFIG_ defines.
Reordered early module pre-init and init, and added comments to
explain why things are ordered in main() the way they are.
Fixed a few assorted init-related bugs along the way, like st32m
keyboard scan double-initializing.
BUG=none
TEST=build link, bds, daisy
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: I04a7fa51d743adfab4be4bdddaeef68943b96dec
This CL adds battery SMI events. And refactors the charging state
machine by adding share state context for all handlers.
Power events are moved to common handler. Minor clean up on console
output messages.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:7526,7937,8450
TEST=manual:
Watch console message when connecting/disconnecting AC adapter and
battery. Check the state transition.
Change-Id: I42eec4f87a9d49bd193cb9dde9080e3dfccbb77c
Board-specific features like lightbar should be config'd at the board
level, not at the chip level.
BUG=none
TEST=build link, bds, daisy
Change-Id: If1df2ca0422f7b8bdc172d0df7bd9f6a1af6a9d2
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Group temperature sensors into different types so we only have to set
temperature threshold for each type instead of each sensor.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8466
TEST=Fan control still works.
Change-Id: I7acc714c32f282cec490b9e02d402ab91a53becf
This works similar to SCI/SMI events, but triggers a separate
level-sensitive signal to the PCH instead.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8514
TEST=manual
From EC console:
gpioget PCH_WAKEn --> should be 1
hostevent wake 0x1
close lid switch (with magnet)
hostevent -> should show wake mask 0x1, raw events 0x1
gpioget PCH_WAKEn --> should be 0
hostevent clear 0x1
hostevent -> should show raw events 0
gpioget PCH_WAKEn --> should be 1
Change-Id: I29832c1dc30239a98987578f07dfeb25791dde11
Keyboard reset now triggers a cold reset.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8397
TEST=power system on, then do 'x86reset cold' for a cold reset or
'x86reset warm' for a warm reset. Check x86 debug console to see that
coreboot detects the warm (soft) reset.
Change-Id: I00930d9f5df98365277cd5c7f2eb8f135c4e4398
Until we solve the I2C hanging issue, we need a reliable way to read
temperature. Add back LPC temperature read command that actually trigger
a I2C read.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8452,chrome-os-partner:8495
TEST=none
Change-Id: Icddd1fe3c1f09889bca633af19041a8aca582de9
Make temp sensor report 0xfd when sensor is unpowered.
Also refactor power specification of temp sensors from thermal.c to
temp_sensor.c.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8279
TEST=none
Change-Id: Ib13813bdbac2f048fbc3b98fae5bbf104ebf37d7
(new method, and x86reset command to call it)
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8460
TEST=manual: powerbtn, wait for system to boot, x86reset
Change-Id: Iad3f5c268b334e8d0ec1adfa2878f9e9d5927b9f
Note that this is a big security hole and should be removed after we
complete the EC autoupdate mechanism and vboot code.
To full update EC firmware on proto 1.0, we need a manual way to switch
EC running on RO/RW. This CL implements the LPC command.
BUG=chrome-os-partner:8415
TEST=on proto 0.5.
ectool reboot_ec RW_A # EC boots to RW A
ectool reboot_ec RO # EC boots to RO
Change-Id: Ibf050328bc4e3d2c6d72bfc478d6334f11f0eb46
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8325
TEST=manual
Boot system with lid open. 'ectool switches' should show lid open.
Use 'dut-control goog_rec_mode:on'. 'ectool switches should show
dedicated recovery signal on.'
Use 'dut-control goog_rec_mode:off'. 'ectool switches should show
dedicated recovery signal off.'
Disable write protect via screw. 'ectool switches' should show WP
signal disabled.
Boot system in recovery mode (power+esc+reload). Should show 0x09.
Change-Id: I0434427c4b5f8c07c02a8714618f7eb101b86fed
This CL adds LPC commands to provide the following information:
- Design Capacity (dword)
- Last Full Charge Capacity (dword)
- Design Voltage (dword)
- Design Capacity of Warning (dword)
- Design Capacity of Low (dword)
- Battery Type (ascii)
- Model Number (ascii)
- Serial Number (ascii)
- OEM (usually Vendor) (ascii)
- Battery charge cycle count (dword)
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:8181
TEST=none
CQ-DEPEND:Iad4d63c996272568b5a661a6716790ef151b29c5
Change-Id: Iabaf7d9862e15c5b21cf5170cf43450e472b7836
These bits are as per definition in "Chrome EC LPC Communication"
document.
BUG=chrome-os-partner:8351
TEST=manual
. tested in concert with coreboot modifications introducing the EC
command implementation
Change-Id: I46d5795e06854e34584132c7fdb37e29150ce179
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:8321
TEST=manual:
type 'battery' in EC serial console, check following fields:
Manufacturer
Device name
Device chemistry
CQ-DEPEND:I0ad3ad45b796d9ec03d8fbc1d643aa6a92d6343f
Change-Id: Iad4d63c996272568b5a661a6716790ef151b29c5
Implement a generalized I2C transmit-receive function that
write-then-read blocks of raw data. Original 8-bit and 16-bit
read/write functions are refactored.
SMBus read-block protocol for ASCII string is also implemented
based on this API.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:8026,8316
TEST=manual:
Type 'lightsaber' to check 8-bit read/write.
Type 'charger' to check 16-bit read.
Type 'charger input 4032' to check 16-bit write.
Change-Id: I0ad3ad45b796d9ec03d8fbc1d643aa6a92d6343f
Note that this only handles lid and power button; see
crosbug.com/p/8325 for write protect.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8185
TEST=manual
1. Check state with lid open
localhost ~ # ectool switches
Current switches: 0x01
Lid switch: OPEN
Power button: UP
Write protect: ENABLED
2. Press power button
localhost ~ # ectool switches
Current switches: 0x03
Lid switch: OPEN
Power button: DOWN
Write protect: ENABLED
3. Release power button and close lid
localhost ~ # ectool switches
Current switches: 0x00
Lid switch: CLOSED
Power button: UP
Write protect: ENABLED
Change-Id: I25f2fa3dfeac004dde9b10a4243ee235875f1b6e
Useful when debugging to determine if a user has an official build or
not, particularly early in the devel process where we're handing
builds to everyone. Particularly useful for proto1, since not all
those systems will be case-open servo-attached.
Also move get-version LPC command into system.c, where it's closer to
the system functions it calls (matches what we do for other host
commands).
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: Idb0f6edf31ca00e32f083be0b0d3f23ab79c5fba
...since x86_power_in_S0() is a terrible function to have implemented
for gaia chipsets, and I need to add more detectable states for lid
switch handling anyway.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: I0c90c6875b27d1bf23f093e88e34eabf2a8c86e4
(Also define other host events)
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8308
TEST=manual:
Use magnet to trigger lid-closed and lid-open.
'hostevent' should show raw events = 0x3.
Press power button.
'hostevent' should now show raw events = 0x7.
Change-Id: I9c8367d5152d526299a7a3149250de84cc2e0557
This CL adds a charge state machine for SMB compliant battery pack.
Vendor specific charge constraints can be applied through function
call, defined in battery_pack.h .
BUG=chrome-os-partner:7526
TEST=Attach EC serial console
Unplug AC adapter: state ==> "discharge"
Plug AC adapter: state ==> "charge"
Battery full: state ==> "idle"
Unplug battery: state ==> "error"
Change-Id: Iabff0988a6067d37c17c11b060bbb7e66505c118
Add build information (date/time/builder) which can be displayed at the
EC console.
Generate a version from the board name and the branch tag.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chromium-os:27013
TEST=on BDS, run version command on the console.
inspect the built binary.
Change-Id: Idb1f68898ba6b811d02919f17ab4536ed9f8934a
This is necessary to support SCI/SMI events.
Note that this breaks compatibility with previous ectool builds - and
probably also breaks flashrom support.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8253
TEST='ectool hello' and 'ectool flashinfo' still work
and 'ectool usbchargemode 3 1' fails with error 2
Change-Id: If39e5b6e7cdcec1b5ec765594e8492925b430b10
Implement LPC commands and ectool commands to
1. Set/get threshold temperature values.
2. Toggle on/off automatic fan speed control.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8251
TEST=Manual test
Change-Id: Ia4282a6fa47a838aed26540f33c1eb7acc92ef0e
The thermal engine monitors the temperature readings from all sensors.
For each sensor, five threshold temperatures can be set:
1. Low fan speed.
2. High fan speed.
3. SMI warning.
4. Shutdown CPU.
5. Shutdown everything we can.
Each of these thresholds can be set to either a fixed value or disabled.
Currently the real implementation of SMI warning and shutting down is
left as TODO, as indicated in the comment.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8250
TEST=Manually change threshold value to test all actions can be triggered.
Change-Id: If168dcff78ef2d7a3203cb227e1739a08eca961e
Actual RPM is now read from LPC mapped space. Modify this command to
return target RPM so we can verify EC receives target RPM.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8238
TEST=Get the same value after setting target RPM.
Change-Id: I9bcc9edd327cec1311b51fd0fcbc4a43b353daff
We now read temp sensor readings using the EC mapped space.
So we don't need this command.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8239
TEST="ectool temps 0" works.
Change-Id: I47f425e45cea992b19734f39ac6d9f6db6433d39
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8097
TEST=manual
faninfo
should report fan is disabled
powerbtn
system turns on, fan turns on
faninfo
should report fan is enabled
powerbtn
system turns off, fan turns off
faninfo
should report fan is disabled again
Change-Id: I1be67004edb23ccd18ad434c9340bfbecc22e7c4
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8097
TEST=manual
faninfo
should report fan is disabled
powerbtn
system turns on, fan turns on
faninfo
should report fan is enabled
powerbtn
system turns off, fan turns off
faninfo
should report fan is disabled again
Change-Id: I8e94c142bf18d07f83bac05287bcd503a098cee7
Add a task to update temperature values in LPC mapped value space every
second. Also modify ectool to read directly from LPC mapped space.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8065
TEST="ectool temps" gives same result as "temps" from ec console.
Change-Id: Idcdef8d822724f9bd22d7e819c717cba5af5eb77
A temperature polling task is added to achieve temporal correction and
also reduce the latency of reading temperature.
Factor out sensor specific part to keep code clean.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:7801
TEST=On link, 'temps' shows all temperature readings.
Cover each sensor with hand and see object temperature rise.
Compilation succeeded on bds/adv/daisy/discovery.
Change-Id: I3c44c8b2e3ab2aa9ce640d3fc25e7fba56534b86
Add a LPC command to control USB charging mode. Also add the command to
ectool.
BUG=chrome-os-partner:7476
TEST=Manually test on link proto-0.
Change-Id: Ica87d0a690bc86e28844bd695f31641398b21939
Signed-off-by: Vic Yang <victoryang@chromium.org>
This CL attempts to abstract underlying bus from i8042 code. Nearly
all i8042 logic is isolated already. This patch is intended to allow
us to use i8042 logic for processing keys and commands on boards which
do not necessarily use LPC as the host <--> KBC bus interface.
This CL does the following:
- Define KBC bus <--> host (kbc_host_bus) on a per-board basis in
board.c.
- Add generic wrappers in place of lpc_keyboard_* in i8042 code.
- Define the behavior of generic wrappers in EC-specific keyboard
sources. If board.c specifies LPC, then send via LPC.
TODO: This needs to be tested on real hardware...
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=None
TEST=Locally compiled for Link, BDS and Discovery.
Change-Id: I9cabd514bd44fd6b508c26994eccc3011eedbc0f
