The typical power consumption in sleep mode is 65uA.
IT83xx uses deep doze mode for low power idle task. The typical power
consumption in this state is 280uA (depends on EC tasks, it should be more)
and the wake up time is in microsecond. We are using deep doze mode for
low power idle task instead of sleep mode is because the wake up time
will be 6ms more.
While in system hibernate (EC sleep mode), EC won't wake up frequently so
we can keep the power consumption at 65uA.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=- hibernate 0 [1|999999]
- hibernate [1|5|10|600]
- hibernate then press power button.
- hibernate then lid open.
Change-Id: I94884c010264f01ede4950c6bb1b0a444d7b1e6d
Reviewed-on: https://chromium-review.googlesource.com/383332
Commit-Ready: Dino Li <dino0303@gmail.com>
Tested-by: Dino Li <dino0303@gmail.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The interrupts on all of the gpios detecting if the device is on were
edge triggered. If the rising edge happened in between when the gpio
level was read and when the interrupt was enabled, then the device state
could be falsely detected as off for a short period of time. This change
changes them to GPIO_INT_HIGH.
BUG=none
BRANCH=none
TEST=buildall
Change-Id: I9aa3cff14047cf4f6473c32f2cdc4724afca3414
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385164
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The interrupts to detect when the falling edge on the UART signals are
currently disabled and never reenabled. Power off is detected by polling
and not through interrupts. This change removes all of those falling
edge interrupts.
BUG=none
BRANCH=none
TEST=cr50 can detect when the EC, AP, and Servo are off or on
Change-Id: I0fd8a0d970f3235b26af6b90dd395ea7c75e0c17
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385192
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Removed power LED support.
In case of discharging, if below critical level, LED should blink;
otherwise, will show power state;
In case of charging, will show charging/battery state.
BUG=chrome-os-partner:56932,chrome-os-partner:57025
BRANCH=none
TEST=Verified on EVT with <10% and <3% battery, LED is blinking
amber at proper duty cycle.
Also verified ectool led command works as expected.
Change-Id: I903396a9a1dc5e08618683f7124b09678678e233
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/383880
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
When cr50 connects to the AP usb it should only initialize the usb when
it knows that the AP is on. If usb is incorrectly initialized it can
prevent cr50 from going to sleep. In this change the AP usb will be
initialized when suzyq is disconnected or on HOOK_CHIPSET_RESUME and it
will be released on HOOK_CHIPSET_SHUTDOWN.
BUG=chrome-os-partner:55747
BRANCH=none
TEST=manual
On reef run apreset and verify the AP can communicate with cr50
over usb after it boots up.
Run poweroff and verify cr50 has released the usb.
power the AP back on and check that it can communicate with cr50
again
Change-Id: Id35010525e2354ee140d3b7220fb5ea434a0993f
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383979
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
On CHIPSET_SHUTDOWN set the idle_action to deep sleep. If sleep is
enabled it will go into deep sleep. If not it will wait until sleep is
sleep is enabled.
This change also sets the idle_action to IDLE_DEFAULT when resuming from
deep sleep or during init. Before cr50 kept track of the previous idle
state in a PWRDN register and then used that state during the next
resume. If we went into deep sleep, on resume we want the idle action to
be reset to sleep and then only enter deep sleep if we have detected the
AP is off.
BUG=chrome-os-partner:56100
BUG=chrome-os-partner:55747
BRANCH=none
TEST=manual
run 'poweroff' on the AP and see that cr50 enables deep sleep
verify that even if the ap is powered off it doesn't prevent ccd
from working and when suzyq is unplugged cr50 will go into deep
sleep
After running poweroff on the AP wait a while and run powerbtn
on the EC. Verify the system can boot up fully without going
into recovery.
Do this on gru and reef.
Change-Id: I07f5a9d85dd0467cd22e499d4261c75caf653563
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/373139
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When generating the RSA endorsement primary key, use the
CR50 vendor specific template. Doing so generates the
RSA key corresponding to the certificate issued at manufacture.
Also, always start the RSA key generation counter at 1. Doing
so matches the certificate generation process at manufacture;
and there is no harm in always starting at 1, since the key
generation process remains deterministic.
BUG=none
BRANCH=none
TESTED=generated key matches endorsement cert;
checked via attestation_client
Change-Id: I6a5c329e99292e32f880c0c5ea364d511cb6ea82
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/386279
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Tested-by: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
- Enable MKBP events:
Allow EC to send sensor event to the kernel sensor stack.
- Disable APCI message display, to avoid overwhelming the console.
- Set the rotation matrices to match Android requirement.
BUG=b:27849483
CQ-DEPEND=CL:384341
BRANCH=reef
TEST=Check we can receive sensor events for ARC++.
Check the acceleromter axis are correct.
Change-Id: I5fa58e22167f027bd1b84e72f002060d15d882c4
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385082
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The g i2c slave controller does not support clock stretching, so it is
necessary to flow control the AP by some other means. Luckily there is
an interrupt line which g can toggle and the AP can watch.
This patch adds generating a pulse on the AP interrupt line once g
finished processing the i2c transaction. In case of the read
transaction the pulse is generated after the data to read is put in
the i2cs transmit buffer.
BRANCH=none
BUG=chrome-os-partner:57338
TEST=with this patch and the AP firmware synchronizing on the
interrupt pulse, the TPM initialization succeeds in coreboot and
depthcharge.
Change-Id: I16c09b59b7d772624baa9d1f5258aaff26f91ff9
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385256
Reviewed-by: Scott Collyer <scollyer@chromium.org>
The bug with USB data connection when the BD9995x power save mode is
enabled has been solved.
We can re-enable the low power mode to save energy.
BRANCH=gru
BUG=chrome-os-partner:57310
TEST=check that usb ethernet works after booting on kevin
Change-Id: I439f97c43e79e50db7af1f63207ad72ce8192a30
Reviewed-on: https://chromium-review.googlesource.com/385696
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This moves the various GPIO/PINMUX reconfigurations needed to
occasionally drive a common-pulldown signal into a set of clean
functions. There's no new functionality, it's just abstracting
the control of SYS_RST_L and EC_RST_L into specific functions.
BUG=none
CQ-DEPEND=CL:380484
BRANCH=none
TEST=make buildall; test on relevant hardware
I tested this on Gru, Kevin, and Reef, and it works correctly in
all cases. I used flashrom over CCD to update both AP and EC
firmware on each of those systems.
If you just want a quick check, you can run this instead:
sudo flashrom -p raiden_debug_spi:target=AP --flash-name
sudo flashrom -p raiden_debug_spi:target=EC --flash-name
Change-Id: I15fa3b2089d10649bfd17f442e3b261f3b62b92e
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382665
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Now that the AP uart is enabled whenever the AP is on, stop using it to
detect the state of servo. Using the EC uart is good enough and it
simplifies the device state stuff.
BUG=none
BRANCH=none
TEST=on reef and gru verify cr50 can detect servo and disable/enable
cr50 uart at whenever it is attached/detached.
Change-Id: I2fe6e796feaae5d90682d5015cdde6b46950dae6
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383955
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
To improve spec compliance, we reduce input current limit on PD voltage
transition. This may cause us to brownout if the battery cannot provide
sufficient current, so use the max. negotiated current when our battery
is critical.
BUG=chrome-os-partner:56139
BRANCH=None
TEST=Boot with critical battery on kevin, verify system boots to OS
without brownout.
Change-Id: I1bdb2b7168c7b810af789e2206d0420f5d2bdcdd
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383733
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
charge_manager may request a charge current limit less than the
capability of the supply in certain cases (eg. during PD voltage
transition, to make an effort to comply with reduced load spec).
Depending on the battery / system state, setting a reduced charge
current limit may result in brownout.
Pass the uncapped / max negotiated current to board_set_charge_limit()
so that boards may use it instead of the requested limit in such
circumstances.
BUG=chrome-os-partner:56139
BRANCH=gru
TEST=Manual on kevin with subsequent commit, boot system with zinger +
low-charge battery, verify devices powers up to OS without brownout.
Change-Id: I2b8e0d44edcf57ffe4ee0fdec1a1ed35c6becbbd
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383732
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
By this time hopefully all old hardware has been junked. Take out the
old code to check for old hardware to save a little bit of space, since
space is tight.
BRANCH=gru
BUG=chrome-os-partner:55561
TEST=Build and boot
Change-Id: I9b147a8c1955e1c2c3fee3dd6ab7fc6e520be4bf
Reviewed-on: https://chromium-review.googlesource.com/384452
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Simon Glass <sjg@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This reverts commit 1966433427.
The CL seems to break USB ethernet dongles (and maybe other USB
functionality). Reverting for now so development isn't impacted.
BUG=chrome-os-partner:57310
BRANCH=gru
TEST=check that usb ethernet works after booting on kevin
Change-Id: I91d05da65d56afcd8a21ac2074a31f759c4aaec8
Reviewed-on: https://chromium-review.googlesource.com/383862
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
LID_OPEN gpio is interrupt trigger on both the edge. If the system is
hibernated when LID is open and then LID is closed, system wakes from
hibernation. Hence setting the LID_OPEN GPIO as interrupt raising before
hibernation so that system won't wake up upon LID close in hibernation.
BUG=chrome-os-partner:57221
BRANCH=none
TEST=Issued hibernate when LID is open, closed the LID after hibernation
observed system won't boot back till LID is open again.
Change-Id: Idc89c3d85b7d246c3e18d0ced48e7d47bebeafec
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/383753
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
There is leakage on SYS_RST_ODL from the internal pullup cr50 has on
DIOM0. This change removes the internal pullup on reef.
On Kevin there is a bug preventing the EC from being able to pull
sys_rst_l up high enoug for cr50 to detect that it is pulled high. This
change adds an internal pullup back when cr50 detects that it is on a
kevin or gru.
BUG=chrome-os-partner:56945
BUG=chrome-os-partner:53544
BRANCH=none
TEST=On gru and kevin remove servo verify when apreset is run on the EC
it resets cr50 and the AP. Run pinmux and check that there is a pullup
on diom0 on kevin but not on gru.
Change-Id: Ica4f557745967b93e0bd9c8462916b1f735756ac
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/381322
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
All PIN() assignments in board/$BOARD/gpio.inc must be unique,
since otherwise you're just creating duplicate names and table
entries for the same core interrupt and may not be initializing
things the way you think.
BUG=none
BRANCH=none
TEST=make buildall; test on Cr50 hardware
Also verified that the image size is exactly the same before an
after this CL.
Change-Id: Ifb1805a010905f67fc5c0d246b6252af73715409
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383773
Reviewed-by: Randall Spangler <rspangler@chromium.org>
On different systems SYS_RST may be edge triggered, so it is not
guaranteed holding it low will hold the AP in reset. With this change,
enable_ap_spi now holds the EC in reset, so it is guaranteed the AP is
in reset.
BUG=chrome-os-partner:54982
BRANCH=none
TEST=run 'sudo flashrom -p raiden_debug_spi:target=[EC|AP] --flash-name'
on gru, kevin and reef
Change-Id: I3176462b932eba5bf8d69dbab70500bca8c7ff46
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380484
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
For kevin, we are not using the PROCHOT# signal for the charger so we
can enable a power save mode. This commit will leave BGATE on but
without monitoring the PROCHOT# signal. When VBUS or VCC is removed
from the charger, the charger will enter this power save mode. It will
return to normal functionality when VBUS or VCC is applied.
BUG=chrome-os-partner:55631
BRANCH=kevin
TEST=Flash kevin; Verify we can still charge; Verify that power
consumption is less with this patch applied than without.
CQ-DEPEND=CL:382877
Change-Id: I05274a770b35c981e0541d8f79f66b81ffb4d153
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/383391
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Enable interrupt from BMI160 for FIFO control.
It can be use for significant motion detection.
BRANCH=kevin
BUG=b:28552512
TEST=Pass CTS tests SensorBatchingTests, SingleSensorTests
To trigger FIFO interrupt during the batch tests, EC lid angle
calculation is disabled from the EC with "acclerate 0 0"
Change-Id: I3ed4afcdee7075c5e5e20974d70a9e6bd64ecd52
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382677
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Allow the detection of tablet mode for sensors and powerd.
BUG=chromium:606718,b:28552512
BRANCH=kevin
TEST=Check with evtest that events are send.
Check sensor data is in lid referal in tablet mode.
Change-Id: I0822e7419ccba01d70bf9327593164c15493fb10
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380377
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This makes minor changes to GPIOs for the next build:
- USB_C0_PD_RST_L is actually push-pull in next build, so remove the
comments about USB_C0_PD_RST_ODL.
- Added TABLET_MODE
- Make the net name for volume up/down buttons match the name in the
schematic.
BUG=none
BRANCH=none
TEST=built and booted on Reef EVT
Change-Id: I0799de059d71809174e246b6bbd7f3a2fe25686a
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/381791
Reviewed-by: Shawn N <shawnn@chromium.org>
Data from the sensor (in Pa) does not fit in 16 bits.
Add set_range/get_range to allow the AP to set the precision.
For pressure around ~1000 hPa, we need to right shift by 2 bits.
BUG=chrome-os-partner:57117
BRANCH=reef
TEST=Check data is not truncated anymore:
> accelrange 4
Range for sensor 4: 262144 (Pa ~= 2621 hPa)
> accelread 4
Current data 4: 24030 0 0
Last calib. data 4: 24030 0 0 (x4 = 961.2 hPa)
Change-Id: I3f7280336e5120d903116612c9c830f4150d2ed7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382323
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Input to the EC UART console is restricted by default so that
casual passers-by can't type random commands to it through the
case-closed debug connection. However, there's no need to
restrict the AP UART console, since it's entirely under the AP's
control.
This CL leaves the AP console enabled by default whenever the CCD
cable is connected. It will be disabled when the AP is powered
down or while servo is attached, but enabled otherwise.
BUG=chrome-os-partner:55322
BRANCH=none
TEST=make buildall, test on Cr50 hardware
Use the "ccd" command to see and modify the UART console
settings, and the "devices" command to observe how things change
when servo is connected and things are powered up and down.
Change-Id: I5cc453bc60473269e22112cf49f61495733abb10
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382152
Commit-Ready: Bill Richardson <wfrichar@google.com>
Tested-by: Bill Richardson <wfrichar@google.com>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This CL includes changes in Cr50 required to support TPM via
the I2CS interface.
BRANCH=none
BUG=chrome-os-partner:40397
TEST=manual
Limited testing so far. Verified that the I2CS interface is
initialized properly and that register reads occur when
initiated on the AP console via command i2cget -y 8 0x50 0x1 w
Change-Id: I16ac17c7c82d420a384908e4b5a9867a3b24bc9e
Reviewed-on: https://chromium-review.googlesource.com/356241
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Port USB firmware update to stm32f4 dwc usb from st usb.
This includes usb dwc usb stream inplementation, generic
endpoint interfaces, and the sweetberry test case.
BUG=chromium:608039
TEST=usb update works
BRANCH=None
Change-Id: Ia26e4f7e990ee64991468799c99b036f5f32190f
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/377520
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The long life scratch register storing the board properties is not
cleared after a hard reset. This change clears the properties before
updating them, so we can reset the properties entirely instead of just
adding to them.
BUG=none
BRANCH=none
TEST=Update Cr50 with an image. Remove one of the board properties it
uses and verify that property has been removed once you update it.
Change-Id: I078dc1443d9f2e7f8761159906e1a277d79cb3cb
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380433
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
CONFIG_FLASH_NVMEM_SIZE was set to CFG_TOP_SIZE and then the partition
size was computed by dividing this value by 2. Changed this so that
now the partition size is set to CFG_TOP_SIZE and the total size is
the partition size * 2. Also reduced the CFG_TOP_SIZE to 0x4000 as
that should be plenty for TPM requirements and leaves room for future
gnubby use.
BRANCH=none
CQ-DEPEND=CL:379076
BUG=chrome-os-partner:56798
TEST=manual
Tested on Kevin, erased the existing NvMem area and verified that TPM
was still manufactured and executed the command: trunks_client --own
Erased parition 0 and 1 in the new locations and repeated the tests.
Change-Id: Ie8910bec641d8d1ff390be5b03b430bf39d18404
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/379095
Commit-Ready: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Tested-by: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
TPM2.0 needs more NvMem space and currently the whole block is
contiguous in memory with 2 partitions. This CL removes the
requirement that the partitions are in contiguous which allows for 1
partition to placed at top of RW_A and the other at RW_B.
This CL does not change the size of each partition as that will be
done in a subsequent CL.
BRANCH=none
BUG=chrome-os-partner:56798
TEST=manual
Tested with the unit test 'make runtests TEST_LIST_HOST=nvmem' and
verified that all tests pass.
Tested on Kevin, erased the existing NvMem area and verified that TPM
was still manufactured and executed the command: trunks_client --own
Erased parition 0 and 1 in the new locations and repeated the tests.
Change-Id: I295441f94dccdf5a152c32603c2638ffac23f471
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/378675
Commit-Ready: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Tested-by: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
There is now a call to reset the retry counter before the hard reset
after an update. Cr50 will use the updated image for the next 5 boots,
but on the 6th it sees the retry counter is greater than 5 and then
jumps back to the old image. Cr50 needs to call
system_process_retry_counter to reset the counter and corrupt the old
image header to prevent falling back to the old image.
Normally the reset counter would be processed after it receives a TPM
command. Reef does not have Cr50 TPM support. Until Cr50 has TPM
support for Reef, Cr50 should have a different point to know when the
update is good. This change adds a board property to mark the process
the reset counter once the Cr50 USB controller receives a set address
request from the host. On Reef the controller defaults to the AP PHY
when suzyq is not connected, so it should have a connection to the AP
or through suzyq after boot.
The board property is only added to Reef. Behavior on Kevin and Gru is
unchanged.
BUG=chrome-os-partner:56864
BRANCH=none
TEST=update reef. Wait until Cr50 prints 'SETAD' then run 'rw
0x4000012c' and verify it is reset to 0.
Change-Id: If517202f25a694cd70550e3be047ea502e7c5383
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380354
This patch makes a few small changes to gpio.inc:
- Correct NC1 assignment (GPIO00)
- Add ENG_STRAP (GPIOB6) which is currently not connected to anything.
- Cosmetic fix for LEDs (replace spaces with tabs for alignment)
BUG=none
BRANCH=none
TEST=built and booted on Reef
Change-Id: Ieca83be6c7423694d88f21ebfc3f57849bf42cde
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380449
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This fixes an issue where the power+charge LED sometimes changes
more than once when power is plugged in.
BUG=chrome-os-partner:56471
BRANCH=none
TEST=Reef power+charger LED changes from one color to another instead
of back and forth (unless there are a lot of PD hard resets, but
that's another matter)
Change-Id: I0ea0dd59cbb7c86b758123fd4e6c8e7b20efa5df
Reviewed-on: https://chromium-review.googlesource.com/378756
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
