This simplifies the re-flashing for stm32 based platforms.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8865
TEST=On Daisy, flashrom -p internal:bus=lpc -w ec.bin
Change-Id: I66860383c34110b1edf852929c244a2b682bc105
(Touchscreen was already disabled in S5)
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9736
TEST=from console, 'gpioget touchscreen_resetn' in these cases:
1) system is off -> 0
2) system is on with lid open -> 1
3) system is on with lid closed -> 1
4) system is suspended with lid open -> 1
5) system is suspended with lid closed -> 1
6) system is shut back down -> 0
7) suspend system with lid open, THEN close lid -> 0
Change-Id: I5fc80b72ea9dcfbf11f5280d79ae805c2ef1b6df
The VMA of the .data segment is in RAM, but we actually put it into FLASH.
The linker doesn't notice if it runs out of flash, so it creates an invalid
image.
This adds an explicit check to be sure it all fits. It also refactors the
region declarations to be more explicit. For vboot-enabled configurations,
CONFIG_SECTION_* - describes the extent of flash for one entire image
CONFIG_FW_* - the region within the SECTION for the firmware only
CONFIG_VBLOCK_* - the region within the RW SECTIONs for the vblocks
CONFIG_VBOOT_ROOTKEY - the region within the RO SECTION for the root key
Look at chip/lm4/config.h for the best example.
BUG=chrome-os-partner:9839
TEST=manual
Build it, run it.
Change-Id: I3c652e82d58a5328115cc750c80ecba6a3fd99a3
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Don't do anything on write protect until we have properly verify the
current implementation to avoid bricking Daisy and Snow boards.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8865 chrome-os-partner:9849
TEST=None
Change-Id: I599a2a733b7304dc17286fae6fd7807fd8f6981c
Implementation of the flash driver for the stm32f100 chip used on Snow board.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8865
TEST=On Snow board, use "flashwrite/flasherase" commands from EC console
and verify result with "rw" command.
Change-Id: Ie8b8be3d549ff9ec8c3036d5f4a97480daa5e03e
Simulation now simulates the physical signal, so uses the power state machine.
Power state machine now doesn't send a spurious press/release event if
the power button signal glitches and returns to its previous state.
Properly handles powering back on when waking from hibernate, if the
lid is open.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9817
TEST=manual:
All of the following should power on the system:
1) at debug console, powerbtn
2) press power button
3) lid open
4) press power+esc+refresh
5) hibernate 10, then press power button
6) hibernate 10, then open lid
These should leave the system off:
1) press power+esc
2) hibernate 10, then let it wake up on its own
Hold down the power button to power on the system, and keep holding it
down; system should shut back down after 8 sec.
Hold down power+esc+refresh, and keep holding it down; system should
boot and NOT shut down after 8 sec.
Change-Id: I2dde951fe67544b6a24c607f0c4ba415ccd2f82f
Ensure we can jump between EC images without powering down the GAIA AP :
- preserve GPIO state
- go back to "power-on" state if needed in GAIA state machine.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8865
TEST=On Daisy, boot Linux, then type "sysjump B" and observed we can
still interact with Linux without any AP reboot.
Change-Id: Ia2bd0f65ea348813b120bcc3a3f3bdfa96a9877a
The stm32 needs to flash half a page (ie 128 bytes),
the current communication protocol is limited to a 64-byte payload for
flash write message.
The workaround buffers the first 64 bytes to be able to flash a full
128-byte half page.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8865
TEST=on Daisy, run flashrom -p internal:bus=lpc -w ec.bin
Change-Id: I8036e66d2aa456b3409f4f8c74daa3755e7c9a51
This also updates the communication protocol between the EC and the AP in a
non backward compatible way.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9614
TEST=on Daisy with updated kernel driver, use the keyboard in ChromeOS
Change-Id: I5a50e9a74b9891153a37ea79318c8a66a1b0c5ca
This cleans up I2C init and debug commands across boards.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=on link and bds:
i2cscan
lightbar run
powerbtn (to power on system)
temps (to read i2c temp sensors)
battery (to read battery)
charger (to read charger)
Change-Id: If3fb0cdb8d3178592bf68cbb2e72bc4b7f71dec5
This was used on the hybrid Badger-Lumpy systems for one-off testing.
It wouldn't necessarily work on a bare Badger board, and maintaining
it resulted in frequent build breaks.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=build link, bds, daisy; boot link and bds
Change-Id: Ib64ccad9f38d76832ab57f7254dbf32f3d5e4a5e
And start wiring to x86_power so it can detect AC state changes
(needed to enable/disable turbo).
*YES*, this compiles for BDS/Daisy now...
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9069
TEST=plug/unplug AC power and look for "x86 AC on" / "x86 AC off" in debug log
Change-Id: I8399fab9637d6635a1c615f07448fd45b86bc25f
The phenomenon is that there is a char on-hold in port 0x60 and the kernel
never picks it up. Hence the keyboard cannnot be recognized after resume.
It comes from multiple reasons:
1. The command I8042_CMD_RESET_BAT(0xff) and I8042_CMD_ENABLE(0xf4) didn't
clean the buffer.
2. clean_underlying_buffer() has clean the queue, but forgot to clean the
TOH (TO Host). Add keyboard_clean_buffer() to clean the TOH (To Host).
3. When KB interrupt is just enabled, the IRQ didn't sent if there is
a char queued in buffer already. keyboard_resume_interrupt() solves
this.
4. Not all keyboard reset should reset the buffer. Only the enable/disble
of controller RAM should NOT reset buffer. Other enable/disable
should clean the buffer.
5. i8042 commands (those commands to port 0x64) should NOT return ACK
even the parameter byte(s) goes to port 0x60.
6. Keyboard was disabled by kernel, but key stroke still sent to host
(this needs the BIOS to fix).
Also fix the minor issues:
1. I8042_CMD_RESEND should not return I8042_RET_ACK.
2. I8042_DIS_KB/I8042_ENA_KB should effect the controller RAM content.
3. only send out the scan code when keyboard is enabled.
4. add kblog command for future debug (disabled by default because it
neeeds 1KB of memory).
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
BUG=chrome-os-partner:9525
TEST=tested on link. Start from S0.
1. Run powerd_suspend.
2. Expect system is in S3.
3. Press any key to wake up system.
4. Expect system is up and keyboard is working.
5. repeat for 20+ times.
Change-Id: I1c48822687d7c1f7ef0e8d8bca54bf9b05fd785f
This CL adds a simple FIFO to store keystrokes. The keyboard_scan()
function will push keystrokes into the FIFO and is the only producer,
while keyboard_get_scan() will pop entries and is the only consumer.
BUG=chrome-os-partner:9594
TEST=tested on daisy
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Testing was mostly subjectively done by typing a sentence quickly
at the Chrome UI.
Change-Id: I6faff41b0f16b75d6426df13a239f84eb62634ec
Preparatory work to use common host command code between ARM and x86.
Just rename constants, do not change the binary API.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9614
TEST=make BOARD=link
Change-Id: I534d427c9b50103273835a6f32a0ddb622c762b3
This patch splits apart EC_INT and CODEC_INT handling for two reasons:
1. Allow other tasks to interrupt the AP without triggering
the keyboard noise suppression.
2. Allow more work to be done after a keystroke is detected but
before interrupting the AP. This is intended to prevent latency
issues with the noise suppression.
Also, Snow does not currently have CODEC_INT hooked up, so it
does not need the extra function for suppressing keystroke noise.
BUG=chrome-os-partner:9594
TEST=tested on daisy (keys still respond), locally compiled for snow.
Change-Id: I73bd42bb7263005b11724337162646092292556f
Signed-off-by: David Hendricks <dhendrix@chromium.org>
An upcoming CL will use the number of keyboard outputs (currently
and incorrectly called KB_COLS) in another file. So this is a good
time to clean up the naming to remove some column/row ambiguity and
move the #define to board-specific configuration.
BUG=none
TEST=locally compiled for link and daisy
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I155e3d6f2069c582517016c1116eaf668ffca86a
This has been true since proto1, and will continue to be so on EVT+.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=faninfo
(on the one board modified for EC +5VALW control, you can also toggle +5VALW and see that powered reports the correct state).
Change-Id: Iaabfa3b84eb7eba46cf9972ec402153770f49fd7
Preparatory work to use common host command code between ARM and x86.
Every command sends back explicitly the size of the response payload.
The size of the response defaults to 0 ond can be updated.
Add a protocol version number returned as command 0x00 to help with
backward compatibility.
move a couple of function from lpc specific header to host commands to
be able to implement them for the I2C link.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9614
TEST=make BOARD=link
Change-Id: I6a28edf02996ddf6b7f32a3831d07d5f0271848f
We don't actually use image B for boards with the STM32F and there is
no longer enough space for it.
BUG=none
TEST=locally compiled for Snow
Change-Id: Ic668c718feaef4cf808869474dc05e45a5f7290c
Signed-off-by: David Hendricks <dhendrix@chromium.org>
This adds a missing init hook
BUG=none
TEST=Tested on Snow
Change-Id: I4571d5bddf415b06e27e5e9eaadbb6017bde4bbe
Signed-off-by: David Hendricks <dhendrix@chromium.org>
This helps us keep track of how long vboot is taking on the EC.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9651
TEST=reboot system and look at debug log. time shouldn't start over after it jumps to image A.
Change-Id: Iad86e90d42dabf1c67b2c2be80dda1151cf9a288
BUG=chrome-os-partner:7459
TEST=manual
In the chroot:
cd src/platform/ec
make BOARD=link
The firmware image (build/link/ec.bin) is signed with dev-keys. Reflash the
EC and try it, and it should verify and reboot into RW A.
Additional tests (setting USE_RO_NORMAL, poking random values into VBLOCK_A
or FW_MAIN_A to force RW B to run, etc.) are left as an exercise for the
reader. I've done them and they work, though.
Change-Id: I29a23ea69aef02a11aebd4af3b043f6864723523
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Open drain cleanup minimizes leakage and signal glitching on shared
reset/signal lines, and is tidier than explicitly switching the
signals between inputs/outputs.
Touchscreen and lightbar are powered by +5VALW so their signals need
to be dropped when +5VALW is off to avoid leakage, and so they see a
clean reset signal when they're powered up.
Moved +5VALW power-on to S5-S3 transition, to minimize power draw in
S5. This also ensures that 5VALW-powered devices get reset when the
device bounces through S5. (No effect on proto1, where 5VALW is not
under EC control.)
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9172
TEST=boot and shutdown system; still works.
Change-Id: Ia4bf0703292a189c324ce283d1e79a33776ee40f
Much of the code in gpio-stmxxx.c is duplicated. Also the gpio_get_name()
function is not present in the new file.
Create a common gpio.c file to hold this function, and hopefully other
code in the future.
BUG=none
TEST=build on all platforms, boot on daisy
Change-Id: I4ab33e0e5c52843b770fabc777c917493abccffe
Signed-off-by: Simon Glass <sjg@chromium.org>
Remove the start-up debug message which otherwise ends up being the
first thing displayed on boot, ahead of the banner.
BUG=chrome-os-partner:9424
TEST=very ad-hoc:
1. build and boot on daisy, flash U-Boot with USB using
'cros_bundle_firmware -w usb', inserting daisy
USB cable when it says 'Reseting board via servo...'
2. Press cold reset, then power on, see that it powers on
3. Then hold power-on for 8 seconds and see that it power off
4. XPSHOLD function not tested yet
Change-Id: I4f057ad32c3a857851d02935286683ea87dc7cd1
Signed-off-by: Simon Glass <sjg@chromium.org>
This saves ~70mw of power.
To make this work, I also had to stretch the power button signal to
give the system a chance to come back up when the user taps the power
button.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9574
TEST=manual
For each of the following tests, wait ~15 sec after the system is
powered off to give it a chance to drop DPWROK.
1) tap power button -> system turns on
2) hold power button 1 sec -> system turns on
3) open lid -> system turns on
4) silego reset (power+refresh, or power+esc on proto1) -> system stays off
5) silego recovery (power+esc+refresh) -> system turns on
6) hold down power button and type 'reboot' on EC console -> system turns on
7) type 'powerbtn' on EC console -> system turns on
Change-Id: I781cf3e665104192521b7fb9ff75a3c3e7f43464
This is cleaner than having x86_power explicitly know about everything
else in the system that cares about power transitions.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=boot and shutdown system; still works. Mouse powered to system is off in S5.
Change-Id: Ib673ca2d9edd5473334e7604e98b99b02b768419
This CL initializes the default transmit mode for I2C to CMDC_NOP.
When we introduced the protocol, we changed the default mode to send
message protocol version. This didn't take into account that U-Boot's
probe command (and probably other userspace commands) do a single-byte
read to probe. So when the probe was asking for a single byte, by
default we were sending multiple bytes for the version message.
This CL also makes the EC reset the mode to noop after each EC-to-AP
transmission. This will help ensure that the EC ends up in a known
state e.g. if the system is reset. That will require the AP to set the
mode before requesting any real data, but that's how we do things now
anyway.
BUG=chrome-os-partner:9556
TEST=Tested on Daisy.
Tested by running "i2c dev 4; i2c probe" at U-Boot prompt, booting
system, and typing on keyboard. Everything seems to work okay.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I0849c94588a9a60ade657af8f941f7267553e316
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9554
TEST=manual
1) Boot system. No recovery.
2) Boot system holding down Refresh+Esc. No recovery.
3) Hold down Power+Esc. System reboots and stays shut down.
4) Hold down Power+Esc+Refresh. System reboots into recovery mode.
Change-Id: I53db224b6d2a03406244e79fb64fb67851919857
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9117
TEST=version; board version should be 0 on proto1 and 1 on EVT
Change-Id: Ic64ad0d009151fbda09f5c1605ef50ae708cb6ae
Implements the on-chip flash erasing and writing functions.
The actual writing is done from a routine in internal RAM (using the
special .iram.text section) with interrupt disabled as we cannot read
flash during the writing process.
The write-protect feature is only lightly tested.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8865
TEST=run on Daisy, from the EC console, use flasherase and flashwrite
commands and observe the results using rw command.
Change-Id: I4c64cf28b23df52b18500b42a32a7d3668d45ba6
This fixes an off-by-one error that was preventing two keys
(left and right arrow) on output 12 from being driven properly,
and causing some other weird ghosting effects.
BUG=chrome-os-partner:9516
TEST=Tested on Daisy
Pressing the right arrow shows this at the EC console:
[1 keys pressed: -- -- -- -- -- -- -- -- -- -- -- -- 40]
and pressing the left arrow shows this at the EC console:
[1 keys pressed: -- -- -- -- -- -- -- -- -- -- -- -- 80]
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ib7af21444c2d03a0787fb1a28b520a779013774d
This is referenced by various files, so should be in the gpio.h header.
BUG=none
TEST=manual:
build and boot on daisy, see that USB download still works
build on all platforms
Change-Id: If579c975ef6c82988b9e411eeaa97c950d9efce4
Signed-off-by: Simon Glass <sjg@chromium.org>
