Match ec_commands.h, adding new type and sensors.
BUG=none
BRANCH=reef
TEST=Check on Reef that barometer sensor info is displayed properly.
Change-Id: I257f5161e5f57be562a2b3a29442b49f47f3fc89
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394749
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Due to an error in ms_command_sizes, fifo_info command
would fail when lost vectors are present:
packet too long (16 bytes, expected 10)
Reorder ms_command_sizes commands properly.
Get the number of sensors present before printing the number of lost
vectors per sensor.
BUG=none
BRANCH=none
TEST=On cave (with broken MKBP support), check fifo_info
is returning the lost vectors count.
Change-Id: Ic745eb762563705372d8a670ce34eab15e188bf9
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/391887
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
In preparation to the new CR50 image release bump up the minor version
number to trigger autoupdate on the devices in the field.
BRANCH=none
BUG=none
TEST=none
Change-Id: I7744b8cb8436d9134ee5900b352487a1cdddcd28
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/392447
Previously, there was no way to identify which flash chip was used by
the EC, for ECs using an external SPI flash. Now, 'ectool flashinfo'
will print more information about the SPI flash chip in these cases.
BUG=chrome-os-partner:56765
BRANCH=any EC with MEC1322 or NPCX still going through factory
TEST=define CONFIG_HOSTCMD_FLASH_SPI_INFO, then
'ectool flashspiinfo' on samus indicates no SPI flash info,
and prints additional info on chell and kevin. Without
the config defined, all platforms report no spi flash info.
CQ-DEPEND=CL:386368
Change-Id: I3c162f7ad12ed4b30ab951c03f24476683382114
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385702
Reviewed-by: Shawn N <shawnn@chromium.org>
We no longer depend on this directory, so there's no need to
include its sha1sum in the version string.
BUG=chrome-os-partner:54101
BRANCH=none
TEST=make buildall; try on Cr50 hardware
Before
> version
Chip: g cr50 B2
Board: 0
RO_A: * 0.0.9/0088a3eb
RO_B: 0.0.3/8fe06b9e
RW_A: * 0.0.6/DEV/cr50_v1.1.5333-cca986c
RW_B: 0.0.6/DEV/cr50_v1.1.5334-115b338
Build: 0.0.6/DEV/cr50_v1.1.5333-cca986c
private-cr51:v0.0.87-24457f2
tpm2:v0.0.264-5e5aaa3
cryptoc:v0.0.4-5319e83
2016-09-16 21:59:31 wfrichar@wintermute.mt
>
After
> version
Chip: g cr50 B2
Board: 0
RO_A: * 0.0.9/0088a3eb
RO_B: 0.0.3/8fe06b9e
RW_A: 0.0.6/DEV/cr50_v1.1.5333-cca986c
RW_B: * 0.0.6/DEV/cr50_v1.1.5334-36b2cee
Build: 0.0.6/DEV/cr50_v1.1.5334-36b2cee
tpm2:v0.0.264-5e5aaa3
cryptoc:v0.0.4-5319e83
2016-09-19 17:48:17 wfrichar@wintermute.mtv.corp.google.com
>
Change-Id: I785dff86e6b970219da87c8674f2a324fa074987
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/387238
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
We often find it handy to build test images that are unlocked or
have special powers. To avoid confusing these with production
images, this adds a "DEV/" to the version string:
"make BOARD=cr50" looks like this:
> version
Chip: g cr50 B2
Board: 0
RO_A: * 0.0.9/0088a3eb
RO_B: 0.0.8/710d4375
RW_A: * 0.0.6/cr50_v1.1.5261-4848d7e
RW_B: 0.0.6/cr50_v1.1.5261-4848d7e
[...]
"CR50_DEV=1 make BOARD=cr50" looks like this:
> version
Chip: g cr50 B2
Board: 0
RO_A: * 0.0.9/0088a3eb
RO_B: 0.0.8/710d4375
RW_A: 0.0.6/cr50_v1.1.5261-4848d7e
RW_B: * 0.0.6/DEV/cr50_v1.1.5261-4848d7e
[...]
BUG=chrome-os-partner:55557
BRANCH=none
TEST=make buildall; also..
Build both with and without the CR50_DEV=1 environment variable.
Observe that the version string differs even if nothing else
does.
Change-Id: Ifee9fbf922c2bbb40a1a9d0a716d2d11aa0d3ec2
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382851
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
We don't really have the ability to build the latest signer yet, but
this should not stop us from being able to build a properly signed
image using the ec makefiles.
As a stopgap measure the suggestion is to keep the latest signer
binary in ~/bin/codesigner in chroot, then with this patch applied
invoking make with CR50_DEV=1 will cause the proper sighner used and
proper signing procedure followed.
The signed targets need to be built in series to avoid concurrent use
of the signer fob, an addition dependency is being added to enforce
that.
BRANCH=none
BUG=chrome-os-partner:55557
TEST=ran make as follows:
CR50_DEV=1 make BOARD=cr50
touched the fob when requested, uploaded the generated
build/cr50/ec.bin on a kevin-tpm2 using usb_updater, and observed
it boot properly with the new version.
Change-Id: Ia9494bdc60b4bd3b8e5e09cbcbd8b27409c739d2
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/376885
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
To be able to parse binary panicinfo from feedback reports, we need
a host tool:
- Move panicinfo generic parsing functions to a separate C file
- Create a new host utility to parse panicinfo
BRANCH=none
BUG=chromium:643062
TEST=base64 -d | ec_parse_panicinfo
Change-Id: Idd8560a2894f270d0ab3a9f654c333135759e57f
Reviewed-on: https://chromium-review.googlesource.com/379639
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Record what current limit we set when we act as a source
and when we are changing it.
The change should be backward-compatible as older EC will return 0 in
`current_max` when their role is PD_ROLE_SOURCE while newer firmware
will set the actual limit.
BRANCH=none
BUG=chrome-os-partner:56110
TEST=manual: on Kevin, plug and unplug various devices on the 2
ports, and dump the values with 'ectool usbpdpower'.
Change-Id: I8e78663f3196b1b81c2235ed8642da0638bed649
Reviewed-on: https://chromium-review.googlesource.com/375918
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When flashing a servo v4, the function will try to initiate a cold_reset
but that interface does not exist for a servo v4. Add in a check for
cold_reset before trying an ec_reset to prevent printing the useless
error message 'No control named "cold_reset"'.
BRANCH=None
BUG=None
TEST=flashed and did not see error message anymore.
Change-Id: I6086883f002b4961807ae0663b0ee32aea4c63d8
Reviewed-on: https://chromium-review.googlesource.com/365151
Commit-Ready: Kevin Cheng <kevcheng@chromium.org>
Tested-by: Kevin Cheng <kevcheng@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
sweetberry is an stm32f446 based power monitoring
board, with 48 channels of INA current sense chips
BUG=chromium:608039
TEST=boots
BRANCH=none
Change-Id: If263bcee3a648ba3605f991999d481b7a0e2a1db
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/370718
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
This adds basic support for the stm32f446.
This consists of:
* New DMA model for stm32f4
* New clock domain support.
* MCO oscillator gpio export support.
* Flash support for irregular blocks.
BUG=chromium:608039
TEST=boots w/ correct clock, stm32f0 also boots.
BRANCH=None
Change-Id: I1c5cf6ddca09009c9dac60da8a3d0c5ceedfcf4d
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363992
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Allow the host to self-report its sleep state through
EC_CMD_HOST_SLEEP_EVENT, which will typically be sent with SUSPEND
param when the host begins its sleep process. While the host has
self-reported that it is in SUSPEND, don't assert the interrupt
line, except for designated wake events.
BUG=chrome-os-partner:56156
BRANCH=None
TEST=On kevin, run 'ectool hostsleepstate suspend', verify that
interrupt assertion is skipped for battery host event. Run 'ectool
hostsleepstate resume' and verify interrupt is again asserted by the
battery host event.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I74288465587ccf7185cec717f7c1810602361b8c
Reviewed-on: https://chromium-review.googlesource.com/368391
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
If an HPD IRQ event is seen, make note of it and keep the status set
until informing the host.
BUG=chrome-os-partner:55925
BRANCH=None
TEST=Manual on kevin, trigger HPD event, verify that event bit is set in
reply to first host command and not subsequent host commands.
Change-Id: I0900a683dcb344d5d4d03a1fa6e3d8de913597b2
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366990
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
The recent addition of the multicomponent version string for cr50,
requires further tweaking of the version generating script. In
particular, the CROS_EC_VERSION32 variable used by the "verson" cli
command is not supposed to include any information about subcomponents
of the image, it should reflect the EC version only.
Separating everything after the first space accomplishes that.
BRANCH=none
BUG=chrome-os-partner:55373
TEST=verified that RO_x and RW_x versions are printed properly:
> vers
Chip: g cr50 B2
Board: 0
RO_A: 0.0.1/84e2dde7
RO_B: * 0.0.3/8fe06b9e
RW_A: cr50_v1.1.4992-7c9f891+ private
RW_B: * cr50_v1.1.4989-52b3cc6+
...
Change-Id: I192eb29816dfa963b08aa97f749b978b1367d6b7
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364490
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The cr50 code comes from four different repositories. This patch
introduces an array of the repositories where version information is
supposed to come from.
For all boards but cr50 this array includes just the local repository,
for cr50 the array is extended with the three other components.
This patch also allows to change the 'tree dirty' marker appended to
the sha1s of the 'dirty' trees, having a shorter marker helps to keep
multicomponent version strings shorter.
All external component's version information in the generated combined
version string is prepended by the component's root directory name.
BRANCH=ToT
BUG=chrome-os-partner:55373
TEST=ran the script for two EC boards, kevin and cr50, verified the
output:
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
$ BOARD=kevin ./util/getversion.sh
/* This file is generated by util/getversion.sh */
/* Version string for use by common/version.c */
/* Version string, truncated to 31 chars (+ terminating null = 32) */
/* Sub-fields for use in Makefile.rules and to form build info string
* in common/version.c. */
/* Repo is clean, use the commit date of the last commit */
$
$ BOARD=cr50 ./util/getversion.sh
/* This file is generated by util/getversion.sh */
/* Version string for use by common/version.c */
/* Version string, truncated to 31 chars (+ terminating null = 32) */
/* Sub-fields for use in Makefile.rules and to form build info string
* in common/version.c. */
/* Repo is clean, use the commit date of the last commit */
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
then introduced some local changes in the ec and tpm2 directories and
ran the script again. Note the '+' used as the 'dirty' marker in the
cr50 string:
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
$ BOARD=kevin ./util/getversion.sh
/* This file is generated by util/getversion.sh */
/* Version string for use by common/version.c */
/* Version string, truncated to 31 chars (+ terminating null = 32) */
/* Sub-fields for use in Makefile.rules and to form build info string
* in common/version.c. */
/* Repo is dirty, using time of last compilation */
$
$ BOARD=cr50 ./util/getversion.sh
/* This file is generated by util/getversion.sh */
/* Version string for use by common/version.c */
/* Version string, truncated to 31 chars (+ terminating null = 32) */
/* Sub-fields for use in Makefile.rules and to form build info string
* in common/version.c. */
/* Repo is dirty, using time of last compilation */
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Change-Id: I4b4ec23ce003970c09442e8d8aeed2306d4e5dd8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363917
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
It is necessary to collect information about more then one git
repositories status for the cr50 board. To facilitate this, separate
the code retrieving build version information into a function,
get_tree_version().
The function returns a two element string, the version information and
the 'dirty' marker in case the tree has any uncommitted changes. The
0x01 character is used to join the elements of the string, which makes
it easier to split the string when processing it.
BRANCH=ToT
BUG=chrome-os-partner:55373
TEST=ran the script before and after changes, observed that generated
output is identical.
Change-Id: I2c211cbda8c3cab3c8c21b4430e4b3102691e74a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362849
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When a kevin, gru, or reef are attached to the host machine using a
suzyQ, they can use CCD to update the AP or EC using flashrom. To use
suzyQ you have to specify raiden_debug_spi as the flashrom programmer.
This change adds support to flash_ec for using the right programmer to
update with CCD over suzyQ instead of servo.
BUG=chrome-os-partner:50701, chrome-os-partner:50712
BRANCH=none
TEST=make sure "util/flash_ec --BOARD=kevin --raiden" updates the EC
when CCD is enabled
Change-Id: Ie63337b9689c68aa60163d7e54c5ebefa97b4e21
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344427
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If the EC has CONFIG_HOSTCMD_RTC set to 'y', then export this via the
features host command. The kernel can then use this feature to expose
an RTC device under /dev/rtc*.
Signed-off-by: Stephen Barber <smbarber@chromium.org>
BRANCH=none
BUG=chrome-os-partner:54639
TEST=`ectool inventory` shows RTC on kevin
Change-Id: I644c8e61c4d9f691cc6ca94ef60bee4384c21660
Reviewed-on: https://chromium-review.googlesource.com/359414
Commit-Ready: Stephen Barber <smbarber@chromium.org>
Tested-by: Stephen Barber <smbarber@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Currently, it is assumed the host will sooner or later retrieve the
events from the sensor ring: It is only used by Android and the sensor
HAL is enabling the ring buffer at boot.
But if nobody processes the ring, and the ring is almost full, the EC will
generate interrupt for every new events.
This can happen with ARC, where events generated for ChromeOS
will be in the ring but nobody will process them until Android is
started.
Add a command to allow sending ring MKBP events. It will be used when
the IIO ring buffer is enabled / disabled.
It also can be used for preventing raising interrupt when the device is
about to go to sleep.
BRANCH=ryu,cyan
BUG=b:25425420,b:27849483
TEST=Check with fiforead that no events are queued when IIO ring
buffer is disabled.
Check with ectool and androsensor that interrupt generation stops.
Change-Id: Ibc85eed2e0eae3a9ec07d191e692118bc2fd0dab
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356689
For designs where the host SOC is responsible for setting the USB-C SS
mux, the EC must track the desired mux state and inform the host when
the desired state changes. Then, the host must ask the EC for the new
desired state and set the mux accordingly.
BUG=chrome-os-partner:52639
BRANCH=None
TEST=Manual on gru with subsequent commit.
Attach USB dongle in port 1 and DP dongle in port 0, then verify `ectool
usbpdmuxinfo` output:
Port 0: DP
Port 1: USB
Flip DP dongle and verify output changes:
Port 0: DP INV
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6a99ce93a76c3197f9195cfaa25c5217d09aeb75
Reviewed-on: https://chromium-review.googlesource.com/355281
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This updates the lockfile path for FHS 3.0 since powerd as well
as other pieces of software are migrating over.
BUG=chromium:616620
CQ-DEPEND=CL:351271
BRANCH=none
TEST=compiled
Change-Id: I6aa5fa30225e45039316e4a3af0e50cdef0fdf4e
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351345
Reviewed-by: Dan Erat <derat@chromium.org>
Adding ability to get # seconds before rtc alarm
goes off.
BUG=chrome-os-partner:52218
BRANCH=None
TEST=ectool rtcgetalarm w/o setting returns
Alarm not set.
ectool rtcsetalarm 30; ectool rtcgetalarm
to make sure counting down to 0. After alarm
goes off, rtcgetalarm should return alarm not
set again.
rtcsetalarm 30; rtcgetalarm to check alarm is set.
rtcsetalarm 0; should disable alarm. Use
rtcgetalarm to ensure that alarm is disabled.
Change-Id: I176b12fe2dda08eedd23ea33dc64785f09f1d9ae
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353331
Reviewed-by: Shawn N <shawnn@chromium.org>
This commands makes it possible to control the PD chip (or
the interaction between EC and PD), from the AP.
- PD_SUSPEND: Suspends the PD chip: EC needs to stop talking
to PD chip. Useful at beginning of PD FW update.
- PD_RESUME: Resumes the PD chip: EC can start talking to PD
chip again. Useful at end of PD FW update.
- PD_RESET: Resets the PD chip (called at the end of the update).
- PD_CONTROL_DISABLE: Prevents further calls to this command
(for security reason, we do not want the AP to be able to
call the other subcommands after the update has been performed).
BRANCH=none
BUG=chrome-os-partner:52433
TEST=ectool pdcontrol {suspend,resume,reset,disable}
Change-Id: I7a955dd27b65086c21d195a6504aa7392eb0406d
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342584
Reviewed-by: Randall Spangler <rspangler@google.com>
This adds a fallback directory in case SYSTEM_LOCKFILE_DIR is
unavailable. Since this is a band-aid meant to help older systems
auto-update, the fallback path is hardcoded to "/tmp" as to avoid
polluting the overall lockfile API.
BUG=chromium:616620
BRANCH=none
TEST=Tested on veyron_jaq by removing /run/lock and seeing
mosys, flashrom, and ectool run successfully with
firmware_utility_lock in /tmp.
Change-Id: Idbe63a574474ec35a5c3b6fe2b0fb3b672941492
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348850
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Only way to set alarm previously was through
rtcalarm command on EC console. Implemented
interface through ectool so that the AP can set
it as well.
BUG=chrome-os-partner:52218
BRANCH=None
TEST=from AP console, run ectool rtcalarm <sec>
Should see [event set 0x02000000] from EC
console in approximately <sec> seconds.
Change-Id: I3202b826cb994dbca456b8b9c22bbca4dbe2766a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347493
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
ec_readmem_dev_v2() was copy/pasted from ec_readmem_dev(), but we forgot
to switch over the fallback 'fake_it' case to the new ioctl format. This
case is used over transports like SPI, which don't implement
cmd_readmem.
BUG=none
TEST=run `ectool version` on kevin (with cros-ec-spi) and don't see:
ioctl -1, errno 25 (Inappropriate ioctl for device), EC result 255 (<unknown>)
BRANCH=none
Change-Id: I4335f8fc3d43169cf628e26cadf1ac8d263955f2
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347111
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Reviewed-by: Stephen Barber <smbarber@chromium.org>
This allows the AP to protect a I2C passthru bus. A board-specific
function then defines what I2C commands are allowed, so that we
can white/black list some addresses (e.g. I2C address allowing
PD chip FW updating).
BRANCH=none
BUG=chrome-os-partner:52431
TEST=Book elm-rev1
Change-Id: Ib106924418b16388ea8ea53c7b6bda6ef92e1d09
Signed-off-by: Nicolas Boichat <drinkcat@google.com>
Reviewed-on: https://chromium-review.googlesource.com/345761
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@google.com>
This adds the basic framework for Reef including full GPIO listing,
board config file, and rudimentary functionality. It has not been
fully tested and still has several TODOs/FIXMEs. For now we just need
something that will build and can be incrementally improved.
BUG=chrome-os-partner:53035
BRANCH=none
TEST=EC and AP both boot, seems reasonably stable for now
Change-Id: I4934ad00917e251dd1d7eb759207a92c45a36136
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/339292
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add generic PWM host commands for setting + getting duty cycle. PWMs can
be controlled through index (board-specific meaning) or by type
(currently KB backlight and display backlight are supported, more can be
added as needed).
BUG=chrome-os-partner:52002
BRANCH=None
TEST=Manual on chell.
`ectool pwmsetduty kb 100` - Verify KB backlight goes to 100%
`ectool pwmgetduty kb` - Prints 100
`ectool pwmgetduty 0` - Prints 100
`ectool pwmsetduty 0 0` - Verify KB backlight goes to 0%
`ectool pwmgetduty kb` - Prints 0
`ectool pwmgetduty disp` - Error res 3 (unsupported PWM type)
`ectool pwmsetduty 1` - Error res 3 (non-existent PWM index)
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I607c92a291e6c2e3af8238eaf22ad2bb81ffc805
Reviewed-on: https://chromium-review.googlesource.com/344012
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Some reason cause the power off during battery fw update process.
Then execute the process again, tool can't detect AC because EC
can't read data from battery. So set AC_PRESS flag after check
battery is in battery fw update mode.
BUG=None
BRANCH=None
TEST=check the battery can execute fw update in this case.
Change-Id: Iafe501eb1719a12425d5cac42d27c897e078acc1
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/341044
Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com>
Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
CROS_EC_DEV_IOCRDMEM must be used on architecture where legacy IO mapped
registers are accessed inderectly via EMI. The kernel is taking care of
the translation.
TEST=Check on reks that we need to use the IOCTL.
BUG=chrome-os-partner:52550,chromium:602832
BRANCH=none
This reverts commit de45353bbd ("ectool: Remove CROS_EC_DEV_IOCRDMEM").
Change-Id: I8efad56df90c58c25bdc9ccd70a508547e629a77
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/340348
Reviewed-by: Shawn N <shawnn@chromium.org>
On !LPC EC, we can read memory via CROS_EC_DEV_IOCXCMD ioctl,
using command EC_CMD_READ_MEMMAP.
On platform that supports direct memory access (lpc), we access
the memory directly, bypassing the ioctl.
BUG=chromium:602832
TEST=On gnawty and veyron, check 'ectool battery' works.
Verify that gnawty use io mapped registers.
BRANCH=none
Change-Id: I9bfcddcf450bf8df63ead78e1df97dd7392289e6
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338853
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Elm is an oak variant that uses ANX7688 PD port controller. This CL sets
PD port count to 1 and modifies TCPC I2C address to 0x50.
Other elm changes are included in this change:
- add 2 KX022 motion sensors, remove BMI160
- remove ALS
- LED configuration changed to 2 bi-color LEDs
- remove pi3usb30532
- add ANX7688 mux driver
- change PD interrupt polarity
BRANCH=none
BUG=none
TEST=manual
make BOARD=elm -j
load and test on elm proto
Signed-off-by: Rong Chang <rongchang@chromium.org>
Change-Id: I8ad02da9acade985bc0e7e2f85d9e58db7e6b38d
Reviewed-on: https://chromium-review.googlesource.com/331453
Reviewed-by: Shawn N <shawnn@chromium.org>
Support both old and new ioctl formats at the same time.
Auto-detect the ioctl format used by the kernel.
BUG=chromium:481710
BRANCH=None
TEST=Work on Samus with kernel 4.4 and 3.8/3.14/3.18
Change-Id: I31d7ce5b517b4b5af8e2b617e386c3cfd3276f20
Signed-off-by: Guenter Roeck <groeck@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/331830
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
This is keyboard test mechanism request for "multiple key press test",
we can thru the testing to scan out kso ksi pins shortting or keyboard has
multiple key pressing, below was the testing steps:
1. Turn off internal keyboard scan function.
2. Set all scan & sense pins to input and internal push up.
3. Set start one pin to output low.
4. check other pins status if any sense low level.
5. repeat step 3~4 for all keyboard KSO/KSI pins.
6. Turn on internal keyboard scan function.
BUG=chrome-os-partner:49235
BRANCH=ToT
TEST=manual
Short any KSO or KSI pins and excute "ectool kbfactorytest", it shows failed.
if no pins short together, it shows passed.
Change-Id: Id2c4310d45e892aebc6d2c0795db22eba5a30641
Signed-off-by: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/332322
Reviewed-by: Shawn N <shawnn@chromium.org>
