Match ec_commands.h, adding new type and sensors.
BUG=none
BRANCH=reef
TEST=Check on Reef that barometer sensor info is displayed properly.
Change-Id: I257f5161e5f57be562a2b3a29442b49f47f3fc89
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394749
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When the kernel reads sensor data via LPC, it expects the order to be:
- ACCEL
- ACCEL
- GYRO
(other sensors data are read through EC commands)
BMI160 expects ACCEL, GYRO and MAG to be next to each other.
Reorganize motion_sensor array to fit these 2 requirements:
If BMI160 in the lid:
- BASE_ACCEL
- LID_ACCEL
- LID_GYRO
...
If BMI160 in the base:
- LID_ACCEL
- BASE_ACCEL
- BASE_GRYO
...
BUG=none
BRANCH=amenia,reef,wheatley
TEST=On reef, check the sensor data pull directly by the AP (for chrome
for lid angle) is correct. Check ARC++ works are expected.
Change-Id: If9477be0de44472e38a057c0b8533cb54acee220
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394751
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
From the specs, "KX022-1020 Specifications Rev4.0", the power up time
can be as long as 10ms.
Add a loop to be sure the device is responsive before initalizing it.
BRANCH=reef,glados,oak,veyron,cyan
BUG=none
TEST=After putting a KX022 accel as first in the list, it would not
initialize properly. After adding the loop, it initializes properly.
Change-Id: I3194a5d1deb0c2eb2a04a459aab3b4269e479af3
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394750
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The new extension command is used to request device reset after a
successful update when communicating over SPI.
tpm_send_pkt() is being refactored to allow passing of different
extension commands.
BRANCH=none
BUG=chrome-os-partner:58226
TEST=verified that the system gets reset and the new image version
kicks in on both gru (over SPI) and reef (over USB).
Change-Id: I02f3ef76fc4b4ee1e52dedb9cb538e072638257a
Signed-off-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/395629
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
While USB updates have a mechanism to trigger the target reset, SPI
updates do not have it.
This patch adds an extension command to cause the device reset.
BRANCH=none
BUG=chrome-os-partner:58226
TEST=with the rest of the patches applied verified that the system
gets reset and the new image version kicks in on both gru (over
SPI) and reef (over USB).
Change-Id: I498538670e2c43d17b13510288eb9ae75eb7b761
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/395628
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Usually CR50 TPM reset happens when the AP reboots, the CR50 RO does
not get a chance to run in this case, so the running RW does not
change either,
Once the idle RW section was updated, the only way to start it is to
reboot the CR50 completely, Rebooting CR50 causes the whole system
reset, so it should not be happening at random moments in time.
This patch introduces a mechanism to delay reboot to the moment when
the TPM is reset. The reboot request would be posted in the end of the
update, and then the AP would reboot, triggering a TPM reboot, which
in turn would trigger the CR50 reset.
The USB update handler now posts the reboot request instead of
triggering the reboot immediately.
BRANCH=none
BUG=chrome-os-partner:58226
TEST=with the rest of the patches applied verified that the system
gets reset and the new image version kicks in on both gru (over
SPI) and reef (over USB).
Change-Id: Iff859f2e7a48c5035a27fffd17aefe7e318af569
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/395627
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When we are using MKBP in LPC mode, user event are not sent over MKBP.
Therefore, we can remove host_get_next_event, it will never been called.
BUG=none
BRANCH=none
TEST=compile
Change-Id: Ia6de611291648bd3f394a20b02072b1787cca7ac
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394069
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Interrupt test checks whether DUT can be interrupted by an interrupt
and an interrupt handler can be invoked as expected.
Note the previous interrupt test ported from test/interrupt.c runs in
an emulated environment on the host, thus does not test the real
interrupt capability of the chip.
BUG=chromium:653195
BRANCH=none
TEST=Run cts.py -m interrupt
Change-Id: I21cecff07594f048633d1c1b699fb3a1876379e0
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363943
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The current implementation of the ecrst and sysrst commands don't
have a way to show the state of the EC_RST_L and SYS_RST_L.
This tweaks the commands to accept an optional "pulse" argument
in addition to the boolean arg, which will assert, pause, then
deassert the relevant signal. With no args at all, the current
signal state is shown.
BUG=chrome-os-partner:58123
BUG=chrome-os-partner:56835
BRANCH=none
TEST=manual
sysrst pulse resets the AP
sysrst on/off asserts/deasserts SYS_RST_L
sysrst displays the current SYS_RST_L state
ecrst pulse resets the EC (and AP)
ecrst on/off asserts/deasserts EC_RST_L
ecrst displays the current EC_RST_L state
Change-Id: I8e1c9a577afd9ed9e770f1b3f5c0a69e4607de66
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/395587
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Make sure that ioexpander is set to output,
and that the uservo usb power enable is set.
BUG=chromium:651860
TEST=check that servo micro is initialized properly
BRANCH=None
Change-Id: Iff994c63cd333933d51db38202a41b7b6fc86d66
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/395186
Reviewed-by: Kevin Cheng <kevcheng@chromium.org>
The EC firmware already has a default sysinfo command, but it's
not relevant for Cr50 and is disabled. This CL adds a sysinfo
command that IS relevant to the Cr50.
BUG=none
BRANCH=none
TEST=make buildall; try on Gru
> sysinfo
Reset flags: 0x00000800 (hard)
Chip: g cr50 B2
RO keyid: 0x3716ee6b
RW keyid: 0xb93d6539
DEV_ID: 0x017a30b0 0x04656742
>
Change-Id: I251f86c1192aee373f1399ea4146ad355c592861
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/395567
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The sysjump capability is not used in Cr50 (it either does
nothing or causes a hard reboot), so just disable these commands.
BUG=none
BRANCH=none
TEST=make buildall; test on Gru
Build with and without CR50_DEV=1, confirm that these commands
aren't present.
Change-Id: Idf882f10a2f750ac0d04cb3d35bb1d6f45cb6cee
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/395566
Reviewed-by: Randall Spangler <rspangler@chromium.org>
BMI160 driver assumes accel, gyro, compass are next to each other.
It was also assuming accel was sensor 0, which is wrong.
BUG=none
BRANCH=glados
TEST=On Cave, check sensors 1 (accel) and 2 (gyro) are working properly.
Change-Id: I37402e1d48070caaecbd7e32bbf53754616ee8cb
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394067
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
BMI INT2 can be input or output.
It is not used currently, but configure it properly nevertheless.
BUG=none
BRANCH=none
TEST=On cave, (int2 is output), ensure FIFO headers are free of
interrupt information.
Change-Id: I9c058689a8676593aad542e33601cc11da105838
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394066
The keyid field of struct SignedHeader is what distinguishes prod
keys from dev keys. This may be useful someday, so let's have the
update protocol return those values for the active RO and RW
images.
Bump the UPGRADE_PROTOCOL_VERSION accordingly.
Note: This doesn't enforce any keyid matches, it just returns the
current values as part of the initial upgrade handshake in case
we want to know.
BUG=chrome-os-partner:57956
BRANCH=none
TEST=make buildall; try on Gru
Make sure that Cr50 can be freely updated and downgraded between
firmwares that speak either v4 or v5 of the protocol, by using
the v5-aware usb_updater tool.
And of course, make sure that v5 images report their keyids. Duh.
Change-Id: If2cc0d4023dca2078b9398fd899618dc2cd409b9
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394732
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The sysinfo and syslock commands aren't needed by all boards that
compile common/system.c, so let's make them individually
selectable.
BUG=none
BRANCH=none
TEST=make buildall; try on Gru
Confirm that by default these commands are still present
everywhere that they were before (since they're #defined by
default). Also confirm that it's possible to #undef them and
still build.
Change-Id: I7a5d21d1f0b9887f3562b9410063616ed8f41163
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/395366
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Every time I run "cat PRESUBMIT.cfg" to see what's in here, it
annoys me that there's no newline at the end. This adds one.
BUG=none
BRANCH=none
TEST=make buildall
Just adding whitespace; no functional change.
Change-Id: I7629312c987696fd6c7bbc986ad63222186729c0
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/395347
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reset-on-hibernate wake performs a soft-reset, which re-initializes GPIO
states to ROM POR values. Therefore, it is necessary to re-init GPIO
states once again based on board-level GPIO settings.
BUG=chrome-os-partner:58077
BRANCH=gru
TEST=Run `hibernate` on gru, wake, then run `bd99955_dump`. Verify
actual register values are printed rather than zeros.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ib3eb1dd6aa264d00d42d8e386bfd1ef7f6cf7717
Reviewed-on: https://chromium-review.googlesource.com/395426
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
With the recent modification of the tpm reset processing the only way
to get the cr50 restart is to reset it internally.
Make sure that usb_updater triggers the cr50 reset in the end of the
update.
BRANCH=none
BUG=none
TEST=with the corresponding init script changes the update on reef
happens as expected.
Change-Id: Ib49b81c4ef6d12d0b877a8a63493cf4d6d5aaeb0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394255
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The previously added '-b' command line option was left out from the
help message. This patch fixes it.
BRANCH=none
BUG=none
TEST=verified that -b command line option description is included in
the help message.
Change-Id: I71117a8653ae5094fd0bf3909c8715d6ec25259d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394254
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Recent tpm2 repository changes introduced more strict checks of the NV
RAM operations' return status. The problem is that in case TPM is not
manufactured tpm_endorse() is invoked before nvram is declared
available, and this causes endorsement operation failure.
Make sure NVRAM initialization is complete before endorsement is
attempted.
BRANCH=none
BUG=none
TEST=tpm manufacturing now succeeds again.
Change-Id: I2217f33915ab8b4d872a9498def6d6862f4b1913
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394129
Tested-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
This change adds apreset, ecreset, ec_rst, sys_rst and powerbtn options
to the ccd console command.
BUG=chrome-os-partner:58123
BUG=chrome-os-partner:56835
BRANCH=none
TEST=manual
sysrst resets the AP
sysrst on/off controls SYS_RST_L
ecrst resets the ec
ecrst on/off controls EC_RST_L
powerbtn 500 will simulate a power button press for 500 ms
Change-Id: I89adc88eb407730c9d57811a07bfef8fcf63c5b9
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/393809
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This patch adds CTS_RC_TIMEOUT, which is returned when test
encounters some sort of timeout.
BUG=none
BRANCH=none
TEST=Run cts.py -m i2c. Make buildall
Change-Id: I6d5cbcdde40f24e797e795f30f002da7621d089e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/393330
Reviewed-by: Randall Spangler <rspangler@chromium.org>
BUG=none (similar to chrome-os-partner:56765, though)
BRANCH=none
TEST=flashrom's "--flash-name" shows SPI chip info instead of EC info
on reef
Change-Id: I1090dd5d4079ff94201fce9fd3e03a384eb3cb7b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/392349
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch moves I2C_MAX_HOST_PACKET_SIZE to include/i2c.h. It's currently
used only by i2c-stm32*.c but should be commonly available for other chips.
It also moves i2c_get_protocol_info to common/i2c.c for the same reason.
BUG=none
BRANCH=none
TEST=make runtest
Change-Id: I28d8bca0167bb7b2ce99574601a6efb62fc20eca
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/393328
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch fixes the error messages displayed when a UART port connected
to DUT or TH is being occupied.
BUG=none
BRANCH=none
TEST=run cts.py -m i2c
Change-Id: I3fbb4068e8ee3af7a1b04f70ae70b3d870a19d2e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/393327
This change makes cts.py fail when building or flashing a module for
DUT or TH fails.
BUG=none
BRANCH=none
TEST=Made cts.py fail by injecting build and flash error
Change-Id: Iec1e11f4a8c261eb4c989b118df218e86cb6f5f1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/393326
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Due to an error in ms_command_sizes, fifo_info command
would fail when lost vectors are present:
packet too long (16 bytes, expected 10)
Reorder ms_command_sizes commands properly.
Get the number of sensors present before printing the number of lost
vectors per sensor.
BUG=none
BRANCH=none
TEST=On cave (with broken MKBP support), check fifo_info
is returning the lost vectors count.
Change-Id: Ic745eb762563705372d8a670ce34eab15e188bf9
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/391887
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
virtual_battery_read() returns a cached value for some of the supported
smart battery parameters. If a value isn't supported, it calls out to
the actual battery. In the case of a battery that's not present, but a
supported battery parameter is queried, we would still return
_something_. This seems to confuse powerd and causes slow boot.
This commit changes the i2c passthru command to return a NAK when the
virtual battery is enabled but the battery is not present.
BUG=chrome-os-partner:55954
BRANCH=gru
TEST=Build and flash kevin. Unplug battery. Verify boot is nice and
quick.
Change-Id: Ib3ab768504c29904f01b91e6194a9689bfdb1e1e
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/392926
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit b5eb2d93820c9e1a162cb1b390b3563bf9effcd5)
Reviewed-on: https://chromium-review.googlesource.com/393187
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
spi_transaction() can be called from motionsense, hooks, hostcmd,
console, and chipset tasks, so add a mutex to ensure an in-process
transaction isn't preempted by another transaction.
BUG=chrome-os-partner:57912
BRANCH=gru
TEST=On kevin, run "while true; do ectool motionsense odr 0 0; sleep 1;
ectool motionsense odr 0 1000000; sleep 1; done", verify watchdog crash
not encountered after 20 minutes.
Change-Id: I7ec495bab295dc03ce02372c20e5c7c5c196715d
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/391892
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit eabdea443775fab834aaabbb7afae871306c7530)
Reviewed-on: https://chromium-review.googlesource.com/392226
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
- changed the pad assignment for plt_rst_l from DIOA13 to DIOM3;
- removed the board property used to keep uart rx disabled, Uart0 is
now enabled by default on Cr50.
- removed resetting fallback counter on USB updates for reef boards,
they are going to use the same mechanism as kevin and gru.
BRANCH=none
BUG=chrome-os-partner:56540
TEST=Tested on Reef Board ID 1 and Gru Board ID 1. Verfied that
plt_rst_l signal is being detected and that there are no
interrupt storms related to not having a pullup resistor on the
uart rx line. Verified that both platforms successfully boot into
chrome OS using cr50 TPM.
Change-Id: I300a0c75e60acbecf93500b46aced303955a192a
Signed-off-by: Scott <scollyer@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/391140
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
In preparation to the new CR50 image release bump up the minor version
number to trigger autoupdate on the devices in the field.
BRANCH=none
BUG=none
TEST=none
Change-Id: I7744b8cb8436d9134ee5900b352487a1cdddcd28
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/392447
When tpm is reset the i2c slave interface initialization function is
called, but it does not quite re-initialize the interface.
This patch adds both a hardware pulse to make sure that the i2c slave
interface state machine is set into the initial state, and code to
zero static variables of the driver.
BRANCH=none
BUG=none
TEST=with the change on the AP firmware side which prevents losing i2c
ready interrupts early in the process tpm reset became much more
reliable. Resetting from EC, AP of cr50 consoles reliably
restarts reef without any TPM communications problems.
Change-Id: I604607c32d4dfc554b245d3d3d82b9ad38271962
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/392306
Reviewed-by: Scott Collyer <scollyer@chromium.org>
This removes some console commands that shouldn't be present in
production builds, even when the console is unlocked.
BUG=chrome-os-partner:57408
BRANCH=none
CQ-DEPEND=CL:391045
CQ-DEPEND=CL:391188
CQ-DEPEND=CL:391244
CQ-DEPEND=CL:391314
CQ-DEPEND=CL:391611
CQ-DEPEND=CL:391612
CQ-DEPEND=CL:391613
CQ-DEPEND=CL:391614
CQ-DEPEND=CL:391127
TEST=make buildall; try on Gru with and without CR50_DEV=1
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: Ic5034a87ba032b14a7e613e6debdbb635a7c1c9a
Reviewed-on: https://chromium-review.googlesource.com/391046
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit 9e7c12b added a command-line option to "make" to build
development versions of the Cr50 board. This makes the symbol
definition useful in makefiles and not just C code.
BUG=chrome-os-partner:57408
BRANCH=none
TEST=make buildall; try on Gru with and without CR50_DEV=1
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: Id0719d63263b00e192a2e4866dbe1551ae49e23c
Reviewed-on: https://chromium-review.googlesource.com/391127
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The application may need to read/write/erase the flash memory,
but we not want console users to do so. This CL adds
CONFIG_FLASH_PHYSICAL, which allows the higher-level CONFIG_FLASH
to be undefined while still providing the chip-specific
flash_physical_* accessor functions.
There aren't many board.h files that needed changes, since
CONFIG_FLASH_PHYSICAL is enabled by default, just like CONFIG_FLASH.
BUG=chrome-os-partner:57408
BRANCH=none
TEST=make buildall; try on Gru with and without CR50_DEV=1
See that it still boots, updates, wipes, restores, etc. without
linking common/flash.o in the production image; and that the
flash commands are still there in the dev build.
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: I7eb1bbcb414b1c70ee427c4fcb5cea899dbb9e93
Reviewed-on: https://chromium-review.googlesource.com/391188
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
We have a large number of config.h options to enable/disable
specific console commands. This adds a few more that we will want
to control.
BUG=chrome-os-partner:57408
BRANCH=none
TEST=make buildall; try on Gru with and without CR50_DEV=1
Change-Id: Id41f0e9f44fc77feaf56853f357a6b33bb685b0c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/391614
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We have a bunch of options to enable/disable individual console
commands, but they're not quite sorted. Now they are.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I186b9f82dc40c2f9fc66f493b4b6cccda020224c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/391613
Reviewed-by: Randall Spangler <rspangler@chromium.org>
And even that's a bit of a stretch. This entire endpoint will
probably be deactivated until it's more useful. In the meantime,
we can just leave the one little debug command for debug builds.
BUG=chrome-os-partner:57408
BRANCH=none
TEST=make buildall; try on Gru with and without CR50_DEV=1
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: Id4c185fe66d52fa49fcbee6a549df41d297c41af
Reviewed-on: https://chromium-review.googlesource.com/391045
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The rdd features are working (and it's better to test with
hardware anyway), so just delete this command.
BUG=chrome-os-partner:57408
BRANCH=none
TEST=make buildall; try on Gru with and without CR50_DEV=1
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: Ifcfc8c8a0e61a9fe31d28f0c96bcb50c3e2b93b5
Reviewed-on: https://chromium-review.googlesource.com/391314
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
It's possible the register values could be sensitive.
BUG=chrome-os-partner:57408
BRANCH=none
TEST=make buildall; try on Gru with and without CR50_DEV=1
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: Id3d4df3aaca116a638332f092d4727accd0cbbcd
Reviewed-on: https://chromium-review.googlesource.com/391612
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
All it does is show the AP/EC/Servo state
BUG=chrome-os-partner:57408
BRANCH=none
TEST=make buildall; try on Gru with and without CR50_DEV=1
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: I375be8e4d9c6f01aa90d0830da1927732740ed92
Reviewed-on: https://chromium-review.googlesource.com/391611
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
It could be used to sniff TPM commands.
BUG=chrome-os-partner:57408
BRANCH=none
TEST=make buildall; try on Gru with and without CR50_DEV=1
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: Ia2e11fb8e01002c2cf5e53b175e3e8b2741e4585
Reviewed-on: https://chromium-review.googlesource.com/391244
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
