This is required so that the kernel can enable/disable remote wake-up
capabilities, and in particular for the kernel to enable autosuspend.
Also, properly implement GET_STATUS.
BRANCH=none
BUG=b:35579996
TEST=echo auto > /sys/bus/usb/drivers/usb/X-Y/power/control, device
autosuspends after 2 seconds, and wakes on keypress.
Note that this introduces other bugs, where keys are missing,
repeated, see b/35775048.
Change-Id: I7ddd257ac3877d27fb2da813f20583a614a0169b
Reviewed-on: https://chromium-review.googlesource.com/450826
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The issue is with how we have the sys_rst_l wake pin setup. How it is
now, the gpio controller never sees that sys_rst_l is asserted, so it
can't tell when there is a rising edge.
sys_rst_l is a rising edge wake pin. Cr50 would enter sleep with
sys_rst_l high. While cr50 was asleep sys_rst_l would be asserted and
then deasserted. The rising edge would wake cr50 up, and when cr50 woke
up the gpio controller would see that sys_rst_l is still high, so it
wouldn't think there was an edge and it wouldn't trigger the tpm reset
interrupt.
This change makes sys_rst_l wake low instead of wake rising. This means
that cr50 will remain awake whenever sys_rst_l is asserted and it will
be awake to see the rising edge on sys_rst_l.
BUG=b:35774896
BRANCH=cr50
TEST=Turn off bob. Wait until cr50 enters regular sleep. Turn the device
back on and make sure it doesn't boot to recovery.
Change-Id: Ibee6c8112d32b3abb8953aa71d68e1f510932286
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450874
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reef RAM / code regions aren't a power of 2, so we cannot program MPU
to protect the regions we desire.
BUG=b:36037354
BRANCH=none
TEST=Boot to OS
Change-Id: I2d1e87eb97f9524620943262845823331f9f71a0
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450831
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit changes the behaviour of handling the CCD_MODE_L pin. When
Cr50 is not in CCD mode, it will stop driving the pin and turn it into
an input. This allows the pin to be driven by the EC. Cr50 will then
poll the CCD_MODE_L pin to see when it is pulled low and then enter CCD
mode. Once the pin is deasserted, CCD mode is disabled.
However, when Cr50 itself makes the decision to enter CCD mode, it
changes the pin from an input to an output and drives the pin low.
NOTE: The rdd interrupt does not directly trigger CCD mode, but now
drives the pin low. A side-effect of the pin going low is that CCD is
enabled. Once Cr50 decides to leave CCD mode, it then reconfigures the
pin to be setup as an input again.
CQ-DEPEND=CL:448988
BUG=b:35804738
BRANCH=cr50
TEST=Flash dev board, use `ccd` console command to both enable and
disable CCD. Verify that when CCD is enabled, the state of DIOM1 does
not disable CCD. Verify that when CCD is disabled, pulling DIOM1 low
enables CCD. Letting it float disables CCD.
TEST=Verify that CCD mode is reflected in the device state.
Change-Id: I44645f28b362977ca6a502b646e4f4ff1a7430c7
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/448161
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This is used for passing button information from EC to AP.
BUG=b:3577493
BRANCH=None
TEST=Verified using evtest that kernel is able to see button
press/release information.
Change-Id: Ifcad417c232c4e6e27e1024d2bed27133250fa07
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450937
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
We had disabled wakeups on the AP phy when we were running on gru,
because the AP phy was not in use. We never changed that for reef, so
UTMI wakeups were disabled even when the AP USB was supposed to be
enabled. After Cr50 went to sleep any usb transactions would drop bits,
because Cr50 wouldn't notice anything was happening until it woke up on
one of the HOOK_TICK events.
This change reenables UTMI wakeups on boards with AP usb. It writes 1 to
USB_PCGCCTL_STOPCLK. This makes the controller disable the PHY clock
whenever it detects a usb suspend. When it resumes out of suspend, this
bit has no effect.
BUG=b:35774906
BRANCH=cr50
TEST=Boot up reef. Wait until cr50 goes to sleep run 'usb_updater -f'
and verify that it runs successfully. Make sure deep sleep still works
Change-Id: I54bd866111b5c9b5738575f23757e0cbe4907ec4
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/448988
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
pdcontrol suspend command will be used to prevent tcpm from putting
the chip into sleep while firmware update is taking place. Currently
the command suspends or resumes port 0. This patch makes the command
apply to ports individually.
pd enable console command now takes a port number:
pd <port> enable/disable.
This patch also replaces CONFIG_USB_PD_COMM_ENABLED with _DISABLED.
When it's defined, PD communication is disabled at startup.
Plankton undefines CONFIG_USB_PD_COMM_ENABLED enable, intending to
disable PD communication at startup. Therefore, this patch defines
CONFIG_USB_PD_COMM_DISABLED in its board.h.
BUG=b:35586859
BRANCH=none
TEST=From AP console:
localhost # /tmp/ectool pdcontrol suspend 1
[600.188013 TCPC p1 suspended!]
> pd 1 state
Port C1 CC1, Dis - Role: SNK-UFP State: SUSPENDED, Flags: 0x0020
localhost # /tmp/ectool pdcontrol resume 1
[678.516613 TCPC p1 resumed!]
> pd 1 state
Port C1 CC1, Ena - Role: SNK-UFP State: DRP_AUTO_TOGGLE, Flags: 0x0020
From ec console:
> pd 1 disable
Port C1 disable
> pd 1 state
Port C1 CC1, Dis - Role: SNK-UFP State: DRP_AUTO_TOGGLE, Flags: 0x0020
> pd 1 enable
Port C1 enabled
> pd 1 state
Port C1 CC1, Ena - Role: SNK-UFP State: DRP_AUTO_TOGGLE, Flags: 0x0020
Change-Id: Ia0cc4904ac52adc4b89de20918968c8df78b9c80
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/447968
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
There are two types of signing of CR50 images - prod and dev.
Designating images built with CR50_DEV variable set in the environment
as DEV is confusing, as this has nothing to do with the signing type
(dev vs prod), and is in fact indicating an image with many debug
features enabled.
This patch changes the string to "DBG".
BRANCH=cr50
BUG=none
TEST=verified that the modified image has correct string in the
version field:
> vers
Chip: g cr50 B2-D
Board: 0
RO_A: * 0.0.10/29d77172
RO_B: -1.-1.-1/ffffffff
RW_A: 0.0.16/DBG/cr50_v1.1.6137-1624610+
RW_B: * 0.0.16/cr50_v1.1.6137-1624610+
Build: 0.0.16/cr50_v1.1.6137-1624610+
tpm2:v0.0.287-1a68fe6
cryptoc:v0.0.8-6283eee
2017-03-06 16:51:15 vbendeb@eskimo.mtv.corp.google.com
>
Change-Id: I06a97a6aff5418a4d02e71ca23813e6d2005da5c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450903
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This counter will count the number of times the system enters deep
sleep. This is mainly for debugging purposes. With access to the deep
sleep count you can start a s3 suspend stress for hundreds of iterations
and verify that cr50 entered and resumed from deep sleep the right
number of times.
BUG=none
BRANCH=cr50
TEST=Wait until cr50 enters deep sleep. Wake it up and verify the
counter increased. Run 'idle C' and verify it is reset to 0.
Change-Id: Icb70a2fefedd82ea10934093f4c917da16b8d4ea
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/448334
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
If we are using more PWRDN or LONG_LIFE scratch registers we want to
make sure we don't clobber any existing uses. The use for each scratch
register is not documented anywhere. This change adds a comment to
init_chip with listing the uses for each long life and pwrdn scratch
register.
BUG=none
BRANCH=cr50
TEST=make buildall
Change-Id: I1e7d5b1f86dfa1a996671e864fe768976987a85e
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/448819
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Once ec receives LRESET/PLTRST on eSPI mode, both WUI57 of table 0 and
WUI15 of table 2 will be issued at the same time. We don't need two WUI
sources to indicate LRESET/PLTRST event on eSPI mode. This CL removes
initialization of LRESET/PLTRST of WUI57 of table 0 in lpc_init() for eSPI.
BUG=b:35954584
BRANCH=None
TEST=Verified that no more watchdog resets are seen on poppy.
Change-Id: Ib35b574d937c40d417ac707296ec080fd0244cf8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450022
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Using -O3 optimization level rather than -Os results in a large speed-up
for a minor code size increase for the RSA code with our current GCC
toolchain.
Add the CONFIG_RSA_OPTIMIZED option to do it on platforms which are not
too size-constrained.
On cortex-M4 based STM32L432, I'm measuring a 37 to 40% speed increase
(depending on CPU frequency) for a 200 bytes code size delta.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=manual: benchmark RSA2048 with F4 exponent on STM32L432:
-Os -O3
@16Mhz 185163 us --> 111942 us
@80Mhz 39286 us --> 24582 us
Change-Id: I8c2e4b757f037f4f645fb73ba0faaaa471b24896
Reviewed-on: https://chromium-review.googlesource.com/445218
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
When battery is fully charged, Reef starts discharging to protect
battery and starts charging again when charge level goes down
around 95%. To prevent the battery LED from showing blue with the
charger plugged in, this patch adds a new state for discharge +
nearly full. Reef shows a color indicating battery is full if
an external charger is present.
BUG=b:35775017
BRANCH=none
TEST=Fully charge Electro. Plug in OEM charger. LED lights blue.
Change-Id: I4c7c62f2c51c1d39188d1b271331984e89d5d7a3
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/448961
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since the interrupts of MIWU group E/F/G/H of table 0 are the same
(interrupt 11), we need to handle LPCs' and GPIOs' events at the
same ISR. But we also found there is a leak that ec has the chance
to skip the other events which don't belong to GPIOs unexpectedly.
(For example, LRESET and eSPI Reset) This CL fixed this issue by
only clearing pending bits belong to GPIOs in their ISRs.
BRANCH=none
BUG=b:35648154
TEST=passed warm-reset testing on pyro over 12 hours.
Change-Id: Ie626db00b54cff566798b4a593f6b0267a6fadc2
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/449472
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
In the process, also manually specify all regions exact size,
which will be useful later on (e.g. when using RO/RW of different
sizes).
BRANCH=none
BUG=chrome-os-partner:61671
TEST=make BOARD=hammer -j; flashwp true/rb/rw protects the expected
regions, flashwp noall unprotects them.
Change-Id: Ib31d9384060b1373e0834cfecb4ebd0a7bafd356
Reviewed-on: https://chromium-review.googlesource.com/430520
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The -b command line option should not be described as requiring a
parameter, as the binary file is given to most of invocations of
usb_updater.
Also adding the missing -p command line option description.
BRANCH=none
BUG=none
TEST='usb_updater -b <file name>' does not fail any more
Change-Id: I6ceefa8c4dda841db63177d6134a611600a43078
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/448956
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Flash INFO access API presently is hardcoded to access the endorsement
space. To enable INFO map based rollback protection one needs to be
able to access different areas of the INFO.
The FLASH REGION3 register used by the API is in fact used for NVMEM
flash accesses too, so it is better to leave it alone and use REGION6
for the purpose of accessing of the INFO space.
The API now requires the user to specify flash offset and region size,
the size must be power of 2, the offset must be aligned at size, and
the region must not spill beyond the INFO space address range.
BRANCH=cr50
BUG=b:35774863
TEST=with the rest of the patches applied it is possible to erase the
base word in the info map segment;
reading of the endorsement space at startup still works fine.
Change-Id: I008165ee9e11a7b49985d2b30683509cf6699431
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/447965
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The host may ask for our switch state at any time, so do initialization
immediately after lid + power button are initialized.
BUG=chrome-os-partner:63073
BRANCH=gru
TEST=On kevin, verify system boots when EC reset is triggered with lid
open. Verify lid close and power button press still succeed to
power-down from dev screen.
Change-Id: I8e37c02ef4f4d2d7c06beb383cdbda8eea67bc5c
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444322
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit 106d33cd3a8e4f3356950a3b2b92ea587977b4e7)
Reviewed-on: https://chromium-review.googlesource.com/445276
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
The function tcpm_select_rp_value() is used to set a given Rp
value. This function was not supported for boards that use the config
option CONFIG_USB_PD_TCPC. This CL adds a weak board_ function which
can be overloaded for boards that have the requirement to set Rp to
different values.
BUG=chrome-os-partner:61878
BRANCH=servo
TEST=run 'make buildall'. On plankton added a console command to trigger
a call to tcpm_select_rp_value(0, 0), verified that it returned
2 (EC_ERROR_NOT_IMPLEMENTED). Then added board_select_rp_value() to
plankton's board.c and verified that it returned 0.
Change-Id: I1cd6f0ed51717736d30575c58025bd9a1c5d6fc4
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446685
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The json parser used by the signer is perfectly capable of parsing
multiline contents.
Let's reformat signer manifests to make it easier to see the entire
file in one terminal window.
BRANCH=none
BUG=b:35774863
TEST=none
Change-Id: I41d69ad11f07521f68a7a50227dc843872613127
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/447841
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Currently if an interrupt is pending before it is enabled the interrupt
will fire immediately. In most cases this is fine, but if we want to
use the interrupt to trigger something like waking the AP it should be
sure that it won't immediately fire once enabled.
For example: on the Eve board we have the trackpad interrupt run to the
AP and the EC in order to support wake from Deep S3 (magic AP state that
only the EC can wake it from). This interrupt is used in S0 by the AP
while ignored by the EC, and then enabled on the transition to S3 in
order to be able to wake. Since it has been active the interrupt may
be pending in the EC (depending on the chip), which can result in the
interrupt firing immediately and waking the AP.
BUG=chrome-os-partner:62224
BRANCH=none
TEST=This has been functionally tested on npcx only as that is what I
have a use case and system for, the others compile and look right but
have not been directly tested.
Change-Id: I9e0877d99e7f09f4c30bf9861fbad81c12c059ad
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446962
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Any call to flash_execute_cmd() can interfere with UMA / mapped read
access, so grab the mutex first.
BUG=b:35587287,b:35848370
BRANCH=reef
TEST=Verify SW sync completes 8 hour stress test on kevin. Also verify
'ectool flashspiinfo' succeeds.
Change-Id: Ib1b04371546c27517c1b1ac860e9afbc1fed435e
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/447905
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Remove the MP2949 workaround as it was only needed for P0 boards.
The fix is "sticky" so any P0 board will already have fixed
values in the MP2949 EEPROM.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=build and boot on Eve P1
Change-Id: I2cb13a6c5ff5ec521e75d51e31fb8356a5081193
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446594
Reviewed-by: Scott Collyer <scollyer@chromium.org>
When debugging PWM on eve I noticed that every tick was adjusting
the pwm duty cycles for all LEDs, even if nothing changed. To keep
that from happening keep track of the current led state and only
adjust if it changes.
This also modifies the "on+charging" state to not set both LEDs to
blue and then change on to amber, but keep track of which side is
charging and set both LEDs to their expected colors.
Finally it fixes a bug with suspend and a full battery not blinking
the other side white to indicate suspend state.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=ensure LEDs still behave as expected with charging and full
battery while in S0, S3, S5 states.
Change-Id: I98e5d5ad04b3e71da6fa4056e95f3661a9271ecf
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446593
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Port changes cl/288874 to generic kionix driver.
From cl/288874:
After we write SRST in CTRL2, there seems to be a period of time where the
accelerometer doesn't respond to i2c commmands. Instead of failing the init
just consider it as part of the timeout period.
BUG=chrome-os-partner:39269,chrome-os-partner:63146
TEST=make -j buildall
BRANCH=veyron,cave
Reviewed-on: https://chromium-review.googlesource.com/445973
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit 4a34b0d88f6b0075ee66a18f4aa22325dc766eb6)
Change-Id: I2197aa7741d1482b76c7c07b0cb0c171aab86a59
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446417
P1B adds 2 new GPIO signals to explicitly control the 1.5 vs 3.0
current limit selection. In addition, the use case for the 5V enable
gpio changes to on/off and no longer needs to be toggled between input
and output.
This change is tied to the board version so that the operation for P1
and older boards is unaffected.
BUG=chrome-os-partner:61431
BRANCH=none
TEST=Manual
Connected display adapter into C0 port and verified gpio signals:
1 USB_C0_5V_EN
0* USB_C1_5V_EN
1* EN_USB_C0_3A
0 EN_USB_C1_3A
Then connect another adapter to C1:
1 USB_C0_5V_EN
1* USB_C1_5V_EN
0* EN_USB_C0_3A
0 EN_USB_C1_3A
Remove adapter from C0:
0* USB_C0_5V_EN
1 USB_C1_5V_EN
0 EN_USB_C0_3A
1* EN_USB_C1_3A
Also tested P1 system to verify that the correct board version is read
and the signals match the expected value.
Change-Id: Iebab84304a33282c766b8963dba4a56052a295c7
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/447866
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Lower hammer's power usage when USB is not in use.
One thing that is missing is some way to put the trackpad into
low power mode as well (should be some I2C command).
BRANCH=none
BUG=chrome-os-partner:62325
TEST=build and flash hammer, connect USB, check power consumption
averaged over 10s is around ~57 mW (~32 mW for base EC,
~25 mW for trackpad).
TEST=Suspend host, power consumption drops to ~3 mW
(~0.04 mW average for base EC, ~3 mW for trackpad).
TEST=Pressing keyboard key or touch the trackpad wakes the system.
Change-Id: I45f5e300d9d9e2bf49a327949649b0e44b544640
Reviewed-on: https://chromium-review.googlesource.com/446220
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
USB uses a special mode the trigger remote wake-up during host
suspend, by setting the K-state on the data differential pair,
and setting a bit in the USB config descriptor attributes field.
Let's enable that so that hammer can wake up host from S3.
BRANCH=none
BUG=chrome-os-partner:62325
TEST=Connect hammer to chell, put chell in S3. Press a key (or use
("kb 3 3 1; kb 3 3 0" in console), or touch trackpad =>
host wakes.
Change-Id: Ib7b1e9047e01869f07ddd771c9c9bc640eef10d6
Reviewed-on: https://chromium-review.googlesource.com/446240
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This follows the basics of what is decribed in
RM0091 Reference Manual 30.5.5 Suspend/Resume events .
We call enable/disable_sleep at suspend/resume, to make
sure the EC stays awake when USB is connected and active.
We also call clock_enable/disable_module, which is stubbed on
stm32f0, but can be used on other devices in the family.
This also fixes interrupt handling in usb_interrupt, by only
clearing interrupt bits that were handled instead of resetting
them all, which is racy, and can potentially lead to issues
if reset comes soon after a resume event.
BRANCH=none
BUG=chrome-os-partner:62325
TEST=build and flash hammer, connect to chell, suspend/resume,
and see that hammer prints USB suspend and USB resume lines.
Change-Id: Ie9d02fd4a114add3ebc98dc9393680bc9a64a522
Reviewed-on: https://chromium-review.googlesource.com/446239
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The command line option to trigger communicating with the cr50 over
/dev/tpm0 has been set to 'spi' originally, as SPI was the interface
to communicate with the TPM on first devices using cr50.
This is not technically correct, as many devices use i2c for this
purpose. Let's rename the command line option from 'spi' to 'dev' and
correct names and comments to reflect this too.
BRANCH=none
BUG=none
TEST=ran on a reef device:
localhost tmp # ./usb_updater -f --systemdev
Could not open TPM: Device or resource busy
localhost tmp # initctl stop trunksd
trunksd stop/waiting
localhost tmp # ./usb_updater -f --systemdev
start
target running protocol version 6
offsets: backup RO at 0x40000, backup RW at 0x4000
keyids: RO 0xaa66150f, RW 0xb93d6539
Current versions:
RO 0.0.10
RW 0.0.16
localhost tmp # ./usb_updater -f -s
start
target running protocol version 6
offsets: backup RO at 0x40000, backup RW at 0x4000
keyids: RO 0xaa66150f, RW 0xb93d6539
Current versions:
RO 0.0.10
RW 0.0.16
Change-Id: Ifbdd3618209ad9930e0678cf50e82a789ae5e2cd
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/447781
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit enables the use of the nvmem vars module. The console lock
state is migrated from using the long life scratch register, to nvmem
vars instead which will persist across power on reboots.
BUG=b:35586145
BRANCH=None
TEST=Flash a dev image. Lock the console. Remove all power from the
system. Power on system and verify that console is still locked.
Unlock the console, remove power from the system, power on the system,
verify that the console is now unlocked.
TEST=Repeat the above test, but using the nvtestvar console command
instead.
Change-Id: I03a2098bb0017cfca59889457a332eafb0e95db6
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445804
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
STM32F091VC has 32 flash protection sectors (31 x 4KB + 1 x 132KB),
which doesn't fit the layout requirement in config_std_internal_flash.h.
This CL hardcodes the layout and flash bank mapping.
BUG=chrome-os-partner:62372
BUG=chromium:694972
TEST=load on elm and manually enable write protect using flashrom
# flashrom -p ec:dev=0 --wp-enable
check ec console write protect option bytes, bank 31 is writable
> rw 0x1ffff808
read 0x1ffff808 = 0xff00ff00
> rw 0x1ffff80c
read 0x1ffff80c = 0x7f80ff00
BRANCH=oak
Change-Id: I23dcf87bfbcd2f37e97a87e94847dce1ea1d343c
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446176
The new option allows the operator to explicitly request the post
reset reboot instead of immediate reboot (which is now ignored by
production cr50 images).
Also sort option descriptions and move the colons where they belong
(after command line arguments requiring additional parameters),
BRANCH=none
BUG=none
TEST=running usb_updater with -b or -d without extra parameter causes
the return error code and the help message printed.
running
$ ./extra/usb_updater/usb_updater -p build/cr50/ec.bin
results in a proper image transfer, with the following reboot of
the chromeos device triggering cr50 reset and the new downloaded
image running.
Change-Id: I64328973a2dfac1b78262f1ffacd677e52956d27
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446939
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Until we can understand and fix the reset loop when we enable
low power for the TCPC mux lets just disable that feature.
BUG=chrome-os-partner:63204
BRANCH=none
TEST=build and boot on eve, verify that TCPC does not get in
a reset loop when the system is off.
Change-Id: I646948066a76ab25758e437498f3fb7f533ba6a5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446592
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Our previous idea to cut Rd for many reset cases cannot work if cr50
consistently resets the EC by asserting the reset pin shortly after
power-on. Therefore, make a decision based upon whether battery-backed
memory indicates we previously negotiated a PD power contract as a sink.
If we previously did not negotiate a contract, or if power was removed
from the device (causing battery-backed memory to wipe) then we can
assume that we don't have an active power contract.
BUG=chrome-os-partner:62952
BRANCH=reef
TEST=On reef, run "cutoff" on the console, reattach AC, and verify
device successfully wakes. Also verify Rp is dropped on console 'reboot'
and F3 + power from RW.
Change-Id: Ie300b9589cac6be7a69b77678bea6b1b6b25578c
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/443356
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This patch makes the battery led behave as follows:
Charge: Amber on (S0/S3/S5)
Full charge: Blue on (S0/S3/S5)
Discharge in S3: Amber on 1sec off 3sec
Discharge in S5: Off
Error: Amber on 1sec off 1sec
Discharge in S0: Blue on
BUG=chrome-os-partner:63202
BRANCH=none
TEST=Fully charge Electro, then the LED shows
with no charger in s0: blue
with charger in s0: blue
with no charger in s3: blinking amber
with charger in s3: blue
with no charger in s5: off
with charger in s5: blue
When not fully charged, the LED shows solid amber in s0/3/5.
Change-Id: Idbfbbf35b951ce73c06377f292746c8c1c3ce0fd
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446580
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
ROLLBACK region will be used to store rollback information, and
can be protected independently of RW (it can only be protected when
RO is protected, though).
This is only supported on stm32f0 currently.
BRANCH=none
BUG=chrome-os-partner:61671
TEST=on hammer (stm32f072)
flashinfo => RO+RW not protected
flashwp true; reboot => only RO protected
flashwp all; reboot => RO+RW+RB protected
flashwp noall; reboot => only RO protected
flashwp rw; reboot => only RO+RW protected
flashwp rb; reboot => RO+RW+RB protected
flashwp norb; reboot => RO+RW protected
flashwp all; reboot => RO+RW+RB protected
flashwp norw; reboot => RO+RB protected
TEST=on reef, rb/norb commands not available
Change-Id: I45ffc66d91cf3699ecff025e5114c59a73dc8274
Reviewed-on: https://chromium-review.googlesource.com/430519
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In preparation for adding the rollback protection region, we
would like to be able to protect RW region independently from
ALL.
BRANCH=none
BUG=chrome-os-partner:61671
TEST=make BOARD=hammer
Change-Id: I790fee6f038d511bce0f768420141b885e1c8c67
Reviewed-on: https://chromium-review.googlesource.com/444528
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Make sure all public and private host commands starting with
EC_CMD_ and EC_PRV_CMD_ are properly formed
BUG=chromium:681240
TEST=manual.
Added following host commands and verified that they were flagged
#define EC_CMD_TESTA 1234
#define EC_CMD_TESTB 0xabcd
#define EC_CMD_TESTC 0x1ABCD
#define EC_CMD_TESTD 0xXEF01
#define EC_PRV_CMD_TESTA 1234
#define EC_PRV_CMD_TESTB 0xabcd
#define EC_PRV_CMD_TESTC 0x1ABCD
#define EC_PRV_CMD_TESTD 0XEF01
These were also flagged by the script
include/ec_commands.h:#define EC_CMD_ACPI_READ 0x80
include/ec_commands.h:#define EC_CMD_ACPI_WRITE 0x81
include/ec_commands.h:#define EC_CMD_ACPI_BURST_ENABLE 0x82
include/ec_commands.h:#define EC_CMD_ACPI_BURST_DISABLE 0x83
include/ec_commands.h:#define EC_CMD_ACPI_QUERY_EVENT 0x84
CQ-DEPEND=CL:445809
BRANCH=none
Change-Id: I4630d6a887ed289a68178e8f1a8f07f5141c80bc
Reviewed-on: https://chromium-review.googlesource.com/445811
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
