In order to prevent keeping the CSAE bit at 1 forever impacts the eSPI
performance, the npcx driver enables host access wakeup functionality
before ec enters deep sleep or wfi. But this bypass also should be added
in __idle() of core/cortex-m/task.c if CONFIG_LOW_POWER_IDLE is
disabled.
This CL also narrows the bypass only when host interface is eSPI.
BRANCH=eve
BUG=b:64730183
TEST=No build errors for make buildall. Disable CONFIG_LOW_POWER_IDLE
functionality on poppy and use following script "count=0; while :;
do echo "--- iteration --- $count"; time flashrom -p ec -r ec.bin; sleep
1; count=$((${count}+1)); done" to test eSPI performances over 300
times. No errors occur and all tests' efficiency are the same as
removing CSAE bypass.
Change-Id: I8b6b69e37318208c185747151c06b3e6bdfd2f4e
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/644967
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
The bit controlling the tri-state of FIU pins is reserved when the
internal flash is used and should not be modified. This CL adds a
compiler error to prevent this kind of misuse.
BRANCH=none
BUG=none
TEST=No build errors for "make buildall". "BORAD=npcx7_evb make" with
CONFIG_CMD_FLASH_TRISTATE defined, make sure the error message is
printed.
Change-Id: I020c8ab9e02b9a377879bbd2a337943e77a369d6
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/624828
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
In eSPI systems, when the host performs a data read from the Shared
Memory space, the returned data may be corrupted. This is a result of
the Core-to-Host access enable bit being toggled (by toggling CSAE bit
in SIBCTRL register) during an eSPI transaction. The bypass for this
symptom is to set CSAE bit to 1 during initialization and remove the
toggling of CSAE bit from other EC firmware code.
But keeping the CSAE bit at 1 forever also impacts the eSPI performance
a lots. When the core clock is stalled by sleep, deep sleep or wfi
instruction, the eSPI Peripheral Channel transaction is stalled if this
bit is set. The bypass for this symptom is to wake up the core by eSPI
peripheral channel transaction and let eSPI module handle the remaining
packet.
BRANCH=eve
BUG=b:64730183
TEST=No build errors for make buildall. Flash poppy ec image, make sure
it can boot to OS. Run "ectool version" over 100000 times, no error
occurs. Use following script "count=0; while :; do echo "---
iteration --- $count"; time flashrom -p ec -r ec.bin; sleep 5;
count=$((${count}+1)); done" to test eSPI performances over 1000
times. No errors occur and all tests' efficiency are the same as
removing CSAE bypass.
Change-Id: I1b9051c5a3d368a5917882d9d1c3bb00481a53ad
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/620301
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
In npcx7, we introduce an enhanced version of Serial Host Interface
(SHI) module. This CL adds the support for it.
It includes:
1. Increase the size of IBF/OBF from 64 bytes to 128 bytes.
2. Add IBULVL/IBFLVL2 in SHICFG4/SHICFG5 which can configure at which
level the IBF pointer reaches to trigger an interrupt to core.
The current setting of these two register fields are:
IBFLVL - 64 (half full)
IBFLVL2 - 8 (the size of host command protocol V3 header)
3. Dedicated CS high/low interrupts.
In old SHI module, the way to generate CS high interrupt event is via
EOR bit. However, it has a defect that EOR won't be set to 1 when CS
is de-asserted if there is no SHI CLK generated. It makes the
handling of glitch condition more complicated.
In the new SHI module, we introduce the CS high/low interrupts
(by enabling the CSnFEN/CSnREEN) to make it easier to handle the
glitch.
The new SHI module is enabled during SHI initialization when the chip
family is npcx7.
BRANCH=none
BUG=none
TEST=No build errors for "make buildall". Test host command
communication is ok between npcx7 EVB and a host emulator.
Make sure the glitch condition can be detected and handled.
Also test the driver on gru, make sure it won't break the operation of
old SHI module.
Change-Id: If297fd32a0ec2c9e340c60c8f1942868fa978fbc
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/607812
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This reverts commit ddbfe690e2.
Reason for revert: Causes move cursor movements to be choppy, and device
to be very unresponsive during flashrom EC operations.
Original change's description:
> npcx: workaround the bug that SHM data read via eSPI may be corrupted
>
> In eSPI systems, when the Host performs a data read from the Shared
> Memory space, the returned data may be corrupted. This is a result of
> the Core-to-Host access enable bit being toggled (by toggling CSAE bit
> in SIBCTRL register) during an eSPI transaction.
>
> The workaround in this CL is to set CSAE bit to 1 during initialization
> and remove the toggling of CSAE bit from other EC firmware code.
> (i.e., let the CSAE bit be always 1.)
>
> BRANCH=none
> BUG=none
> TEST=No build errors for make buildall. Flash poppy ec image, make sure
> it can boot to OS. Run "ectool version" over 100000 times, no error
> occurs.
>
> Change-Id: I7aac6805ece64e8f77964d4acb026d9871cd2ebe
> Signed-off-by: CHLin <CHLIN56@nuvoton.com>
> Reviewed-on: https://chromium-review.googlesource.com/590396
> Commit-Ready: Shawn N <shawnn@chromium.org>
> Tested-by: CH Lin <chlin56@nuvoton.com>
> Reviewed-by: Shawn N <shawnn@chromium.org>
BUG=b:64730183
TEST=flashrom -p ec -r ecr.bin, device still responsive.
Change-Id: Idaeef2707df990b2441a77a15807698d41018449
Reviewed-on: https://chromium-review.googlesource.com/618366
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This patch defines CONFIG_DATA_RAM_SIZE, which indicates the size
of the RAM used for data, thus can be marked as non-executable.
If it's not defined, it defaults to CONFIG_RAM_SIZE. Thus, other chips
are not affected.
BUG=b:36037354
BRANCH=none
TEST=buildall. Run 'sysjump disable' on Reef and verify mpu_protect_ram
is successful.
Change-Id: I54d74fd1dabff7e1013fff2542fd02c3646803d1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/596518
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In eSPI systems, when the Host performs a data read from the Shared
Memory space, the returned data may be corrupted. This is a result of
the Core-to-Host access enable bit being toggled (by toggling CSAE bit
in SIBCTRL register) during an eSPI transaction.
The workaround in this CL is to set CSAE bit to 1 during initialization
and remove the toggling of CSAE bit from other EC firmware code.
(i.e., let the CSAE bit be always 1.)
BRANCH=none
BUG=none
TEST=No build errors for make buildall. Flash poppy ec image, make sure
it can boot to OS. Run "ectool version" over 100000 times, no error
occurs.
Change-Id: I7aac6805ece64e8f77964d4acb026d9871cd2ebe
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/590396
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
gpio_interrupt_type_sel() is guaranteed to be called with at least one
GPIO_INT_ANY bit set, but our new toolchain doesn't seem to realize it.
BUG=chromium:747553
BRANCH=None
TEST=`make BOARD=gru -j` with next_gcc, also verify kevin boots to OS.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ice2a9963983dca2ee9c0c543bf55c27753c42933
Reviewed-on: https://chromium-review.googlesource.com/584820
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If we have no ISR for an enabled GPIO interrupt (eg. for a UART GPIO
interrupt that wakes from low-power idle) then clear it, to avoid
interrupt storm.
BUG=b:63958831
BRANCH=eve
TEST=Verify we can repeatedly wake from low-power idle on eve by hitting
'enter' on the EC console.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6a01cae33e3bf1a3b5b42c0389c4613dc1cb9b7d
Reviewed-on: https://chromium-review.googlesource.com/584011
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
This CL adds CHIP_VARIANT_NPCX7M6G to support another npcx7 ec SKU.
Please note that the default setting in npcx7_evb is npcx7m6f.
For the EVB using the 128-pins EC package, please change CHIP_VARIANT
from npcx7m6f to npcx7m6g in build.mk.
BRANCH=none
BUG=none
TEST=No build errors for make buildall; Set CHIP_VARIANT=npcx7m6g in
board/npcx7_evb/build.mk; Build the image and test on EVB.
Change-Id: I2f857e4f6524eab45930bac3cc209409d4a53ee8
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/569320
Commit-Ready: Jun Lin <riverq@gmail.com>
Tested-by: Jun Lin <riverq@gmail.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
In the CL:505861, we print the warnning message to indicate that the VBAT
has ever dropped if the IBBR bit is set but do not clear the IBBR. This
forbid the access to BBRAM until EC power-on reset.
In this CL, we clear the IBBR bit to make BBRAM work again without the
need of EC power-on reset.
BRANCH=none
BUG=none
TEST=No build error for make buildall; Check warining messages are
printed and IBBR bit is cleared.
Change-Id: I58a0370c1c496b3c1208d9d5ac6b55c4d66fe8b6
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/542976
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch makes EC read the slot to verify and jump to from the
battery backed up RAM (BBRAM).
BUG=b:38462249
BRANCH=none
TEST=Boot Fizz
Change-Id: I0c78861ea3ccdc45d0aa08e690e3a68f53658409
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/518255
This patch sets/clears RESET_FLAG_AP_OFF on S5<->S3 transitions.
It's set when the system gracefully shuts down and cleared when the
system boots up. The result is EC tries to go back to the
previous state upon AC plug-in on battery-less systems.
This is required for digital signage and kiosk.
This also reverts: CL 514209, 486946, and 486945.
BUG=b:37536389
BRANCH=none
TEST=Tested as follows:
A. Boot to S0
A.1. Unplug AC while system is in S0 then plug in - PASS
A.2. Unplug AC while system is in S3 then plug in - PASS
A.3. Press recovery+power in S0 - PASS
A.4. Press recovery+power in G3 - FAIL (To be fixed)
A.5. Execute reboot console command - PASS
A.6. Execute reboot OS command - PASS
A.7. Execute reboot console command in G3 - PASS
B. Boot to G3
B.1 Unplug AC while system is in G3 then plug in - PASS
B.2 Unplug AC after B.1 then plug in - PASS
B.3 Shutdown by power button on recovery screen then unplug
plug in AC - PASS
B.4 Execute reboot ap-off console command - PASS
B.5 Execute shutdown command from OS then plug in AC - PASS
Change-Id: Iaa6f930585050fdd3511c711b449dff47525066d
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/517287
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Don't discard irqprio data when the IRQ_PRIORITY macro is used directly
(for watchdog / watchdog timer).
This change is probably a NOP for all platforms, since the power-on
default for the IRQ prio register seems to be zero, which is the same
priority we're setting in our direct use of IRQ_PRIORITY.
BUG=chromium:634701
BRANCH=None
TEST=Verify 'prio_44' entry exists in irqprio section by checking
ec.RO.map on kevin.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Idaffc484a2ce4749c18212f179b3951ff570aed0
Reviewed-on: https://chromium-review.googlesource.com/545201
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Mapped reads are relative to CONFIG_EC_*_STORAGE_OFF, not
CONFIG_R*_MEM_OFF. The previous implementation happened to work for
internal mapped storage (eg. stm32) but failed for external mapped
storage which is copied to SRAM before execution (eg. npcx).
BUG=b:62841029
TEST=Verify sysjump works again on eve/poppy/soraka. Verify sysjump
and sig verification continues to work on fizz and stm32.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id51ce5697555eea38b246b58dbf47f22d4befaa7
Reviewed-on: https://chromium-review.googlesource.com/541861
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
The setup time of original i2c setting which i2c freq is 1MHz is closed
to the margin of the spec. This CL improves the setup time with a new
setting. (For example, in npcx evb, measured setup time now is about
480 ns.)
This CL also removes the timing settings of higher i2c source clock
frequencies which are not used so far to save the code size.
BRANCH=none
BUG=b:38217035
TEST=No build error for make buildall; run stress test with i2cxfer and
i2cscan on gru with 400K and 1MHz i2c freq.
Change-Id: I5428a7dab1d935fd428ee9012604813e752cead8
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/527739
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This CL locks VCC_RST# alternative bit, NO_VCC1_RST, of DEVALTA
in case the developers switch it to GPO77 unexpectedly by setting
VCC1_RST_LK bit in DEV_CTL4.
BRANCH=none
BUG=none
TEST=Use rw console command to make sure NO_VCC1_RST bit is
locked on npcx7_evb.
Change-Id: Ic7882ef1c8050c3daca85bd241d5368f009e4e2e
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/522206
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In this CL, we add selecting LFCLK sources functionality for npcx7 ec
series. (Please notice not all of npcx7 ec series support this feature.)
Beside internal LFCLK source, ec also can choose the external 32kHz
crystal oscillator as LFCLK source for the specific application. We also
introduce a new definition, CONFIG_CLOCK_SRC_EXTERNAL, to switch this
feature in the board level driver.
This CL also adds:
1. LFCG register definitions in registers.h.
2. Change the order of each npcx modules by memory address.
BRANCH=none
BUG=none
TEST=Output LFCLK source through GPIO75. Compare with external 32kHz
crystal osc. on npcx7_evb and make sure the sources are the same.
Change-Id: I137146bf51ccb51266b9aac1e2e28bcea87dc4f5
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/520745
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This CL adds:
1. Fixed the incorrect address of BKUP_STS register.
2. Cleared the IBBR bit of BKUP_STS register at initial because
its default value is 1(means the content of BBRAM is invalid) whenever
VBAT is powered up.
3. Add debug msg when IBBR bit is set to indicate the BBRAM's
corruption.
4. Modified the valid BBRAM offset from 1 to 0 and size from 63 to 64.
BRANCH=none
BUG=b:38187362
TEST=No build error for make buildall; Check IBBR is cleared at initial.
Check IBBR is set by changing the VBAT voltage below VBAT MIN.
Test console command "reboot ap-off" on poppy.
Change-Id: I69d98b50d4e0aec17b55a4a9b5e8f1a412a3fe45
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/505861
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
max_response_packet_size was incorrectly set to
response_size + SPI header/footer,
leading to the command handler to return EC_RES_OVERFLOW when the
response buffer size was set by the host to a larger size then
response_size.
It is happening since flashrom does not limit itself to 128 bytes
command since cl/264034.
The SHI repsone buffer is laid out as follow:
,.... out_msg_padded
/
|
|< SHI_OUT_START_PAD >|< SHI_MAX_RESPONSE_SIZE >|< SHI_OUT_END_PAD >|
+---+-----------------+-------------------------+-------------------+
| | | | |
+---+-----------------+-------------------------+-------------------+
| \
| -------
| \
| EC_SPI_FRAME_START_LENGTH
|
\..... out_msg
BUG=b:35571522,chromium:725580
BRANCH=gru
TEST=Before flashrom would fail:
cros_ec_set_max_size: sending protoinfo command
cros_ec_set_max_size: rc:12
cros_ec_set_max_size: max_write:536 max_read:163
...
Reading flash... __cros_ec_command_dev_v2(): Command 0x11 returned
result: 11
Ater, flashrom works:
cros_ec_set_max_size: sending protoinfo command
cros_ec_set_max_size: rc:12
cros_ec_set_max_size: max_write:536 max_read:160
...
Reading flash... done.SUCCESS
Verified that cros_ec.c/cros_ec_spi.c set some space for header and
footer in addition to max_response_packet_size.
Change-Id: I0de7ee5e8109e9277692113f2bb1d4a4758be9f6
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/520585
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
In old system driver, ec clears "Predefined Time Occurred" (PTO) flag
before setting a new alarm (PT field in WTC). If PT field is the same
as the first 25 TTC bits at this moment, we might receive unexpected
rtc interrupt again. This CL sets new alarm first then clears PTO flag
to make sure rtc interrupt is issued from new alarm.
BRANCH=none
BUG=b:38310685
TEST=Duplicated the same symptom by the script in issue 38310685 on
gru. No symptoms occurred with the same script for 3 hours by applying
this CL.
Change-Id: Ia6410d6aa4ef8e2acb7bfadf9192d619045bfa58
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/508572
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
In order to support write-protect mechanism for the internal flash
of npcx7 ec, WP_IF, bit 5 of DEV_CTL4, is used to achieve this by
controlling the WP_L pin of internal flash. During ec initialization
or any utilities related to access status registers, we'll protect them
if WP_L is active. Please notice the type of WP_IF is R/W1S. It means we
only can unlock write protection of internal flash by rebooting ec.
This CL also includes:
1. Add protect_range array of npcx7's internal flash (W25Q80) for
write-protect mechanism.
2. Add bypass of bit 7 of DEVCNT.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series. (Besides gru)
Build poppy board and upload FW to platform. No issues found.
Passed flash write-protect checking on npcx796f evb.
Change-Id: I0e669ce8b6eaebd85e062c6751e1f3dd809e21e2
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/501727
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This CL implements two methods for hibernating on npcx7 ec. One is using
PSL (Power Switch Logic) circuit to cut off ec's VCC power rail. The
other is turning off the power of all ram blocks except the last code
ram block. In order to make sure hibernate utilities are located in the
last code ram block and work properly, we introduce a new section called
'after_init' in ec.lds.S.
We also moved the hibernate utilities, workarounds for sysjump and so on
which are related to chip family into system-npcx5/7.c. It should be
easier to maintain.
It also includes:
1. Add CONFIG_HIBERNATE_PSL to select which method is used on npcx7 for
hibernating.
2. Add new flag GPIO_HIB_WAKE_HIGH to configure the active priority of
wake-up inputs during hibernating.
3. Add DEVICE_ID for npcx796f.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found. Make
sure AC_PRESENT and POWER_BUTTON_L can wake up system from
hibernate. Passed hibernate tests no matter CONFIG_HIBERNATE_PSL is
enabled or not on npcx796f evb.
Change-Id: I4e045ebce4120b6fabaa582ed2ec31b5335dfdc3
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/493006
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This CL added the support for the quasi-bidirectional buffer which has
an open-drain output and a low-impedance pull-up resistance on KSO pins.
The low-impedance pull-up is active when ec changes the output data
buffers from 0 to 1, thereby reducing the low-to-high transition time.
Add CONFIG_KEYBOARD_KSO_HIGH_DRIVE to enable/disable this feature for
npcx7 series ec.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found.
Change-Id: I138f0e433394816e1e5c58b5053580f202c1ac48
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/497189
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This CL added the support for additional 5 adc channels on npcx7 series
ec. The pin-mux functionality of adc channels was already introduced in
CL 481561.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found.
All 10 adc channels passed the test on npcx796f evb.
Change-Id: I2c7458958ff659fce78f265eefa160050dee7daf
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/497526
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This CL added support for 8 i2c controllers and 11 i2c ports in
npcx7 series ec. we also added i2c-npcx5/7.c and moved the functions
related to chip family to them. (Such as i2c_port_to_controller(),
i2c_select_port() and so on.) Note the layout and bit position of i2c
registers which are accessed in these functions are irregular between
npcx5 and npcx7. We think abstracting them from i2c.c is easier to
maintain.
In this CL, we also modified the checking rule for I2C_PORT_COUNT in
task.h in order to prevent compiler error. So far, the ECs besides
stm32 only use TASK_EVENT_I2C_IDLE to wait for i2c hardware completes
its job. Put (I2C_PORT_COUNT > TASK_EVENT_MAX_I2C) checking rule
for all ECs seems not suitable.
It also includes
1. Remove useless NPCX_I2C_PUBIT macro function.
2. Remove useless NPCX_PWDWN_CTL_COUNT in registers.h.
3. Add CGC_OFFSET_I2C2 and CGC_I2C_MASK2 to power down the other 4 i2c
controllers of npcx7 ec.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found.
All 8 i2c controllers and 10 ports (npcx796f supports PSL.) passed
i2c stress tests on npcx796f evb.
Change-Id: I2b5076d21bcd0f8d17fd811cad2ff7bd200b112a
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/487541
Reviewed-by: Randall Spangler <rspangler@chromium.org>
On npcx5, the peci speed should be 750K bps but we got 1.5M bps since
selecting wrong source clock of peci. From the peci specification, the
speed range is from 2K bps to 2M bps. That's why we still passed the
peci test on npcx5's evb. This CL corrects the source clock of it from
apb2 to fmclk and make sure the speed is 750K bps by the scope.
BRANCH=none
BUG=none
TEST=Passed peci test on npcx5's evb and make sure the speed of peci is
750K bps.
Change-Id: Ic5c55f7be9be195182e4c4f4ad64b7426afd42db
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/486680
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
In old clock driver, the relationships between each clock sources are
ambiguous. For example, we treat OSC_CLK and FM_CLK as the same but
sometimes they're not on npcx5. (Only one OSC_CLK definition cannot
present the npcx ec's clock tree very well.) This CL added FM_CLK,
CORE_CLK, and APBx_CLK definitions and used macro functions to confine
the limitation of each clock sources in clock_chip.h to make it more
clearly.
We also modified the uart driver and fixed its source clock to 15MHz so
far in this CL. Since npcx7 already supports uart wake-up mechanism, we
removed the functions of switching pins from UART to GPIO by CHIP_FAMILY
definitions for saving code space.
It also includes:
1. Remove useless CHIP_VERSION definition.
2. Move frequency multiplier values M/N for OSC_CLK to clock_chip.h
3. Add clock_get_fm_freq() for the modules rely on it. Ex, peci.
4. Add clock turbo utilities for npcx7 series.
5. Support uart wake-up mechanism for npcx7 series.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found.
Passed clock turbo, sysjump and wake-up from UART signals stress
tests on npcx796f evb.
Change-Id: Id01a8a5d0263f0d2438e6346dfa33bcdef2be56e
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/486821
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
To configure 1 MHz speed when the APB clock is 15 MHz, the firmware
currently sets the SCLHT register to 4. However, we found out that
writing 4 to this register (and to SCLLT register) is illegal and
results in unexpected results. So there is a need to write 5 in that
case. However, this means that the actual i2c frequency will be 750 KHz.
To get a higher i2c clock frequency, there is a need to run with a
higher APB clock (and a higher core clock). For example, with APB set to
20 MHz, the i2c clock frequency is 833 KHz.
In this CL, the i2c freq setting for APB clock=20 MHz is also added which
may be used for NPCX7 in the future.
BRANCH=none
BUG=chromium:714314
TEST=No build error for make buildall(except gru). Use scope to capture
SCL signal on npcx5 EVB and make sure its freqency is about 750 KHz.
Change-Id: I9025344e6df4b584b203c8c59bb9875250d9fe4f
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/484202
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
This CL includes:
1. Add gpio_chip-npcx5/7.h files and move all macro functions
related to chip family to them. (Move wui macro func from
gpio_wui.h to them.)
2. Replace alternative and low-voltage mapping table with macro
function NPCX_ALT_TABLE and NPCX_LVOL_TABLE.
3. Add UART wakeup mechanism in __gpio_wk1h_interrupt() ISR.
4. Add gpio register definitions of npcx7 family in registers.h.
5. Add GPIO_LOCKED flag for lock functionality.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series (besides gru).
Build poppy board and upload FW to platform. No issues found.
Passed validation for all GPIO functionalities on npcx5m6g
and npcx796f evb.
Change-Id: I60c30ce223629a0d8cb767a54a0a9b02a69de9c5
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/481561
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This CL includes:
1. Add CHIP_FAMILY_NPCX5/7 and CHIP_VARIANT_NPCX7M6F to distinguish
which npcx's ec is used on the board.
2. Add config_chip-npcx5/7.h files and move features depend on chip
family into them.
3. Add NPCX_INT_FLASH_SUPPORT, NPCX_PSL_MODE_SUPPORT and
NPCX_EXT32K_OSC_SUPPORT to determine which features are supported on
npcx7 ec. We'll use them later in gpio/system/flash drivers.
4. Add ram size checking for all npcx ec series.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series (besides gru).
Build poppy board and upload FW to platform. No issues found.
Change-Id: Ia932996d01da71fea73ddd545255bdd59e581bcf
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/481560
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In npcx's fan driver, ec selected mode 5 and capturer A as tachometer's
input. Choosing TB2 as the second tachometer source is not correct since
we didn't initialize the registers for TB2. This patch modified the
second tachometer's input from TB2 to TA2 and passed the verification by
following changes.
1. Add the second fan settings in pwm_channels, fans, and mft_channels
arraies.
2. Modified ALTERNATE marco for pwm-type fans.
3. Set CONFIG_FAN from 1 to 2.
4. Set NPCX_TACH_SEL2 to 1 to test tachometer input 2. (ie.GPIO73/A6)
BRANCH=none
BUG=none
TEST=test dual fans with fanset command on npcx_evb and use faninfo for
verifying. Measure the actual rpm by scope.
Change-Id: Ia1af2732d9a64e24285d12371223eb0e77e53357
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/472310
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This CL simplified TACH_TO_RPM formula and abstracted two definitions
(PULSES_ROUND and RPM_DEVIATION) for the pwm-type fan used on boards.
The developers can modify them in board-level driver if fan doesn't meet
the default spec.
In this CL, it also fixed:
1. Declare rpm_pre as array if FAN_CH_COUNT > 1.
2. Add checking for the value of next duty of pwm.
3. Use TAPND pending bit to make sure TCRA is valid.
BRANCH=none
BUG=none
TEST=test fan used in kahlee and Sunon fan with fanset command on
npcx_evb and use faninfo for verifying. Measure the actual rpm by scope.
Change-Id: Ieb07482eb359912286414ccb9738341d98ea99e4
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/472289
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Setting PWM IO type in gpio driver seems not a proper way. This
CL moves this functionality to pwm driver and introduces a new
flag PWM_CONFIG_OPEN_DRAIN to achieve it when user declared it
in board driver.
BRANCH=none
BUG=none
TEST=test pwm functionality on npcx_evb.
Change-Id: I90c60445d1fb10902244ddf0f635d8304e72f4ab
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/458043
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Remove unused wui sources of GPIO96/A0/A2/A4 since we don't
support them in 128/132-pins packages of npcx5mng. This CL also
removes wui source of GPO66 in case developer declares it as
GPIO_INT.
BRANCH=none
BUG=none
TEST=test gpio functionality on npcx_evb, reef and poppy.
Change-Id: I363813128d02be0fc642e82ca0b463971af22a90
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/458238
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
By generating the wui mapping table for GPIO pins which have interrupt
handler like CL 451366 did, we needn't browse all items in original
gpio_wui_table to find the MIWU info. It saves code space and improves
interrupt lantency.
BRANCH=none
BUG=none
TEST=Test gpio functionality on npcx_evb, reef and poppy.
Change-Id: I77e9ad439ecf6a501a7976fe5099dd309dba81ee
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/449514
Once ec receives LRESET/PLTRST on eSPI mode, both WUI57 of table 0 and
WUI15 of table 2 will be issued at the same time. We don't need two WUI
sources to indicate LRESET/PLTRST event on eSPI mode. This CL removes
initialization of LRESET/PLTRST of WUI57 of table 0 in lpc_init() for eSPI.
BUG=b:35954584
BRANCH=None
TEST=Verified that no more watchdog resets are seen on poppy.
Change-Id: Ib35b574d937c40d417ac707296ec080fd0244cf8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450022
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Since the interrupts of MIWU group E/F/G/H of table 0 are the same
(interrupt 11), we need to handle LPCs' and GPIOs' events at the
same ISR. But we also found there is a leak that ec has the chance
to skip the other events which don't belong to GPIOs unexpectedly.
(For example, LRESET and eSPI Reset) This CL fixed this issue by
only clearing pending bits belong to GPIOs in their ISRs.
BRANCH=none
BUG=b:35648154
TEST=passed warm-reset testing on pyro over 12 hours.
Change-Id: Ie626db00b54cff566798b4a593f6b0267a6fadc2
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/449472
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
