Add a hook to act when the a device is going in tablet mode and back.
BUG=chromium:606718
BRANCH=kevin
TEST=Test with evtest that an event is sent to the AP.
Change-Id: Ic9c3b158f1178504af41abff18b28de8e07fc7a7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380412
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This CL includes changes in Cr50 required to support TPM via
the I2CS interface.
BRANCH=none
BUG=chrome-os-partner:40397
TEST=manual
Limited testing so far. Verified that the I2CS interface is
initialized properly and that register reads occur when
initiated on the AP console via command i2cget -y 8 0x50 0x1 w
Change-Id: I16ac17c7c82d420a384908e4b5a9867a3b24bc9e
Reviewed-on: https://chromium-review.googlesource.com/356241
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
To save space of working image, make the console memory commands
optional.
BRANCH=veyron
BUG=b:27849483
TEST=Compile, save 320 bytes.
Change-Id: Ia538b30b4c06955c44b29eb22ed1a09fad83bd9e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/379115
Reviewed-by: Randall Spangler <rspangler@chromium.org>
TPM2.0 needs more NvMem space and currently the whole block is
contiguous in memory with 2 partitions. This CL removes the
requirement that the partitions are in contiguous which allows for 1
partition to placed at top of RW_A and the other at RW_B.
This CL does not change the size of each partition as that will be
done in a subsequent CL.
BRANCH=none
BUG=chrome-os-partner:56798
TEST=manual
Tested with the unit test 'make runtests TEST_LIST_HOST=nvmem' and
verified that all tests pass.
Tested on Kevin, erased the existing NvMem area and verified that TPM
was still manufactured and executed the command: trunks_client --own
Erased parition 0 and 1 in the new locations and repeated the tests.
Change-Id: I295441f94dccdf5a152c32603c2638ffac23f471
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/378675
Commit-Ready: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Tested-by: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
There is now a call to reset the retry counter before the hard reset
after an update. Cr50 will use the updated image for the next 5 boots,
but on the 6th it sees the retry counter is greater than 5 and then
jumps back to the old image. Cr50 needs to call
system_process_retry_counter to reset the counter and corrupt the old
image header to prevent falling back to the old image.
Normally the reset counter would be processed after it receives a TPM
command. Reef does not have Cr50 TPM support. Until Cr50 has TPM
support for Reef, Cr50 should have a different point to know when the
update is good. This change adds a board property to mark the process
the reset counter once the Cr50 USB controller receives a set address
request from the host. On Reef the controller defaults to the AP PHY
when suzyq is not connected, so it should have a connection to the AP
or through suzyq after boot.
The board property is only added to Reef. Behavior on Kevin and Gru is
unchanged.
BUG=chrome-os-partner:56864
BRANCH=none
TEST=update reef. Wait until Cr50 prints 'SETAD' then run 'rw
0x4000012c' and verify it is reset to 0.
Change-Id: If517202f25a694cd70550e3be047ea502e7c5383
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380354
This is for boards on which AC_PRESENT can be expected to fluctuate
over a much longer period than the code was originally designed for.
Specifically, USB-PD systems may require several hundred milliseconds
for the state machine to settle before making decisions based on
AC_PRESENT status, for example, changing LED state.
BUG=chrome-os-partner:56471
BRANCH=none
TEST=Tested on Reef with follow-up patch
Change-Id: I370048cb79d1593a14077563ec8db8e8282afb16
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/378755
CONFIG_POWER_TRACK_HOST_SLEEP_STATE has a dependency on
CONFIG_POWER_COMMON, so remove it from test builds that don't have a
chipset task, rather than heavy-handedly removing it from all test
builds.
BUG=chrome-os-partner:56197
BRANCH=None
TEST=`make BOARD=gru tests`
Change-Id: I86e20b4dccbb01ee285054a47093d6f60abc2166
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/378119
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
stm32f446 uses a synopsys designware USB block
rather than the typical ST one. This change adds driver support
for the new block, including usb console support.
BUG=chromium:608039
TEST=usb console works
BRANCH=None
Change-Id: I0e143758ae0b5285f1c94ea2ec5aee159e22e00c
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/365448
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add a policy to handle the case where the device can source the
`CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT` over one of its type-C port if
there is no sink connected on the other ones.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:56110
TEST=manual: on Kevin, plug and unplug various devices on the 2 ports,
while measuring the type-C pull-up with Twinkie.
Change-Id: Id5961f04d0a1b1073f5ab340068efd9079918209
Reviewed-on: https://chromium-review.googlesource.com/373818
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
UART0 RX only needs to be disabled on reef. This change uses a system
property instead of a #define to disable UART0 RX that way it can just
be done on Reef not Gru or the dev board.
BUG=chrome-os-partner:55510
BRANCH=none
TEST=manual
rw 0x4060000c shows a value of 1 for reef and 3 for gru
gru kevin and reef still boot.
Connect DIOA13 to DIOA1 on the dev board and verify the console
can be used.
Change-Id: I5ee3559c2b35f959c0d67f233d1dfa40743b4064
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/378336
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
This adds support for CONFIG_RESTRICTED_CONSOLE_COMMANDS. If the
appropriate options are configured, restricted commands can be
prevented from running.
Nothing in this CL actually uses that, but it works if you turn
it on.
BUG=chrome-os-partner:55322
BRANCH=none
TEST=make buildall, test on Cr50 hardware
I also tested it manually. If you add this to board.h:
#define CONFIG_CONSOLE_COMMAND_FLAGS
#define CONFIG_RESTRICTED_CONSOLE_COMMANDS
#define CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT CMD_FLAG_RESTRICTED
and this to board.c:
static int restricted_state;
int console_is_restricted(void)
{
return restricted_state;
}
static int command_lock(int argc, char **argv)
{
int enabled;
if (argc > 1) {
if (!parse_bool(argv[1], &enabled))
return EC_ERROR_PARAM1;
restricted_state = enabled;
}
ccprintf("The restricted console lock is %s\n",
restricted_state ? "enabled" : "disabled");
return EC_SUCCESS;
}
DECLARE_CONSOLE_COMMAND_FLAGS(lock, command_lock,
"[<BOOLEAN>]",
"Get/Set the restricted console lock",
0); /* no restrictions */
then you can use the "lock" command to enable and disable every
other console command except for it and "help".
Change-Id: Ic9517f9ea7a9867f15e5d14b302246070163d558
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/376186
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If we add a .flags field to the console commands data structure,
we can use it to distinguish some commands from others, for
example to mark some commands as safe and others as dangerous.
This just adds the undefined CONFIG_ options. They aren't used
anywhere, so there's no behavioral difference yet.
BUG=chrome-os-partner:55322
BRANCH=none
TEST=make buildall
Change-Id: I17fdf177dcb4324c77565bd95344da1405ea15ed
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/376185
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add API to switch the Rp pull-up value on CC dynamically at runtime.
This is a preparatory work for boards having a more complex maximum
source current policy (eg 2 ports sharing a common pool of power).
For fusb302, update the voltage thresholds for open/Rd/Ra as they depend
on the Rp (was missing from the previous change).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:56110
TEST=make buildall
Change-Id: Id3c24a31a16217075a398ec21ef58ee07187a882
Reviewed-on: https://chromium-review.googlesource.com/373501
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Cr50 needs to connect to the AP phy when not in ccd so cr50 can be
updated and used as a gnubby. This change uses the strapping options
to detect when it is on reef and modifies the ccd behavior to
initialize usb on the AP phy when ccd is disabled. On gru the cr50
behavior is unchanged.
In RDD this change removes the checks that the current_map is the
correct one based on the detected debug state. rdd_init calls
rdd_interrupt to set up the usb and ccd state correctly. Having that
check prevents that initial rdd_interrupt from calling rdd_detached.
Before rdd_detached just disabled usb and we knew during init it
would already be disabled. Now we want to make sure it is called if a
debug accessory is not attached to initialize usb on the AP PHY.
BUG=chrome-os-partner:56098
BRANCH=none
TEST=manual
verify ccd still works on gru
disconnect suzyq and reset reef.
run lsusb on the AP and verify it shows cr50 as a device.
connect suzyq and check that the AP no longer sees cr50.
disconnect suzyq and verify the AP sees it again
Change-Id: I3c1ccc54895835bce12302f3ea43fc2e751b4c97
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/372920
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
when TCPC takes a longer time to update its CC status upon
connection, a legacy C-to-A charger or certain Type-C charger
that presents 5V VBUS by default, TCPM could be mistaken the
charger as a debug accessory.
BUG=chrome-os-partner:55980
BRANCH=none
TEST=Manually tested on Reef. PD, Type-C, BC1.2, non-BC1.2,
DP, HDMI are working on both C-ports.
Change-Id: Ic3b0ecd3d14109239d8c0ff0064476595b7f93a0
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/367950
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Nothing has used this config option since Spring and Skate, back
in early 2014. There's nothing in ToT that uses it at all. I want
to add something similar for other purposes, and having two
similar-sounding options will just cause confusion.
NOTE: Although the comments in include/system.h said that the two
functions
system_get_console_force_enabled()
system_set_console_force_enabled()
were only useful when CONFIG_CONSOLE_RESTRICTED_INPUT is defined,
they were being used in chip/stm32/system.c. But since the
bkpdata registers are only accessible to the EC, there was no way
to initialize or modify the one relevant bit that those functions
cared about, so they almost certainly had no effect.
BUG=chrome-os-partner:55322
BRANCH=none
TEST=make buildall
Change-Id: Id41541193d4559f5c507bdd0268b049166af4497
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/374525
* Added MACRO for specifying row size of flash device.
* Set chip/g specific values for flash row size.
The flash API for g/chip will segment large write operations into a
maximum of 32 word blocks for batch writes to flash memory. Prior to
the change in this commit, the segmentation will adhere to avoiding
crossing page boundaries (2048B) but will not respect row boundaries
(256B). The flash controller will reject any write op that crosses a
row boundary and set a row boundary violation code on its error
register.
BRANCH=none
BUG=b:30819377
TEST=make BOARD=haven_dev
Change-Id: I489122ec0f0db6374dd373a1385c3012bdface20
Reviewed-on: https://chromium-review.googlesource.com/371003
Commit-Ready: Bill Richardson <wfrichar@chromium.org>
Commit-Ready: Johnnie Chan <johnniec@google.com>
Tested-by: Johnnie Chan <johnniec@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
BMP280 driver API is designed to work with motion
sensor task. The sensor sampling parameters are
configured optimally for handheld device in accordance
with BMP280 spec recommendation.
BUG=None
BRANCH=master
TEST=Tested on amenia; with appropriate .odr in board file
test command "accelread 4" returns raw pressure
value in Pa; accelinfo on 4000 shows Pa value.
Change-Id: I3f4c0c33a77dd317aa1425624d3cc7f4ec6b45a1
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/351660
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Add math_util, as matrix and vectors are used in this file.
BRANCH=none
BUG=none
TEST=compile when caller does not include math_util.
Change-Id: Ic8f6ada4f24a0f9d3c91dbf14bea98546089a08f
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/373039
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Since pretty much always, we've declared console commands to take
a "longhelp" argument with detailed explanations of what the
command does. But since almost as long, we've never actually used
that argument for anything - we just silently throw it away in
the macro. There's only one command (usbchargemode) that even
thinks it defines that argument.
We're never going to use this, let's just get rid of it.
BUG=none
BRANCH=none
CQ-DEPEND=CL:*279060
CQ-DEPEND=CL:*279158
CQ-DEPEND=CL:*279037
TEST=make buildall; tested on Cr50 hardware
Everything builds. Since we never used this arg anyway, there had
better not be any difference in the result.
Change-Id: Id3f71a53d02e3dc625cfcc12aa71ecb50e35eb9f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/374163
Reviewed-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Can now accept and maintain a single connection indefinitely by
sending empty packets at every connection interval to keep the
connection alive.
TEST=BTLE dongle sending connect requests and connecting to NRF51
running this code. Connection was established and ran for at least
48 hours until manual termination.
BUG=None
BRANCH=None
Change-Id: Iad4bd434ecd1edd6c5c8dfe8b72ca41fd82d0bb4
Signed-off-by: Levi Oliver <levio@google.com>
Reviewed-on: https://chromium-review.googlesource.com/370839
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This feature is not enabled, is awkwardly written, and shouldn't
be left lying around to use as a bad example. This CL doesn't
change any compiled code.
A followup CL will add a working RBOX interrupt handler.
BUG=none
BRANCH=none
TEST=make buildall; test on Cr50 hardware
Change-Id: I5d0701f55ab9521bf1f29e7ec18994c4401d68fb
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/373600
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Support Rp/Rp debug accessories in the USB PD state machine
including detecting the polarity and the available type-C current.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:52592
TEST=manual, plug a Suzy-Q reworked with Rp3A0/Rp1A5 resistors
on a Kevin, and see the PD state machine is going to
PD_STATE_SNK_ACCESSORY (and leaving it on unplug).
Re-verify a few existing accessories (Rd/Rd SuzyQ, legacy RpUSB cable,
Rp3A0 power supply).
Change-Id: Icef6c90027105d7c633f2785210ab9dae74fc33c
Reviewed-on: https://chromium-review.googlesource.com/368700
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This adds basic support for the stm32f446.
This consists of:
* New DMA model for stm32f4
* New clock domain support.
* MCO oscillator gpio export support.
* Flash support for irregular blocks.
BUG=chromium:608039
TEST=boots w/ correct clock, stm32f0 also boots.
BRANCH=None
Change-Id: I1c5cf6ddca09009c9dac60da8a3d0c5ceedfcf4d
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363992
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Previously, timeout meant the number of attempts taken to receive. Now,
it means the number of microseconds before timing out.
TEST=printouts displaying time before and after rx attempt. Not included
in CL.
BUG=None
BRANCH=None
Change-Id: I00ccfc4bbf15f77c2777f35c911dceacaff98e4f
Signed-off-by: Levi Oliver <levio@google.com>
Reviewed-on: https://chromium-review.googlesource.com/368471
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Allow the host to self-report its sleep state through
EC_CMD_HOST_SLEEP_EVENT, which will typically be sent with SUSPEND
param when the host begins its sleep process. While the host has
self-reported that it is in SUSPEND, don't assert the interrupt
line, except for designated wake events.
BUG=chrome-os-partner:56156
BRANCH=None
TEST=On kevin, run 'ectool hostsleepstate suspend', verify that
interrupt assertion is skipped for battery host event. Run 'ectool
hostsleepstate resume' and verify interrupt is again asserted by the
battery host event.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I74288465587ccf7185cec717f7c1810602361b8c
Reviewed-on: https://chromium-review.googlesource.com/368391
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Moved link layer-specific constants into link layer .h file.
Renamed data channel function to better represent its function.
TEST=make BOARD=hadoken
BUG=None
BRANCH=None
Change-Id: I239d535cf3725bf003443fc211fc802bc8aee13f
Signed-off-by: Levi Oliver <levio@google.com>
Reviewed-on: https://chromium-review.googlesource.com/367805
Commit-Ready: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Re-wrote ble_radio_init to work with both data and
advertising packets. Updated all calls to refactored function.
RADIO_PCNF0_ADV renamed because it applies to advertisement and
data packet formats. Updated all references to this value.
TEST=make BOARD=hadoken
BUG=None
BRANCH=None
Change-Id: I0fdbe0eb146ce5cbc40e3ac67bf4d0e5465dcc2f
Signed-off-by: Levi Oliver <levio@google.com>
Reviewed-on: https://chromium-review.googlesource.com/367732
Commit-Ready: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Myles Watson <mylesgw@chromium.org>
Add espi driver for x86-based platform which support espi interface such
as skylake and so on.
Added source:
1. espi.c: Add drivers which supports the utilities of peripheral and
virtual-wire channels so far.
2. espi.h: Add espi virtual-wire declaration for power sequence FW.
Modified sources:
1. lpc.c: Add interrupts and initialization steps for espi.
2. gpio.c: Add interrupt handler of espi reset.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
Change-Id: Ie80afe79d85aba47fc0b72898a8374c2898ec114
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/366181
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If an HPD IRQ event is seen, make note of it and keep the status set
until informing the host.
BUG=chrome-os-partner:55925
BRANCH=None
TEST=Manual on kevin, trigger HPD event, verify that event bit is set in
reply to first host command and not subsequent host commands.
Change-Id: I0900a683dcb344d5d4d03a1fa6e3d8de913597b2
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366990
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Sometimes a perfectly sane image enters rolling reboot mode in case
some data change triggered a bug which prevents the normal startup and
causes a reset.
The most likely task causing in in case of cr50 would be the tpm task.
Let's add another check of the restart counter: should it reach the
value of 50, do not start the TPM task.
BRANCH=none
BUG=chrome-os-partner:55708
TEST=with this code plus an unaligned access introduced in tpm
initialization sequence in both RW_A and RW_B, program the full
image on the dev board.
Observe the device reset 50 time is rapid succession and then
stop with the following message on the console:
Bldr |511709
retry|50
Himg =4F992103..408D193E
Hfss =384E4655..EE13EBD0
Hinf =44D21600..B70529BD
jump @00044000
--- UART initialized after reboot ---
[Reset cause: rtc-alarm]
[Image: RW, cr50_v1.1.5044-8d6f7a2+ private-cr51:v0.0.68-633229c ...
+ cryptoc:v0.0.4-5319e83 2016-08-07 19:37:16 vbendeb@kvasha]
[0.004130 Inits done]
[0.006919 Active NVram partition set to 0]
Console is enabled; type HELP for help.
> system_rolling_reboot_suspected: roling reboots suspected. Try \
powercycling to clear
this condition.
[0.010502 Task 2 (TPM) exited!]
Change-Id: I6b08c5c1a02da9edf9bdf394e57cc56d2e595ad1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366892
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The nvmem space defined in the ec code base for the cr50 board is used
by the TPM2 library, which has its own nvram size definition. The two
definitions must match.
On top of the fact that the definitions are not locked to each other,
there is a third completely unrelated nvram size definition in
board/cr50/board.c.
This patch unifies nvmem size definitions between cr50 and tpm2
repositories by adding a compile time check for the size to be the
same on both sides.
Also, it turns out that two certificates (RSA and ECC) together do not
quite fit into the cr50 TPM nvram. Hence the total allocated nvmem
space is being increased to 20K (note that the actual nvram size
available to the TPM is less than half of this).
BRANCH=none
BUG=chrome-os-partner:55898
TEST=tpm does not lock up any more when 'tpm_client --own' is ran on the
Kevin-tpm2 command line
CQ-DEPEND=CL:367010
Change-Id: I20b4f54118bd2fa12e5bd5741d6c58fbe91f65d1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366796
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Servo_micro sets usb config maxpower to 100mA.
Servo_v4 is set to self powered as it's powered by a
shared vbus and not be the bub it's connected to.
cr50 is self powered as no power is transmitted as part of CCD.
* Add CONFIG_USB_MAXPOWER_MA to define USB maximum power draw requested
per board.
* Add CONFIG_USB_SELF_POWERED to indicate that a device is not
powered by allocated USB power.
BUG=chromium:631302
TEST=lsusb reports 100mA bMaxPower (micro), Self powered (v4)
BRANCH=None
Change-Id: I79b8ce46f32d94f16104a4a8080104e30dce7f2c
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363153
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add a case statement to handle HCI commands.
Add a test commands.
Try to match the hcitool syntax, so the same commands
can be executed on a Linux host.
Added lcmd (long cmd) to pass more parameters in fewer arguments
BUG=None
BRANCH=None
TEST=Use HCI commands to configure an advertiser and listen for
it using `hcitool lescan` on the host.
Change-Id: Ie28038847c9549eb1c27a605aa0fbad5efd3b2c7
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362145
Commit-Ready: Dan Shi <dshi@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
I keep thinking this refers to "Embedded Controller" instead of
"Elliptic Curve Cryptography". Make it clearer.
There's no functional change, I'm just renaming a constant.
BUG=none
BRANCH=none
TEST=make buildall; run tests on Cr50 dev board
make -C test/tpm_test && sudo ./test/tpm_test/tpmtest.py
Change-Id: Iaf2e2839e88fdbbcb1a712934be56a0dd47e4a70
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366752
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
There are few reasons why the SoC may reboot which we haven't
been reporting (they just show up as "[Reset cause: other]").
This adds a bit of decoding to explain some of those "other"
reasons.
BUG=none
BRANCH=none
TEST=make buildall; try on Cr50
I tested one of the new reasons using "crash hang". It shows up
correctly as "{Reset cause: security]". I haven't specifically
tested all of the new reasons, but since this is basically just a
change to console message they should work too. I'll double-check
those cases once some blocking bugs are fixed.
Change-Id: I46daed29d7e37bda9034a3486127bed0ea25f803
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366400
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reef doesn't have the battery temperature sense pin connected to
the charger, hence reading the battery temperature from the battery
registers.
BUG=chrome-os-partner:55834
BRANCH=none
TEST=Using 'battery' & 'temps' console command verified,
temperature readings are same from both the commands.
Change-Id: I897e453296151f31344f3e0434202baa67c7025d
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/365970
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
There is just one version of Cr50 firmware for all boards
that it's used on. However, on some boards the AP communicates
to the TPM via a SPI interface (i.e. Kevin) and on others, the
AP communicates via an I2C interface (i.e. Reef). In order to
dynamically discover which interface to configure, there are
strapping resistors added to the board which enables the Cr50
to detect which configuration to implement.
This CL is a first pass and is only looking at DIOA1 which is
pulled high for SPI and pulled low for I2C configurations.
The strapping resistor should be read when the AP is in reset
prior to it attempting to drive any of the lines used for
strapping. To ensure this condition is met, Cr50 will only
check the strapping options following a POR (power on reset).
Once the configuration type is discovered, a 'long_life'
register is used to hold the result so that the result can
always be available. The long_life register contents remain
unchanged until a subsequent power down event.
BRANCH=none
BUG=chrome-os-partner:50728
TEST=manual
Tested on Kevin and Reef. Verfifed by reading the stored value
that the SPI configuraiton is detected for Kevin and the I2C
interface is detected on Reef. In addition, verified on Kevin
that the Cr50 FW version is correctly reported to the AP which
means that TPM register reads via the slave SPI are functioning.
Change-Id: Ibd7624ad8e3b4126f6346dce0bc72f62a3cc6d18
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363014
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
